ATSAML21

Part: ATSAML21J18B-AUT — Microchip (Atmel) SAM L21J

Type: ARM Cortex-M0+ Ultra Low-Power MCU

Description: 32-bit Arm Cortex-M0+ MCU at up to 48 MHz with up to 256 KB Flash and 40 KB SRAM, 1.62–3.63 V operation, in 64-pin packages.

Operating Conditions:

• Supply voltage: 1.62–3.63 V
• Operating temperature: -40 to 85 °C (suffix-dependent; -40 to 105 °C also listed for other grades)
• Max CPU clock: 48 MHz

Absolute Maximum Ratings:

• Max supply voltage (VDD): 3.8 V
• Max current into a VDD pin: 92 mA (max source 46 mA / sink 65 mA per GPIO cluster)
• Max current out of a GND pin: 130 mA
• Pin voltage: GND-0.6 V to VDD+0.6 V
• Storage temperature: -60 to 150 °C

Key Specs:

• CPU: Arm Cortex-M0+ up to 48 MHz (2.46 CoreMark/MHz)
• Memory: 32/64/128/256 KB Flash; 4/8/16/32 KB SRAM main plus 2/4/8/8 KB low-power SRAM
• ADC: 12-bit, 1 MSPS, up to 20 channels
• DAC: two 12-bit, 1 MSPS dual-output
• USB: full-speed 12 Mbps USB 2.0 host/device
• SERCOM: up to six, each configurable as USART, I2C (up to 3.4 MHz), SPI or LIN slave
• I/O: up to 51 programmable pins
• Touch: PTC with 169-channel capacitive touch and proximity sensing

Features:

• Idle, Stand-by, Backup and Off sleep modes with SleepWalking peripherals
• Static and dynamic power gating, battery backup support
• Embedded Buck/LDO regulator with on-the-fly selection
• Two performance levels
• 16-channel DMAC and 12-channel Event System
• Up to five 16-bit TCs and three TCCs (two 24-bit, one 16-bit)
• AES engine, TRNG, CRC-32, Configurable Custom Logic
• Three op-amps, two analog comparators
• Oscillators: XOSC, XOSC32K, OSC16M, DFLL48M, FDPLL96M
• Serial Wire Debug and Micro Trace Buffer
• 32-bit RTC with clock/calendar and watchdog timer

Applications:

• Ultra low-power battery-powered devices
• Capacitive touch and proximity sensing interfaces

Package:

• 64-pin TQFP, QFN, WLCSP (SAM L21J)
• Other family members: 48-pin TQFP/QFN, 32-pin TQFP/QFN

• Processor
• -Arm Cortex-M0+ CPU running at up to 48 MHz
• Single-cycle hardware multiplier
• Micro Trace Buffer
• Memories
• -32/64/128/256-KB in-system self-programmable Flash
• -1/2/4/8-KB Flash Read-While-Write section
• -4/8/16/32-KB SRAM main memory
• -2/4/8/8-KB SRAM low-power memory
• System
• -Power-on Reset (POR) and Brown-out Detection (BOD)
• -Internal and external clock options
• -External Interrupt Controller (EIC)
• -16 external interrupts
• -One non-maskable interrupt
• -Two-pin Serial Wire Debug (SWD) programming, testing, and debugging interface
• Low Power
• -Idle, Stand-by, Backup, and Off Sleep modes
• -SleepWalking peripherals
• -Static and Dynamic Power Gating Architecture
• -Battery backup support
• -Two performance levels
• -Embedded Buck/LDO regulator supporting on-the-fly selection
• Peripherals
• -16-channel Direct Memory Access Controller (DMAC)
• -12-channel Event System
• -Up to five 16-bit Timer/Counters (TC) including one low-power TC, each configurable as:
• 16-bit TC with two compare/capture channels
• 8-bit TC with two compare/capture channels
• 32-bit TC with two compare/capture channels, by using two TCs

The Pin Configuration register (PINCFGy) is used for additional I/O pin configuration. A pin can be set in a totempole, or pull configuration.

As pull configuration is done through the Pin Configuration register, all intermediate PORT states during switching of pin direction and pin values are avoided.

The I/O pin configurations are described further in this chapter, and summarized in Table 29-2.

Note: 1.These values are based on simulation. They are not covered by production test limits or characterization.

Stresses beyond those listed in Table 46-1 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 46-1. Absolute Maximum Ratings

1. Maximum source current is 46mA and maximum sink current is 65mA per cluster. A cluster is a group of GPIOs.

Also note that each VDD/GND pair is connected to two clusters, so current consumption through the pair will be a sum of the clusters' source/sink currents.

This device is sensitive to electrostatic discharges (ESD). Improper handling may lead to permanent performance degradation or malfunctioning. Handle the device following best practice ESD protection rules:

Be aware that the human body can accumulate charges large enough to impair functionality or destroy the device.

The following table summarizes the thermal resistance data depending on the package.

Table 50-1. Thermal Resistance Data