STM32U595QI/JI

Part: STM32U595QII6 — STMicroelectronics

Type: 32-bit Arm Cortex-M33 Microcontroller

Description: Ultra-low-power 32-bit Arm Cortex-M33 MCU operating up to 160 MHz (240 DMIPS) with TrustZone, FPU, up to 4 MB Flash, 2.5 MB SRAM, advanced 2D GPU, MIPI DSI, and integrated SMPS step-down converter.

Operating Conditions:

• Supply voltage: 1.71 to 3.6 V (V_DD)
• Operating temperature: -40 to +85 °C (suffix 6) / -40 to +125 °C (suffix 3)
• Maximum AHB/APB clock frequency: 160 MHz (Range 1)
• Analog supply voltage (V_DDA): 1.62 to 3.6 V (ADC used)

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V (V_DDX - V_SS)
• Max continuous current: 200 mA (total current into sum of all V_DD power lines)
• Max junction/storage temperature: 140 °C junction / -65 to +150 °C storage

Key Specs:

• Maximum Core Frequency: 160 MHz (AHB clock Range 1)
• Coremark Score: 655 CoreMark (4.09 CoreMark/MHz)
• Power Consumption: 18.5 μA/MHz Run mode at 3.3 V
• Power Consumption: 150 nA Shutdown mode, 195 nA Standby mode, 2 μA Stop 3 mode (40-Kbyte SRAM)
• Flash Memory: Up to 4 MB with ECC (2 banks read-while-write)
• SRAM: Up to 2514 KB (with SRAM3 ECC off)
• ADCs: 2x 14-bit ADC (2.5 Msps) + 1x 12-bit ADC (2.5 Msps, autonomous in Stop 2)
• DAC: 12-bit DAC (2 channels)

Features:

• Arm Cortex-M33 core with TrustZone, MPU, DSP, and FPU
• ART Accelerator with 32 KB ICACHE and 16 KB DCACHE1, plus 16 KB DCACHE2
• Neo-Chrom GPU (GPU2D), Chrom-ART Accelerator (DMA2D), and Chrom-GRC (GFXMMU)
• Embedded regulator (LDO) and SMPS step-down converter with voltage scaling
• Low-power background autonomous mode (LPBAM) functional down to Stop 2 mode
• MIPI DSI host controller with two DSI lanes up to 500 Mbit/s each and LTDC controller
• 2 Octo-SPI interfaces and 16-bit HSPI interface up to 160 MHz
• Cryptographic security: HASH hardware accelerator, TRNG (NIST SP800-90B), active tampers, and SFI

Applications:

• Wearables and smart devices
• Medical and healthcare equipment
• Industrial sensors and IoT endpoints
• Advanced GUI and smart display controllers

Package:

• LQFP64
• LQFP100
• UFBGA132
• LQFP144
• WLCSP150
• TFBGA169
• WLCSP208
• TFBGA216

• Neo-Chrom GPU (GPU2D) accelerating any angle rotation, scaling, and perspective correct texture mapping
• 16-Kbyte DCACHE2
• Chrom-ART Accelerator (DMA2D) for smooth motion and transparency effects
• Chrom-GRC (GFXMMU) allowing up to 20 % of graphic resources optimization
• MIPI ® DSI host controller with two DSI lanes running at up to 500 Mbit/s each
• LCD-TFT controller (LTDC)
• Digital camera interface

DS13633 Rev 2

Table 25. Legend/abbreviations used in the pinout table

Name	Name	Abbreviation	Definition
Pin name	Pin name	Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name	Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
		S	Supply pin
	type	I	Input only pin
		I/O	Input/output pin
		FT	5V-tolerant I/O
		TT	3.6V-tolerant I/O
		DSI	1.2 V I/O for DSI interface
		RST	Bidirectional reset pin with embedded weak pull-up resistor
		Option for TT or FT I/Os (1)	Option for TT or FT I/Os (1)
		_a	I/O, with analog switch function supplied by V DDA
		_c	I/O with USB Type-C power delivery function
	structure	_d	I/O with USB Type-C power delivery dead battery function
		_f	I/O, Fm+ capable
		_h	I/O with high-speed low-voltage mode
		_o	I/O with OSC32_IN/OSC32_OUT capability
		_p	I/O with differential clock capability CLKP/CLKN
		_s	I/O supplied only by V DDIO2
		_t	I/O with a function supplied by V SW
		_u	I/O, with USB function supplied by V DDUSB
		_v	I/O very high-speed capable
Notes	Notes	Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.	Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
	Alternate functions	Functions selected through GPIOx_AFR registers	Functions selected through GPIOx_AFR registers
	Additional functions	Functions directly selected/enabled through peripheral registers	Functions directly selected/enabled through peripheral registers

Table 25. Legend/abbreviations used in the pinout table

Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - LQFP64 SMPS	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - LQFP100 SMPS	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - UFBGA132 SMPS	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - LQFP144 SMPS WLCSP150 SMPS	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - WLCSP150 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - TFBGA169 SMPS	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - WLCSP208 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - TFBGA216 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - LQFP64	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - LQFP100	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - UFBGA132 LQFP144	Table 26. STM32U59xxx pin/ball definitions (1) - Pin number - TFBGA169	Table 26. STM32U59xxx pin/ball definitions (1) - Pin name (function after reset)	Table 26. STM32U59xxx pin/ball definitions (1) - Pin type	Table 26. STM32U59xxx pin/ball definitions (1) - I/O structure	Table 26. STM32U59xxx pin/ball definitions (1) - Notes	Table 26. STM32U59xxx pin/ball definitions (1) - Alternate functions	Table 26. STM32U59xxx pin/ball definitions (1) - Additional functions	Table 26. STM32U59xxx pin/ball definitions (1)
-	1	B3 1	A13	D10	A1	G20	E5	-	1	B3 1	A1	PE2	I/O	FT_ha	-	TRACECLK, TIM3_ETR, SAI1_CK1, USART6_CK,LCD_R0, TSC_G7_IO1, LPGPIO1_P14, FMC_A23, SAI1_MCLK_A, EVENTOUT	-
-	2	A2 2	D10	G9	D3	E22	C3	-	2	A2 2	D3	PE3	I/O	FT_hat	-	TRACED0,TIM3_CH1, OCTOSPIM_P1_DQS, USART6_CTS, LCD_R1, TSC_G7_IO2, LPGPIO1_P15, FMC_A19, SAI1_SD_B, EVENTOUT	TAMP_IN6/ TAMP_OUT3
-	3	B2 3	F10	J9	C2	F21	B2	-	3	B2 3	C2	PE4	I/O	FT_hat	-	TRACED1,TIM3_CH2, SAI1_D2, MDF1_SDI3, USART6_RTS_DE, LCD_B0, TSC_G7_IO3, DCMI_D4/PSSI_D4, FMC_A20,SAI1_FS_A, EVENTOUT	WKUP1, TAMP_IN7/ TAMP_OUT8

• 112/386 Table 26. STM32U59xxx - Pin number - LQFP64 SMPS Table 26. STM32U59xxx - Pin number - LQFP100 SMPS Table 26. STM32U59xxx - Pin number - UFBGA132 SMPS Table 26. STM32U59xxx - Pin number - LQFP144 SMPS Table 26. STM32U59xxx - Pin number - WLCSP150 DSI SMPS TFBGA169 SMPS Table 26. STM32U59xxx - Pin number - WLCSP208 DSI SMPS Table 26. STM32U59xxx - Pin number - TFBGA216 DSI SMPS Table 26. STM32U59xxx - Pin number - LQFP64 Table 26. STM32U59xxx - Pin number - LQFP100 Table 26. STM32U59xxx - Pin number - UFBGA132 Table 26. STM32U59xxx - Pin number - LQFP144 Table 26. STM32U59xxx - Pin number - TFBGA169 Table 26. STM32U59xxx - definitions Pin name (function - after reset) Table 26. STM32U59xxx - Pin type Table 26. STM32U59xxx - I/O structure Table 26. STM32U59xxx - Notes Table 26. STM32U59xxx - Alternate functions Table 26. STM32U59xxx - Additional functions
• DS13633 - 4 A1 4 H10 F10 D2 G22 D3 - 4 A1 4 D2 PE5 I/O FT_hat - TRACED2,TIM3_CH3, SAI1_CK2, MDF1_CKI3, LCD_G0, TSC_G7_IO4, DCMI_D6/PSSI_D6, FMC_A21, SAI1_SCK_A, EVENTOUT WKUP2, TAMP_IN8/ TAMP_OUT7
• Rev 2 - 5 C2 5 E11 D12 E4 C24 E4 - 5 C2 5 E4 PE6 I/O FT_ht - TRACED3,TIM3_CH4, SAI1_D1, LCD_G1, DCMI_D7/PSSI_D7, FMC_A22, SAI1_SD_A, EVENTOUT WKUP3, TAMP_IN3/ TAMP_OUT6
• 1 6 B1 6 C13 C13 C1 B25 C2 1 6 B1 6 C1 VBAT S - - - -
• • • • • • • F2 B11 A1 - - - - F2 VSS S - - - -
• 2 7 C3 7 D12 E11 E3 D23 F4 2 7 C3 7 E3 PC13 I/O FT (2) (3) EVENTOUT WKUP2, RTC_TS/ RTC_OUT1, TAMP_IN1/T AMP_OUT2
• 3 8 C1 8 E13 A13 D1 C26 B1 3 8 C1 8 D1 PC14- OSC32_IN (PC14) I/O FT_o (2) (3) EVENTOUT OSC32_IN

Table 26. STM32U59xxx - LQFP64 SMPS	Table 26. STM32U59xxx - LQFP100 SMPS	Table 26. STM32U59xxx - UFBGA132 SMPS LQFP144 SMPS	Table 26. STM32U59xxx - WLCSP150 SMPS	Table 26. STM32U59xxx - WLCSP150 DSI SMPS	Table 26. STM32U59xxx - TFBGA169 SMPS	Table 26. STM32U59xxx - WLCSP208 DSI SMPS	Table 26. STM32U59xxx - TFBGA216 DSI SMPS	Table 26. STM32U59xxx - LQFP64	Table 26. STM32U59xxx - LQFP100	Table 26. STM32U59xxx - UFBGA132 LQFP144	Table 26. STM32U59xxx	Table 26. STM32U59xxx - TFBGA169	Table 26. STM32U59xxx - Pin name (function after reset)	Table 26. STM32U59xxx - Pin type	Table 26. STM32U59xxx - I/O structure	Table 26. STM32U59xxx - Notes	Table 26. STM32U59xxx - Alternate functions	Table 26. STM32U59xxx - Additional functions
4	9	D1 9	G13	B12	E1	D25	C1	4	9	D1	9	E1	PC15- OSC32_ OUT (PC15)	I/O	FT_o	(2) (3)	EVENTOUT	OSC32_OUT
-	-	D2 10	G11	G11	E2	H19	H3	-	-	D2	10	E2	PF0	I/O	FT_fh	-	I2C6_SDA, I2C2_SDA, OCTOSPIM_P2_IO0, USART6_TX,FMC_A0, EVENTOUT	-
-	-	E2 11	H12	H10	F3	H21	J4	-	-	E2	11	F3	PF1	I/O	FT_fh	-	I2C6_SCL, I2C2_SCL, OCTOSPIM_P2_IO1, USART6_RX, FMC_A1, EVENTOUT	-
-	-	E1 12	J13	F12	F4	J20	J3	-	-	E1 12	F4		PF2	I/O	FT_h	-	LPTIM3_CH2, I2C2_SMBA, OCTOSPIM_P2_IO2, USART6_CK, FMC_A2, EVENTOUT	WKUP8
-	-	D3 13	K12	L11	G5	K23	K4	-	-	D3 13		G5	PF3	I/O	FT_h	-	LPTIM3_IN1, ADF1_CCK0, OCTOSPIM_P2_IO3, MDF1_CCK0, USART6_CTS, UART5_TX, FMC_A3, EVENTOUT	-

114/386	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP100 SMPS UFBGA132 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP144 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP150 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP150 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin TFBGA169 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - number WLCSP208 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA216 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP100	Table 26. STM32U59xxx pin/ball definitions (continued) - UFBGA132 LQFP144	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA169	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin after	Table 26. STM32U59xxx pin/ball definitions (continued) - name (function reset)	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin type	Table 26. STM32U59xxx pin/ball definitions (continued) - I/O structure	Table 26. STM32U59xxx pin/ball definitions (continued) - Notes	Table 26. STM32U59xxx pin/ball definitions (continued) - Alternate functions	Table 26. STM32U59xxx pin/ball definitions (continued) - Additional functions
DS13633	-	- E3	14	J11	N11	G6	J22	K3	-	-	E3	14	G6	PF4	I/O	FT_hvp	-	LPTIM3_ETR, ADF1_SDI0, OCTOSPIM_P2_CLK, MDF1_SDI0, USART6_RTS_DE, UART5_RX, FMC_A4, EVENTOUT	-
Rev 2	-	- F2	15	L11	R11	G4	K21	L2	-	-	F2	15	G4	PF5	I/O	FT_hvp	-	LPTIM3_CH1, OCTOSPIM_P2_NCLK , MDF1_CKI0, FMC_A5, EVENTOUT	-
	-	10 F6	16	F12	-	H2	B15	A15	-	10	F6	16	H2	VSS	S	-	-	-	-
	-	11 F7	17	L13	A11	G1	L26	F5	-	11	F7	17	G1	VDD	S	-	-	-	-
	-	- -	18	N11	J11	H6	J16	M2	-	-	-	18	H6	PF6	I/O	FT_h	-	TIM5_ETR,TIM5_CH1, DCMI_D12/PSSI_D12, OCTOSPIM_P2_NCS, OCTOSPIM_P1_IO3, SAI1_SD_B, EVENTOUT	-
	-	- -	19	N13	K10	G2	J14	L3	-	-	-	19	G2	PF7	I/O	FT_h	-	TIM5_CH2, FDCAN1_RX, OCTOSPIM_P1_IO2, SAI1_MCLK_B, EVENTOUT	-

LQFP64 SMPS - -	LQFP100 SMPS - -	UFBGA132 SMPS - -	LQFP144 SMPS WLCSP150 SMPS - 20 - 21 - 22	WLCSP150 DSI SMPS - P10 - P12 - R11	TFBGA169 SMPS - M10 F1 - L9 - K8	WLCSP208 DSI SMPS - K19 - G3 L20 - H4 L22	TFBGA216 DSI SMPS - M3 - L4 - L1	LQFP64 - -	LQFP100 - -	UFBGA132 LQFP144 - -	20 - 21 - 22	TFBGA169 - F1 - G3 - H4	Pin name (function after reset) - PF8 - PF9 - PF10	Pin type - I/O	I/O structure - FT_h - FT_hv	Notes - -	Alternate functions - TIM5_CH3, PSSI_D14, FDCAN1_TX, OCTOSPIM_P1_IO0, SAI1_SCK_B, EVENTOUT - TIM5_CH4, PSSI_D15, OCTOSPIM_P1_IO1, SAI1_FS_B, TIM15_CH1, EVENTOUT - OCTOSPIM_P1_CLK, PSSI_D15, MDF1_CCK1, DCMI_D11/PSSI_D11, DSI_TE, SAI1_D3, TIM15_CH2, EVENTOUT	Additional functions - -
5	12	F1	23	R13	W13	H1 M23		N1 5	12				PH0- OSC_IN (PH0)	I/O	FT	-	EVENTOUT	OSC_IN
			24	U13	V12	J1	M25	6	13	F1	23	H1	PH1- OSC_OUT	I/O	FT	-	EVENTOUT	OSC_OUT
6	13	G1						N2		G1	24	J1	(PH1)
7	14	G2	25	T12	U11	H3 M21	R2	7	14	G2	25	H3	NRST	I-O	RST	-	-	-

116/386 Table 26. STM32U59xxx - LQFP64 SMPS	116/386 Table 26. STM32U59xxx - LQFP100 SMPS	116/386 Table 26. STM32U59xxx - UFBGA132 SMPS	116/386 Table 26. STM32U59xxx - LQFP144 SMPS WLCSP150 SMPS	116/386 Table 26. STM32U59xxx - WLCSP150 DSI SMPS	116/386 Table 26. STM32U59xxx - TFBGA169 SMPS	116/386 Table 26. STM32U59xxx - WLCSP208 DSI SMPS	116/386 Table 26. STM32U59xxx - TFBGA216 DSI SMPS	116/386 Table 26. STM32U59xxx - LQFP64	116/386 Table 26. STM32U59xxx - LQFP100	116/386 Table 26. STM32U59xxx - UFBGA132 LQFP144	116/386 Table 26. STM32U59xxx - TFBGA169	116/386 Table 26. STM32U59xxx - Pin name (function after reset)	116/386 Table 26. STM32U59xxx - Pin type	116/386 Table 26. STM32U59xxx	116/386 Table 26. STM32U59xxx - I/O structure	116/386 Table 26. STM32U59xxx - Notes Alternate	116/386 Table 26. STM32U59xxx - functions	116/386 Table 26. STM32U59xxx - Additional functions
8	15	H2	26 N9	P10	J2	K17	P2	8	15 H2	26	J2		PC0	I/O	FT_fha	-	LPTIM1_IN1, OCTOSPIM_P1_IO7, I2C3_SCL(boot), SPI2_RDY, MDF1_SDI4, USART6_CTS, LPUART1_RX, SDMMC1_D5, SAI2_FS_A, LPTIM2_IN1, EVENTOUT	ADC1_IN1, ADC2_IN1, ADC4_IN1
9	16	G3	27 M8	L7	J3	K15	M1	9	16	G3 27		J3	PC1	I/O	FT_fhav	-	TRACED0, LPTIM1_CH1, SPI2_MOSI, I2C3_SDA(boot), MDF1_CKI4, USART6_CK, LPUART1_TX, OCTOSPIM_P1_IO4, SDMMC2_CK, SAI1_SD_A, EVENTOUT	ADC1_IN2, ADC2_IN2, ADC4_IN2
Table 26. STM32U59xxx - LQFP64 SMPS	Table 26. STM32U59xxx - LQFP100 SMPS	Table 26. STM32U59xxx - UFBGA132 SMPS LQFP144 SMPS	Table 26. STM32U59xxx - WLCSP150 SMPS	Table 26. STM32U59xxx - WLCSP150 DSI SMPS	Table 26. STM32U59xxx - TFBGA169 SMPS	Table 26. STM32U59xxx - WLCSP208 DSI SMPS	Table 26. STM32U59xxx - TFBGA216 DSI SMPS	Table 26. STM32U59xxx - LQFP64	Table 26. STM32U59xxx - LQFP100	Table 26. STM32U59xxx - UFBGA132 LQFP144	Table 26. STM32U59xxx	Table 26. STM32U59xxx - TFBGA169	Table 26. STM32U59xxx - Pin name (function after reset)	Table 26. STM32U59xxx - Pin type	Table 26. STM32U59xxx - I/O structure	Table 26. STM32U59xxx - Notes	Table 26. STM32U59xxx - Alternate functions	Table 26. STM32U59xxx - Additional functions
10	17	F3 28	V12	Y12	J4	L18	P1	10	17	F3	28	J4	PC2	I/O	FT_ha	-	LPTIM1_IN2, SPI2_MISO, MDF1_CCK1, USART6_RX, OCTOSPIM_P1_IO5, LPGPIO1_P5, EVENTOUT	ADC1_IN3, ADC2_IN3, ADC4_IN3
11	18	F4 29	U11	T10	K1	M19	N3	11	18	F4	29	K1	PC3	I/O	FT_ha	-	LPTIM1_ETR, LPTIM3_CH1, SAI1_D1, SPI2_MOSI, USART6_TX, OCTOSPIM_P1_IO6, SAI1_SD_A, LPTIM2_ETR, EVENTOUT	ADC1_IN4, ADC2_IN4, ADC4_IN4
12	19	H1 30	W13	AA13	K2	N26	K6	12	19	H1	30	K2	VSSA	S	-	-	-	-
-	-	- -	-	-	-	N24	K5	-	20	-	31	-	VREF-	S	-	-	-	-
-	20	J1 31	Y12	AB12	L1	P25	L5	-	21	J1	32	L1	VREF+	S	-	-	-	VREFBUF _OUT
13	21	K1 32	AA13	AC13	L2	R26	L6	13	22	K1	33	L2	VDDA	S	-	-	-	-

	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx	Table 26. STM32U59xxx
118/386	LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	Pin TFBGA169 SMPS	number WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132 LQFP144	pin/ball TFBGA169	definitions Pin name (function after reset)	Pin type	(continued) I/O structure	Notes	Alternate functions	Additional functions
DS13633	14	22	J2 33	T10	W11	K3	N22	N4	14	23	J2	34 K3	PA0	I/O	FT_hat	-	TIM2_CH1,TIM5_CH1, TIM8_ETR,SPI3_RDY, USART2_CTS, UART4_TX, OCTOSPIM_P2_NCS, SDMMC2_CMD, AUDIOCLK, TIM2_ETR, EVENTOUT	OPAMP1 _VINP, ADC1_IN5, ADC2_IN5, WKUP1, TAMP_IN2/T AMP_OUT1
Rev 2	-	-	H3 -	-	-	M1	-	R3	-	-	H3	- M1	OPAMP1_V INM	I	TT	-	-	-
	15	23	G4 34	W11	V10	L3	L16	P3	15	24	G4	35 L3	PA1	I/O	FT_hat	-	LPTIM1_CH2, TIM2_CH2,TIM5_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, UART4_RX, OCTOSPIM_P1_DQS, LPGPIO1_P0, TIM15_CH1N, EVENTOUT	OPAMP1 _VINM, ADC1_IN6, ADC2_IN6, WKUP3, TAMP_IN5/ TAMP_OUT4

Pinout, pin description and alternate functions

LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132 LQFP144	TFBGA169	Pin after	name (function reset)		I/O structure	Pin type Notes	Alternate functions	Additional functions
16	24	K2	35 R9	R9	M2	M17	M4	16	25	K2 36		M2	PA2	I/O	FT_ha	-	TIM2_CH3,TIM5_CH3, SPI1_RDY, USART2_TX(boot), LPUART1_TX, OCTOSPIM_P1_NCS, UCPD1_FRSTX1, TIM15_CH1, EVENTOUT	COMP1 _INP3, ADC1_IN7, ADC2_IN7, WKUP4/ LSCO
17	25	L1	36 V10	N9	N2	P23	P4	17	26	L1	37	N2	PA3	I/O	TT_hav	-	TIM2_CH4,TIM5_CH4, SAI1_CK1, USART2_RX(boot), LPUART1_RX, OCTOSPIM_P1_CLK, LPGPIO1_P1, SAI1_MCLK_A, TIM15_CH2, EVENTOUT	OPAMP1 _VOUT, ADC1_IN8, ADC2_IN8, WKUP5
18	26	G7	37 AC13	AB10	M3	B23	E10	18	27	G7	38	M3	VSS	S	-	-	-	-
19	27	G6	38 AB12	A3	N3	T25	F8	19	28	G6	39	N3	VDD	S	-	-	-	-
20	28	L3	39 P8	M8	N1	N20	M5	20	29	L3	40	N1	PA4	I/O	TT_ha	-	OCTOSPIM_P1_NCS, SPI1_NSS(boot), SPI3_NSS, USART2_CK, DCMI_HSYNC/PSSI_D E, SAI1_FS_B, LPTIM2_CH1, EVENTOUT	ADC1_IN9, ADC2_IN9, ADC4_IN9, DAC1_OUT1 , WKUP2

	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386	120/386
	LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
DS13633	21	29 M1	40	AA11	AA11	K4	P21	R4	21	30	41	K4	PA5	I/O	TT_a	-	CSLEEP, TIM2_CH1, TIM2_ETR, TIM8_CH1N, PSSI_D14, SPI1_SCK(boot), USART3_RX, LPTIM2_ETR, EVENTOUT	ADC1_IN10, ADC2_IN10, ADC4_IN10, DAC1_OUT2 , WKUP6
Rev 2	22	30	L2 41	U9	U9	N4	N18	P5	22	31		42	N4 PA6	I/O	FT_ha	-	CDSTOP, TIM1_BKIN, TIM3_CH1, TIM8_BKIN, DCMI_PIXCLK/PSSI_P DCK, SPI1_MISO(boot), USART3_CTS, LPUART1_CTS, OCTOSPIM_P1_IO3, LPGPIO1_P2, TIM16_CH1, EVENTOUT	OPAMP2 _VINP, ADC1_IN11, ADC2_IN11, ADC4_IN11, WKUP7
	-	- M2	-	-	-	H5	-	N5	-	-	-	H5	OPAMP2 _VINM	I	TT	-	-	-

Pinout, pin description and alternate functions

						Table	26.		STM32U59xxx			pin/ball definitions		(continued)
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132 LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
23	31	K3 42	Y10	P8	J5	R22	R5	23	32	K3 43	J5	PA7	I/O	FT_fha	-	SRDSTOP, TIM1_CH1N, TIM3_CH2, TIM8_CH1N, I2C3_SCL, SPI1_MOSI(boot), USART3_TX, OCTOSPIM_P1_IO2, LPTIM2_CH2, TIM17_CH1, EVENTOUT	OPAMP2 _VINM, ADC1_IN12, ADC2_IN12, ADC4_IN20, WKUP8
-	-	M3 -	AC11	T8	L4	T23	R6	24	33	M3	44 L4	PC4	I/O	FT_ha	-	I2C6_SMBA, USART3_TX, OCTOSPIM_P1_IO7, EVENTOUT	COMP1 _INM2, ADC1_IN13, ADC2_IN13, ADC4_IN22
-	-	J3 -	N7	N7	M4	P19	P6	25	34	J3 45	M4	PC5	I/O	FT_at	-	TIM1_CH4N,SAI1_D3, PSSI_D15, USART3_RX, EVENTOUT	COMP1 _INP1, ADC1_IN14, ADC2_IN14, ADC4_IN23, WKUP5, TAMP_IN4/T AMP_OUT5

122/386	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64 SMPS LQFP100 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - UFBGA132 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP144 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP150 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP150 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin TFBGA169 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - number WLCSP208 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA216 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP100	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP144	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA169	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin name (function after	Table 26. STM32U59xxx pin/ball definitions (continued) - reset)	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin type I/O structure	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued) - Notes Alternate	Table 26. STM32U59xxx pin/ball definitions (continued) - functions	Table 26. STM32U59xxx pin/ball definitions (continued) - Additional functions
DS13633 Rev	24	32 M4	43	T8	Y10	K5	H13	N6	26	35	46	K5		PB0	I/O	TT_ha	-	TIM1_CH2N, TIM3_CH3, TIM8_CH2N, LPTIM3_CH1, SPI1_NSS, USART3_CK, OCTOSPIM_P1_IO1, LPGPIO1_P9, COMP1_OUT, AUDIOCLK, EVENTOUT	OPAMP2 _VOUT, ADC1_IN15, ADC2_IN15, ADC4_IN18
2	25	33 L4	44	W9	W9	N5	L14	M6	27	36	47		N5	PB1	I/O	FT_ha	-	TIM1_CH3N, TIM3_CH4, TIM8_CH3N, LPTIM3_CH2, MDF1_SDI0, USART3_RTS_DE, LPUART1_RTS_DE, OCTOSPIM_P1_IO0, LPGPIO1_P3, LPTIM2_IN1, EVENTOUT	COMP1 _INM1, ADC1_IN16, ADC2_IN16, ADC4_IN19, WKUP4

Table 26. STM32U59xxx - LQFP64 SMPS	Table 26. STM32U59xxx - LQFP100 SMPS	Table 26. STM32U59xxx - UFBGA132 SMPS	Table 26. STM32U59xxx - LQFP144 SMPS WLCSP150 SMPS	Table 26. STM32U59xxx - WLCSP150 DSI SMPS	Table 26. STM32U59xxx - TFBGA169 SMPS	Table 26. STM32U59xxx - WLCSP208 DSI SMPS	Table 26. STM32U59xxx - TFBGA216 DSI SMPS	Table 26. STM32U59xxx - LQFP64	Table 26. STM32U59xxx - LQFP100	Table 26. STM32U59xxx - UFBGA132	Table 26. STM32U59xxx - LQFP144	Table 26. STM32U59xxx - TFBGA169	Table 26. STM32U59xxx - Pin name (function after reset)	Table 26. STM32U59xxx - Pin type	Table 26. STM32U59xxx - I/O structure	Table 26. STM32U59xxx - Notes	Table 26. STM32U59xxx - Alternate functions	Table 26. STM32U59xxx - Additional functions
26	34	K4 45	AB10	M6	L5	M15	R7	28	37	K4	48	L5	PB2	I/O	FT_hat	-	LPTIM1_CH1, TIM8_CH4N, I2C3_SMBA, SPI1_RDY, MDF1_CKI0, LCD_B1, OCTOSPIM_P1_DQS, UCPD1_FRSTX1, EVENTOUT	COMP1 _INP2, ADC1_IN17, ADC2_IN17, WKUP1, RTC_OUT2
-	-	K5	46 R7	R7	M5	N16	P7	-	-	K5	49	M5	PF11	I/O	FT_hv	-	OCTOSPIM_P1_NCLK , LCD_DE, DCMI_D12/PSSI_D12, DSI_TE, LPTIM4_IN1, EVENTOUT	-
-	-	L5 47	V8	V8	K6	T21	N7	-	-	L5	50	K6	PF12	I/O	FT_h	-	OCTOSPIM_P2_DQS, LCD_B0, FMC_A6, LPTIM4_ETR, EVENTOUT	-
-	-	-	48 AA9	AB8	M7	B5	F10	-	-	-	51	M7	VSS	S	-	-	-	-
-	-	-	49 AC9	A7	N7	T19	J5	-	-	-	52	N7	VDD	S	-	-	-	-
-	-	M5	50 P6	AA9	M6	P17	M7	-	-	M5	53	M6	PF13	I/O	FT_h	-	I2C4_SMBA, LCD_B1, UCPD1_FRSTX2, FMC_A7, LPTIM4_OUT, EVENTOUT	-

	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued)
124/386	LQFP64 SMPS	LQFP100 SMPS UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	Pin TFBGA169 SMPS	number WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132 LQFP144	TFBGA169	Pin (function after	name reset)	Pin type I/O structure		Notes	Alternate functions	Additional functions
	-	- J5	51	U7	Y8	L6	K13	R8	-	-	J5 54		L6	PF14	I/O	FT_fha	-	I2C4_SCL, LCD_G0, TSC_G8_IO1, FMC_A8, EVENTOUT	ADC4_IN5
	-	- L6	52	Y8	U7	N6	R18	P8	-	-	L6	55	N6	PF15	I/O	FT_fha	-	I2C4_SDA, LCD_G1, TSC_G8_IO2, FMC_A9, EVENTOUT	ADC4_IN6
DS13633 Rev	-	- M6	53	T6	P6	J6	H11	R9	-	-	M6	56	J6	PG0	I/O	FT_ha	-	OCTOSPIM_P2_IO4, TSC_G8_IO3, FMC_A10, EVENTOUT	ADC4_IN7
2	-	- K6	54	W7	W7	H7	J12	N8	-	-	K6 57		H7	PG1	I/O	FT_ha	-	OCTOSPIM_P2_IO5, TSC_G8_IO4, FMC_A11, EVENTOUT	ADC4_IN8
	-	35 K7	55	AB8	T6	L7	L12	N9	-	38	K7 58		L7	PE7	I/O	FT_h	-	TIM1_ETR, MDF1_SDI2, LCD_B6, FMC_D4, SAI1_SD_B, EVENTOUT	WKUP6
	-	36 J6	56	V6	AA7	K7	N14	M8	-	39	J6	59	K7	PE8	I/O	FT_h	-	TIM1_CH1N, MDF1_CKI2, LCD_B7, FMC_D5, SAI1_SCK_B, EVENTOUT	WKUP7

Table 26. STM32U59xxx - LQFP64 SMPS	Table 26. STM32U59xxx - LQFP100 SMPS	Table 26. STM32U59xxx - UFBGA132 SMPS LQFP144 SMPS	Table 26. STM32U59xxx - WLCSP150 SMPS	Table 26. STM32U59xxx - WLCSP150 DSI SMPS	Table 26. STM32U59xxx - TFBGA169 SMPS	Table 26. STM32U59xxx - WLCSP208 DSI SMPS	Table 26. STM32U59xxx - TFBGA216 DSI SMPS	Table 26. STM32U59xxx - LQFP64	Table 26. STM32U59xxx - LQFP100	Table 26. STM32U59xxx - UFBGA132 LQFP144	Table 26. STM32U59xxx - TFBGA169	Table 26. STM32U59xxx - Pin after	Table 26. STM32U59xxx - name (function reset)	Table 26. STM32U59xxx	Table 26. STM32U59xxx - I/O structure	Table 26. STM32U59xxx - Pin type Notes	Table 26. STM32U59xxx - Alternate functions	Table 26. STM32U59xxx - Additional functions
-	37	M7 57	U5	V6	J7	T17	P9	-	40	M7	60	J7	PE9	I/O	FT_hv	-	TIM1_CH1, ADF1_CCK0, MDF1_CCK0, LCD_G2, OCTOSPIM_P1_NCLK , FMC_D6, SAI1_FS_B, EVENTOUT	-
-	-	- 58	AA7	C11	-	E4	F6	-	-	-	61	-	VSS	S	-	-	-	-
-	-	J4 59	AC7	AC1	-	T15	L7	-	-	J4	62	-	VDD	S	-	-	-	-
-	38	J7 60	Y6	R5	H8	M13	P10	-	41	J7	63	H8	PE10	I/O	FT_hav	-	TIM1_CH2N, ADF1_SDI0, MDF1_SDI4, LCD_G3, TSC_G5_IO1, OCTOSPIM_P1_CLK, FMC_D7, SAI1_MCLK_B, EVENTOUT	-
-	39	L7 61	W5	U5	M8	P15	P11	-	42	L7	64	M8	PE11	I/O	FT_ha	-	TIM1_CH2,SPI1_RDY, MDF1_CKI4, LCD_G4, TSC_G5_IO2, OCTOSPIM_P1_NCS, FMC_D8, EVENTOUT	-

126/386 - LQFP64 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - LQFP100 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - UFBGA132 SMPS LQFP144 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - WLCSP150 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - WLCSP150 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - TFBGA169 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - WLCSP208 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - TFBGA216 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - LQFP64	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - LQFP100	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number - UFBGA132 LQFP144	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin number	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA169	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin name (function after reset)	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin type	Table 26. STM32U59xxx pin/ball definitions (continued) - I/O structure	Table 26. STM32U59xxx pin/ball definitions (continued) - Notes	Table 26. STM32U59xxx pin/ball definitions (continued) - Alternate functions	Table 26. STM32U59xxx pin/ball definitions (continued) - Additional functions
-		40 J8	62	V4	Y6	N8	R14	N11	-	43	J8	65	N8	PE12	I/O	FT_ha	-	TIM1_CH3N, SPI1_NSS, MDF1_SDI5, LCD_G5, TSC_G5_IO3, OCTOSPIM_P1_IO0, FMC_D9, EVENTOUT	-
DS13633 Rev 2 -		41 M8	63	Y4	AB6	L8	N12	M9	-	44	M8	66 L8		PE13	I/O	FT_ha	-	TIM1_CH3,SPI1_SCK, MDF1_CKI5, LCD_G6, TSC_G5_IO4, OCTOSPIM_P1_IO1, FMC_D10, EVENTOUT	-
-		42	K8 64	AB6	P4	K8	P13	R10	-	45	K8 67		K8	PE14	I/O	FT_h	-	TIM1_CH4, TIM1_BKIN2, SPI1_MISO, LCD_G7, OCTOSPIM_P1_IO2, FMC_D11, EVENTOUT	-
-		43	L8 65	AA5	T4	M9	R12	N10	-	46	L8	68	M9	PE15	I/O	FT_h	-	TIM1_BKIN, TIM1_CH4N, SPI1_MOSI, LCD_R2, OCTOSPIM_P1_IO3, FMC_D12, EVENTOUT	-

Pinout, pin description and alternate functions

Table 26. STM32U59xxx - SMPS - 27 - -	LQFP64 LQFP100 SMPS - 44 - 45	UFBGA132 SMPS - K9 - L9	LQFP144 SMPS - 66 - 67	WLCSP150 SMPS - W3 - AA3	WLCSP150 DSI SMPS TFBGA169 SMPS - W5 K9 - AA5	WLCSP208 DSI SMPS - T13 - L9	TFBGA216 DSI SMPS - N12 - R10 M10	LQFP64 - 29 - -	LQFP100 - 47 - -	UFBGA132 LQFP144 - K9 - L9	69 - -	TFBGA169 - K9 - L9	Pin name (function after reset) - PB10 - PB11	Pin type - I/O	I/O structure - FT_fhv - FT_fh	-	Notes Alternate functions - TIM2_CH3, LPTIM3_CH1, I2C4_SCL, I2C2_SCL(boot), SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, OCTOSPIM_P1_CLK, LPGPIO1_P4, COMP1_OUT, SAI1_SCK_A, EVENTOUT - TIM2_CH4,I2C4_SDA, I2C2_SDA(boot), SPI2_RDY, USART3_RX, LPUART1_TX, OCTOSPIM_P1_NCS, COMP2_OUT, EVENTOUT	Additional functions - WKUP8 - -
28	46	M10	68	AC5	AC5	N9	T11	R11 -	-	-	-	-	VLXSMPS	S	-	-	-	-
29	47	M9	69	AB4	AB4	N10	T9	R12 -	-	-	-	-	VDDSMPS	S	-	-	-	-
30	48	L10	70	AC3	AC3	M10 -	R8	P12 - -	- 48	-	-	-	VSSSMPS	S	- -	- -	-	-
-	-	-	-	-	-	-		30	-	L10	70	N11	VCAP	S	-	-	-	-
	49	M11	71	AB2	AB2	N11		-		-	-	-	VDD11	S			-	-
31							T3	R13

Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP100 SMPS UFBGA132 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP144 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP150 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP150 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA169 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP208 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA216 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP100	Table 26. STM32U59xxx pin/ball definitions (continued) - UFBGA132 LQFP144	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA169	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin name (function after reset)	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin type	Table 26. STM32U59xxx pin/ball definitions (continued) - I/O structure	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued) - Notes	Table 26. STM32U59xxx pin/ball definitions (continued) - Alternate functions	Table 26. STM32U59xxx pin/ball definitions (continued) - Additional functions
32	50 E9	72	AA1	C3	M11	F3	F7	31	49	E9 71		M11	VSS	S	-	-	-	-
33	51 D4	73	AC1	AC11	N12	P1	L8	32	50	D4	72	N12	VDD	S	-	-	-	-
-	-	- -	-	-	-	T1	-	-	-	-	-	-	VDD	S	-	-	-	-
-	-	L11 -	Y2	AA3	L10	T5	M11	33	51	L11 73	L10		PB12	I/O	FT_hav	-	TIM1_BKIN, I2C6_SMBA, I2C2_SMBA, SPI2_NSS(boot), MDF1_SDI1, USART3_CK, LPUART1_RTS_DE, TSC_G1_IO1, OCTOSPIM_P1_NCLK , SAI2_FS_A, TIM15_BKIN, EVENTOUT	-
34	52	K10 74	R5	Y4	N13	T7	M12	34	52	K10	74	N13	PB13	I/O	FT_fa	-	TIM1_CH1N, LPTIM3_IN1, I2C2_SCL, SPI2_SCK(boot), MDF1_CKI1, USART3_CTS, LPUART1_CTS, TSC_G1_IO2, SAI2_SCK_A, TIM15_CH1N, EVENTOUT	-

Pinout, pin description and alternate functions

Pinout, pin description and alternate functions

Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP100 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - UFBGA132 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP144 SMPS WLCSP150 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP150 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA169 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP208 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA216 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP100	Table 26. STM32U59xxx pin/ball definitions (continued) - UFBGA132 LQFP144	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA169	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin name (function after reset)	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin type	Table 26. STM32U59xxx pin/ball definitions (continued) - I/O structure	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued) - Notes	Table 26. STM32U59xxx pin/ball definitions (continued) - Alternate functions	Table 26. STM32U59xxx pin/ball definitions (continued) - Additional functions
35	53	K11	75 T4	V4	M12	R6	P13	35	53	K11 75	M12		PB14	I/O	FT_fda	-	TIM1_CH2N, LPTIM3_ETR, TIM8_CH2N, I2C2_SDA, SPI2_MISO(boot), MDF1_SDI2, USART3_RTS_DE, TSC_G1_IO3, SDMMC2_D0, SAI2_MCLK_A, TIM15_CH1, EVENTOUT	UCPD1_ DBCC2
36	54	K12	76 N5	Y2	L11	P11	R14	36	54	K12	76	L11	PB15	I/O	FT_c	(4)	RTC_REFIN, TIM1_CH3N, LPTIM2_IN2, TIM8_CH3N, SPI2_MOSI(boot), MDF1_CKI2, FMC_NBL1, SDMMC2_D1, SAI2_SD_A, TIM15_CH2, EVENTOUT	UCPD1_CC2 , WKUP7
-	-	-	- -	H12	-	G24	G5	-	-	- -		-	VDDDSI	S	-	-	-	-
-	-	-	- -	M12	-	J24	H5	-	-	- -	-		VDD11DSI	S	-	-	-	-
-	-	-	- -	E13	-	E26	G1	-	-	- -		-	DSI_D0P	I/O	DSI	-	-	-

LQFP64 SMPS	130/386 Table 26. STM32U59xxx - Pin number	130/386 Table 26. STM32U59xxx - Pin number - LQFP100 SMPS	130/386 Table 26. STM32U59xxx - Pin number - UFBGA132 SMPS LQFP144 SMPS	130/386 Table 26. STM32U59xxx - Pin number - WLCSP150 SMPS	130/386 Table 26. STM32U59xxx - Pin number - WLCSP150 DSI SMPS	130/386 Table 26. STM32U59xxx - Pin number - TFBGA169 SMPS	130/386 Table 26. STM32U59xxx - Pin number - WLCSP208 DSI SMPS	130/386 Table 26. STM32U59xxx - Pin number - TFBGA216 DSI SMPS	130/386 Table 26. STM32U59xxx - Pin number - LQFP64	130/386 Table 26. STM32U59xxx - Pin number - LQFP100	130/386 Table 26. STM32U59xxx - Pin number - UFBGA132	130/386 Table 26. STM32U59xxx - Pin number - LQFP144	130/386 Table 26. STM32U59xxx - TFBGA169	130/386 Table 26. STM32U59xxx - Pin name (function after reset)	130/386 Table 26. STM32U59xxx - Pin type	130/386 Table 26. STM32U59xxx - structure - I/O	130/386 Table 26. STM32U59xxx - Notes	130/386 Table 26. STM32U59xxx - Alternate functions	130/386 Table 26. STM32U59xxx - Additional functions
-	-	-	-	-	G13	-	F25	G2	-	-	-	-	-	DSI_D0N	I/O	DSI	-	-	-
-	-	-	-	-	K12	-	E24	G6	-	-	-	-	-	VSSDSI	S	-	-	-	-
-	-	-	-	-	-	-	H23	H6	-	-	-	-	-	VSSDSI	S	-	-	-	-
-	-	-	-	-	J13	-	G26	H1	-	-	-	-	-	DSI_CKP	I/O	DSI	-	-	-
	-	- -	-	-	L13	-	H25	J1	-	-	-	-	-	DSI_CKN	I/O	DSI	-	-	-
-	-	-	-	-	N13	-	J26	K2	-	-	-	-	-	DSI_D1P	I/O	DSI	-	-	-
-	-	-	-	-	R13	-	K25	K1	-	-	-	-	-	DSI_D1N	I/O	DSI	-	-	-
-	-	-	-	-	P12	-	F23	H2	-	-	-	-	-	VSSDSI	S	-	-	-	-
-	-	-	-	-	-	-	-	J2	-	-	-	-	-	VSSDSI	S	-	-	-	-
-	55	L12	77	W1	W3	L12	P9	N13	-	55	L12	77	L12	PD8	I/O	FT_h	-	USART3_TX,LCD_R3, DCMI_HSYNC/PSSI_D E, FMC_D13, EVENTOUT	-
-	56	J10	78	V2	U3	L13	P7	P15	-	56	J10	78	L13	PD9	I/O	FT_h	-	LPTIM2_IN2, USART3_RX,LCD_R4, DCMI_PIXCLK/PSSI_P DCK, FMC_D14, SAI2_MCLK_A, LPTIM3_IN1, EVENTOUT	-

Pinout, pin description and alternate functions

Table 26. STM32U59xxx - LQFP64 SMPS	Table 26. STM32U59xxx - LQFP100 SMPS	Table 26. STM32U59xxx - UFBGA132 SMPS LQFP144 SMPS	Table 26. STM32U59xxx - WLCSP150 SMPS	Table 26. STM32U59xxx - WLCSP150 DSI SMPS	Table 26. STM32U59xxx - TFBGA169 SMPS	Table 26. STM32U59xxx - WLCSP208 DSI SMPS	Table 26. STM32U59xxx - TFBGA216 DSI SMPS	Table 26. STM32U59xxx - LQFP64	Table 26. STM32U59xxx - LQFP100	Table 26. STM32U59xxx - UFBGA132 LQFP144	Table 26. STM32U59xxx - TFBGA169	Table 26. STM32U59xxx - Pin name (function after reset)	Table 26. STM32U59xxx - Pin type I/O structure	Table 26. STM32U59xxx	Table 26. STM32U59xxx - Notes	Table 26. STM32U59xxx - Alternate functions	Table 26. STM32U59xxx - Additional functions	Table 26. STM32U59xxx
-	57 M12	79	U3	W1	K11	P5	P14	-	57	M12 79	K11	PD10	I/O	FT_ha	-	LPTIM2_CH2, I2C5_SMBA, USART3_CK,LCD_R5, TSC_G6_IO1, FMC_D15, SAI2_SCK_A, LPTIM3_ETR, EVENTOUT	-
-	58	J11 80	P4	R3	M13	M11	L12	-	58	J11	80 M13	PD11	I/O	FT_ha	-	I2C4_SMBA, USART3_CTS, LCD_R6, TSC_G6_IO2, FMC_CLE/FMC_A16, SAI2_SD_A, LPTIM2_ETR, EVENTOUT	ADC4_IN15
-	59 J12	81	R3	T2	K10	L10	M13	-	59	J12 81	K10	PD12	I/O	FT_fha	-	TIM4_CH1, I2C4_SCL, USART3_RTS_DE, LCD_R7, TSC_G6_IO3, FMC_ALE/FMC_A17, SAI2_FS_A, LPTIM2_IN1, EVENTOUT	ADC4_IN16

132/386	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP100 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - UFBGA132 SMPS LQFP144 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP150 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP150 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA169 SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - WLCSP208 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - TFBGA216 DSI SMPS	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP64	Table 26. STM32U59xxx pin/ball definitions (continued) - LQFP100	Table 26. STM32U59xxx pin/ball definitions (continued) - UFBGA132 LQFP144	Table 26. STM32U59xxx pin/ball definitions (continued)	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin after TFBGA169	Table 26. STM32U59xxx pin/ball definitions (continued) - name (function reset)	Table 26. STM32U59xxx pin/ball definitions (continued) - Pin type	Table 26. STM32U59xxx pin/ball definitions (continued) - I/O structure	Table 26. STM32U59xxx pin/ball definitions (continued) - Notes	Table 26. STM32U59xxx pin/ball definitions (continued) - Alternate functions	Table 26. STM32U59xxx pin/ball definitions (continued) - Additional functions
DS13633 Rev 2	-	60	H11 82	U1	N3	K12	K11	N14	-	60	H11	82	K12	PD13	I/O	FT_fha	-	TIM4_CH2,I2C4_SDA, USART6_CTS, LCD_VSYNC, TSC_G6_IO4, LPGPIO1_P6, FMC_A18, LPTIM4_IN1, LPTIM2_CH1, EVENTOUT	ADC4_IN17
DS13633 Rev 2	-	-	- 83	T2	C7	J12	G4	F9	-	-	-	83	J12	VSS	S	-	-	-	-
DS13633 Rev 2	-	-	- 84	R1	AC9	A11	R2	L9	-	-	-	84	J13	VDD	S	-	-	-	-
DS13633 Rev 2	-	61	H10 85	N3	P2	J10	N10	N15	-	61	H10	85	J10	PD14	I/O	FT_h	-	TIM4_CH3, USART6_CK,LCD_B2, FMC_D0, LPTIM3_CH1, EVENTOUT	-
DS13633 Rev 2	-	62	H12 86	P2	R1	J11	K9	K12	-	62	H12	86	J11	PD15	I/O	FT_h	-	TIM4_CH4, USART6_RTS_DE, LCD_B3, FMC_D1, LPTIM3_CH2, EVENTOUT	-
	-	-	G10 87	N1	N1	K13	F9	G12	-	-	G10	87	K13	PG2	I/O	FT_hs	-	SPI1_SCK, FMC_A12, SAI2_SCK_B, EVENTOUT	-

The definition and values of output AC characteristics are given in Figure 35: Output AC characteristics definition and in the table below respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 32 .

Table 88. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode (1) , and FT_o I/Os) (2)(3)(4)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
00	Fmax	Maximum frequency all I/Os	C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	12.5
00	Fmax	Maximum frequency all I/Os	C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	5
00	Fmax	Maximum frequency all I/Os	C L = 50 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	1	MHz
00	Fmax	Maximum frequency all I/Os	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	12.5
00	Fmax	Maximum frequency all I/Os	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	5
00	Fmax	Maximum frequency all I/Os	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	1
00	t r /t f	Output rise and fall time all I/Os	C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	17	ns
00	t r /t f	Output rise and fall time all I/Os	C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	33	ns
00	t r /t f	Output rise and fall time all I/Os	C L = 50 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	85	ns
00	t r /t f	Output rise and fall time all I/Os	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	12.5	ns
00	t r /t f	Output rise and fall time all I/Os	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	25	ns
00	t r /t f	Output rise and fall time all I/Os	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	50	ns

Table 88. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode (1) , and FT_o I/Os) (2)(3)(4)

Table 88. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode (1) , and FT_o I/Os) (2)(3)(4) (continued)

Speed	Symbol	Conditions	Min	Max	Unit
01		C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	55	MHz
01		C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	12.5	MHz
01		C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	2.5	MHz
01	Fmax	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	55	MHz
01		C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	12.5	MHz
01		C L = 10 pF, 1.08 V ≤ V DDIOx ≤ <1.58 V	-	2.5	MHz
01	t r /t f	C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	5.8	ns
01	t r /t f	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	10	ns
01	t r /t f	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	18	ns
01	t r /t f	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	4.2	ns
01	t r /t f	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	7.5	ns
01	t r /t f	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	12	ns
10	Fmax	C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	100 (5)	MHz
10	Fmax	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	33 (5)	MHz
10	Fmax	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	5	MHz
10	Fmax	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	133 (5)	MHz
10	Fmax	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	40 (5)	MHz
10	Fmax	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	5	MHz
10	t r /t f	C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	3.3 (5)	ns
10	t r /t f	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	6.0 (5)	ns
10	t r /t f	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	13.3	ns
10	t r /t f	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	2 (5)	ns
10	t r /t f	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	4.1 (5)	ns
10	t r /t f	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	9.2	ns
11	Fmax	C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	100 (5)	MHz
11	Fmax	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	33 (5)	MHz
11	Fmax	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	5
11	Fmax	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	133 (5)
11	Fmax	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	40 (5)
11	Fmax	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	5

Table 88. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode (1) , and FT_o I/Os) (2)(3)(4) (continued)

348

Table 88. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode (1) , and FT_o I/Os) (2)(3)(4) (continued)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
11 (cont'd)	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	140 (5)	MHz
11 (cont'd)	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	40 (5)	MHz
11 (cont'd)	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	5	MHz
11 (cont'd)	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	166 (5)	MHz
11 (cont'd)	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	50 (5)	MHz
11 (cont'd)	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	5	MHz
11 (cont'd)	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	3.3 (5)
11 (cont'd)	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	6.0 (5)
11 (cont'd)	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	13.3
11 (cont'd)	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	2.0 (5)
11 (cont'd)	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	4.1 (5)
11 (cont'd)	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	9.2
11 (cont'd)	t r /t f	Output rise and fall time FT_v and TT_v I/Os	C L = 30 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	2.5 (5)	ns
11 (cont'd)	t r /t f	Output rise and fall time FT_v and TT_v I/Os	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	5.0 (5)
11 (cont'd)	t r /t f	Output rise and fall time FT_v and TT_v I/Os	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	11
11 (cont'd)	t r /t f	Output rise and fall time FT_v and TT_v I/Os	C L = 10 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	1.66 (5)
11 (cont'd)	t r /t f	Output rise and fall time FT_v and TT_v I/Os	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	3.1 (5)
11 (cont'd)	t r /t f	Output rise and fall time FT_v and TT_v I/Os	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	7
Fm+	Fmax	Maximum frequency	C L = 550 pF, 1.08 V ≤ V DDIOx < 3.6 V	-	1	MHz
Fm+	t f	Output fall time (6)	C L = 100 pF, 1.58 V ≤ V DDIOx < 3.6 V	-	50	ns
Fm+	t f	Output fall time (6)	C L = 100 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	80	ns
Fm+	t f	Output fall time (6)	C L = 550 pF, 1.58 V ≤ V DDIOx < 3.6 V	-	100	ns
Fm+	t f	Output fall time (6)	C L = 550 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	220	ns

1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO port configuration register.

3. Specified by design. Not tested in production.

4. Compensation system enabled.

5. The fall time is defined between 70% and 30% of the output waveform accordingly to I 2 C specification.

Table 89. Output AC characteristics, HSLV ON (all I/Os except FT_c, FT_t in V BAT mode (1) , and FT_o I/Os) (2)(3)(4)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
00	Fmax	Maximum frequency	C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	10	MHz
00	Fmax	Maximum frequency	C L = 50 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	4	MHz
00	Fmax	Maximum frequency	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	15	MHz
00	Fmax	Maximum frequency	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	4	MHz
00	t r /t f	Output rise and fall time	C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	18	ns
00	t r /t f	Output rise and fall time	C L = 50 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	32	ns
00	t r /t f	Output rise and fall time	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	12	ns
00	t r /t f	Output rise and fall time	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	21	ns
01	Fmax	Maximum frequency	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	50	MHz
01	Fmax	Maximum frequency	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	10	MHz
01	Fmax	Maximum frequency	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	67	MHz
01	Fmax	Maximum frequency	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	10	MHz
01	t r /t f	Output rise and fall time	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	5.3	ns
01	t r /t f	Output rise and fall time	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	10.6	ns
01	t r /t f	Output rise and fall time	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	3.1	ns
01	t r /t f	Output rise and fall time	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	5.6	ns
10	Fmax	Maximum frequency	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	75 (5)	MHz
10	Fmax	Maximum frequency	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	15	MHz
10	Fmax	Maximum frequency	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	100 (5)	MHz
10	Fmax	Maximum frequency	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	15	MHz
10	t r /t f	Output rise and fall time	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	4.4 (5)	ns
10	t r /t f	Output rise and fall time	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	9.6	ns
10	t r /t f	Output rise and fall time	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	2.2 (5)	ns
10	t r /t f	Output rise and fall time	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	4.7	ns

Table 89. Output AC characteristics, HSLV ON (all I/Os except FT_c, FT_t in V BAT mode (1) , and FT_o I/Os) (2)(3)(4)

348

Table 89. Output AC characteristics, HSLV ON (all I/Os except FT_c, FT_t in V BAT mode (1) , and FT_o I/Os) (2)(3)(4) (continued)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
11	Fmax	Maximum frequency All I/Os except FT_c, FT_v, and TT_v	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	75 (5)
11	Fmax	Maximum frequency All I/Os except FT_c, FT_v, and TT_v	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	15
11	Fmax	Maximum frequency All I/Os except FT_c, FT_v, and TT_v	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	100 (5)
11	Fmax	Maximum frequency All I/Os except FT_c, FT_v, and TT_v	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	15	MHz
11	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	110 (5)
11	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	25
11	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	150 (5)
11	Fmax	Maximum frequency FT_v and TT_v I/Os	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	25
11	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	4.4 (5)	ns
11	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	9.6	ns
11	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V		2.2 (5)	ns
11	t r /t f	Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V		4.7	ns
11		Output rise and fall time FT_v and TT_v I/Os	C L = 30 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	3.0 (5)	ns
11		Output rise and fall time FT_v and TT_v I/Os	C L = 30 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	6.6	ns
11		Output rise and fall time FT_v and TT_v I/Os	C L = 10 pF, 1.58 V ≤ V DDIOx < 2.7 V		1.6 (5)	ns
11		Output rise and fall time FT_v and TT_v I/Os	C L = 10 pF, 1.08 V ≤ V DDIOx < 1.58 V	-	3.4	ns

1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO port configuration register.
3. Specified by design. Not tested in production.
4. Compensation system enabled.

Table 90. Output AC characteristics for FT_c I/Os (1)(2)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
00	Fmax	Maximum frequency	All I/Os, C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	10	MHz
00	Fmax	Maximum frequency	All I/Os, C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	5	MHz
00	t r /t f	Output rise and fall time	All I/Os, C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	33	ns
00	t r /t f	Output rise and fall time	All I/Os, C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	66	ns
01	Fmax	Maximum frequency	All I/Os, C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	25	MHz
01	Fmax	Maximum frequency	All I/Os, C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	10	MHz
01	t r /t f	Output rise and fall time	All I/Os, C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	13	ns
01	t r /t f	Output rise and fall time	All I/Os, C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	33	ns

Table 90. Output AC characteristics for FT_c I/Os (1)(2)

Table 90. Output AC characteristics for FT_c I/Os (1)(2) (continued)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
1x	Fmax	Maximum frequency	All I/Os, C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	40	MHz
1x	Fmax	Maximum frequency	All I/Os, C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	20	MHz
1x	t r /t f	Output rise and fall time	All I/Os, C L = 50 pF, 2.7 V ≤ V DDIOx ≤ 3.6 V	-	8	ns
1x	t r /t f	Output rise and fall time	All I/Os, C L = 50 pF, 1.58 V ≤ V DDIOx < 2.7 V	-	17	ns

Table 91. Output AC characteristics for FT_t I/Os in V BAT mode, and for FT_o I/Os (1)

Symbol	Parameter	Conditions	Min	Max	Unit
Fmax	Maximum frequency	C L = 50 pF, 2.7 V ≤ V SW ≤ 3.6 V	-	0.5	MHz
Fmax	Maximum frequency	C L = 50 pF, 1.58 V ≤ V SW < 2.7 V	-	0.25	MHz
t r /t f	Output rise and fall time	C L = 50 pF, 2.7 V ≤ V SW ≤ 3.6 V	-	400	ns
t r /t f	Output rise and fall time	C L = 50 pF, 1.58 V ≤ V SW < 2.7 V	-	900	ns

Figure 35. Output AC characteristics definition

Table 91. Output AC characteristics for FT_t I/Os in V BAT mode, and for FT_o I/Os (1)

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Stresses above the absolute maximum ratings listed in Table 29 , Table 30 , and Table 31 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 29. Voltage characteristics (1) (2)

Symbol	Ratings	Min	Max	Unit
V DDX - V SS	External main supply voltage (including V DDSMPS , V DDA , V DDUSB , V DDDSI , V BAT , V REF+ )	-0.3	4.0	V
V DDIOx (3) - V SS	I/O supply when HSLV = 0	-0.3	4.0	V
V DDIOx (3) - V SS	I/O supply when HSLV = 1	-0.3	2.75	V
V IN (4)	Input voltage on FT_xx pins except FT_c pins	V SS - 0.3	Min (min (V DD , V DDA , V DDUSB, V DDIO2 ) + 4.0, 6.0) (5)(6)	V
V IN (4)	Input voltage on FT_t pins in V BAT mode	V SS - 0.3	Min (min (V BAT , V DDA , V DDUSB, V DDIO2 ) + 4.0, 6.0) (5)(6)	V
V IN (4)	Input voltage on FT_c pins	V SS - 0.3	5.5	V
V IN (4)	Input voltage on any other pins	V SS - 0.3	4.0	V
V REF+ - V DDA	Allowed voltage difference for V REF+ > V DDA	-	0.4	V
| ∆ V DDx |	Variations between different VDDx power pins of the same domain	-	50.0	mV
|V SSx -V SS |	Variations between all the different ground pins (7)	-	50.0	mV

1. All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VDDDSI, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must always be connected to the external power supply, in the permitted range.
2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
3. VDDIO1 or V DDIO2 , V DDIO1 = V DD .
4. VIN maximum must always be respected. Refer to Table 30 for the maximum allowed injected current values.
5. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
6. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.
7. Including VREF- pin.

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Table 30. Current characteristics

Symbol	Ratings	Max	Unit
∑ IV DD	Total current into sum of all V DD power lines (source) (1)	200	mA
∑ IV SS	Total current out of sum of all V SS ground lines (sink) (1)	200	mA
IV DD	Maximum current into each VDD power pin (source) (1)	100	mA
IV SS	Maximum current out of each VSS ground pin (sink) (1)	100	mA
I IO	Output current sunk by any I/O and control pin	20	mA
I IO	Output current sourced by any I/O and control pin	20	mA
∑ I (PIN)	Total output current sunk by sum of all I/Os and control pins (2)	120	mA
∑ I (PIN)	Total output current sourced by sum of all I/Os and control pins (2)	120	mA
I INJ(PIN) (3)(4)	Injected current on FT_xx, TT_xx, RST pins	-5/+0	mA
∑ |I INJ(PIN) |	Total injected current (sum of all I/Os and control pins) (5)	±25	mA

Table 31. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature	140	°C

Table 31. Thermal characteristics

The maximum chip-junction temperature, T J max, in degrees Celsius, can be calculated using the following equation:

$$T_J\text{ max} = T_A\text{ max} + (P_D\text{ max} * \Theta_{JA})$$

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.

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