STM32U595VI

STM32U59xxx

Microcontroller

The STM32U595VI is a microcontroller from STMicroelectronics. STM32U59xxx. View the full STM32U595VI datasheet below including key specifications, electrical characteristics, absolute maximum ratings.

Manufacturer

STMicroelectronics

Key Specifications

Parameter	Value
Connectivity	CANbus, I2C, IrDA, LINbus, MMC/SD/SDIO, SAI, SmartCard, SPDIF, SPI, UART/USART, USB, USB OTG
Core Processor	ARM® Cortex®-M33
Core Size	32-Bit
Data Converters	A/D 24x12/14b SAR; D/A 2x12b
Mounting Type	Surface Mount
Number of I/O	110
Operating Temperature	-40°C ~ 85°C (TA)
Oscillator Type	External, Internal
Package / Case	132-UFBGA
Peripherals	Brown-out Detect/Reset, DMA, LCD, Motor Control PWM, POR, PWM, WDT
Flash Memory Size	2MB (2M x 8)
Program Memory Type	FLASH
RAM Size	2.5M x 8 B
Clock Speed	160MHz
Supplier Device Package	132-UFBGA (7x7)
Supply Voltage	1.71V ~ 3.6V

Overview

Part: STMicroelectronics STM32U59xxx

Type: Ultra-low-power Arm® Cortex®-M33 32-bit Microcontroller

Description: Ultra-low-power Arm® Cortex®-M33 32-bit MCU with TrustZone® and FPU, operating up to 160 MHz (240 DMIPS), featuring up to 4 MB Flash, 2.5 MB SRAM, LTDC, and MIPI® DSI.

Operating Conditions:

Supply voltage: 1.71 V to 3.6 V
Operating temperature: -40 °C to +125 °C
Max CPU frequency: 160 MHz

Absolute Maximum Ratings:

Max supply voltage: 4.0 V
Max continuous current: 120 mA (Total current into VDD_x)
Max junction/storage temperature: 150 °C

Key Specs:

Core: Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU
Max CPU frequency: 160 MHz (240 DMIPS)
Flash memory: Up to 4 Mbyte with ECC
SRAM: Up to 2.5 Mbyte (2514 Kbyte with SRAM3 ECC off)
Run mode current: 18.5 μA/MHz at 3.3 V
Stop 3 mode current: 8.2 μA with 2.5-Mbyte SRAM
Analog-to-Digital Converters: 2x 14-bit ADC 2.5-Msps, 1x 12-bit ADC 2.5-Msps
General-purpose I/Os: Up to 156 fast I/Os

Features:

Ultra-low-power with FlexPowerControl and various low-power modes (Shutdown, Standby, Stop 2, Stop 3)
Arm® TrustZone® security architecture with flexible life cycle scheme
Rich graphic features including Neo-Chrom GPU, Chrom-ART Accelerator, LTDC, and MIPI® DSI host controller
Embedded regulator (LDO) and SMPS step-down converter
Up to 25 communication peripherals including USB Type-C/PD, USB OTG HS, I2C, USART, SPI, CAN FD, SDMMC

Applications:

null

Package:

LQFP64
LQFP100
UFBGA132
LQFP144
WLCSP150
TFBGA169
WLCSP208
TFBGA216

Features

Includes ST state-of-the-art patented technology

Ultra-low-power with FlexPowerControl

1.71 V to 3.6 V power supply
- 40 °C to + 85/125 °C temperature range
Low-power background autonomous mode (LPBAM): autonomous peripherals with DMA, functional down to Stop 2 mode
VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM
150 nA Shutdown mode (24 wake-up pins)
195 nA Standby mode (24 wake-up pins)
480 nA Standby mode with RTC
2 μA Stop 3 mode with 40-Kbyte SRAM
8.2 μA Stop 3 mode with 2.5-Mbyte SRAM
4.65 μA Stop 2 mode with 40-Kbyte SRAM
17.5 μA Stop 2 mode with 2.5-Mbyte SRAM
18.5 μA/MHz Run mode at 3.3 V

Core

• Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU

Pin Configuration

Table 25. Legend/abbreviations used in the pinout table

Name	Abbreviation	Definition
Pin name		Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
	S	Supply pin
Pin type	I	Input only pin
	I/O	Input/output pin
	FT	5V-tolerant I/O
	TT	3.6V-tolerant I/O
	DSI	1.2 V I/O for DSI interface
	RST	Bidirectional reset pin with embedded weak pull-up resistor Option for TT or FT I/Os(

^1. The related I/O structures in the table below are a concatenation of various options. Examples: FT_hat, FT_fs, FT_u, TT_a.

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
-	1	B 3	1	A 1 3	D 1 0	A 1	G 2 0
-	2	A 2	2	D 1 0	G 9	D 3	E 2 2
-	3	B 2	3	F 1 0	J 9	C 2	F 2 1

							Tal	ole 26	. STN	/132U	59xxx	c pin/	ball d	efinitions ⁽¹⁾	(cor	ntinued)
					ı	Pin nu	ımber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
-	4	A1	4	H10	F10	D2	G22	D3	-	4	A1	4	D2	PE5	I/O	FT_hat
-	5	C2	5	E11	D12	E4	C24	E4	-	5	C2	5	E4	PE6	I/O	FT_ht
1	6	B1	6	C13	C13	C1	B25	C2	1	6	B1	6	C1	VBAT	S	-
-	-	-	-	-	-	F2	B11	A1	-	-	-	-	F2	VSS	S	-
2	7	C3	7	D12	E11	E3	D23	F4	2	7	C3	7	E3	PC13	I/O	FT
3	8	C1	8	E13	A13	D1	C26	B1	3	8	C1	8	D1	PC14- OSC32_IN (PC14)	I/O	FT_o

Ta b le 2 6. S T M 3 2 U 5 9x xx	( 1) in / ba l l de f in i t io p ns	( t in d ) co n ue
-------------------------------------------------------------------------	--------------------------------------------------------------------------------	-----------------------------------------

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
4	9	D 1	9	G 1 3	B 1 2	E 1	D 2 5
-	-	D 2	1 0	G 1 1	G 1 1	E 2	H 1 9
-	-	E 2	1 1	H 1 2	H 1 0	F 3	H 2 1
-	-	E 1	1 2	J 1 3	F 1 2	F 4	J 2 0
-	-	D 3	1 3	K 1 2	L 1 1	G 5	K 2 3

							Tal	ole 26	. STN	/132U	59xxx	pin/	ball d	efinitions ⁽¹⁾	(00)	ntinued)
					ı	Pin nu	ımber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
-	1	E3	14	J11	N11	G6	J22	K3	-	-	E3	14	G6	PF4	I/O	FT_hvp
-	-	F2	15	L11	R11	G4	K21	L2	-	-	F2	15	G4	PF5	I/O	FT_hvp
-	10	F6	16	F12	-	H2	B15	A15	-	10	F6	16	H2	VSS	S	-
-	11	F7	17	L13	A11	G1	L26	F5	-	11	F7	17	G1	VDD	S	-
-	-	-	18	N11	J11	H6	J16	M2	-	-	-	18	H6	PF6	I/O	FT_h
-	1	-	19	N13	K10	G2	J14	L3	1	-	-	19	G2	PF7	I/O	FT_h

S Ta b le 2 6. T M 3 2 U 5 9x xx	( 1) / f in ba l l de in i t io p ns	( ) t in d co n ue
-------------------------------------------------------------------------	--------------------------------------------------------------------------------	-----------------------------------------

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
-	-	-	2 0	1 0 P	1 0 M	1 F	1 9 K
-	-	-	2 1	P 1 2	L 9	G 3	L 2 0
-	-	-	2 2	R 1 1	K 8	H 4	L 2 2
5	1 2	F 1	2 3	R 1 3	W 1 3	H 1	M 2 3
6	1 3	G 1	2 4	U 1 3	V 1 2	J 1	M 2 5
7	1 4	G 2	2 5	T 1 2	U 1 1	H 3	M 2 1

Pinout, pin description and alternate functions

|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:--------------------------------|:---------|:--------------|:------|:--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Table 26. STM32U59xxx	pin/ball definitions ⁽¹⁾	(continued)
-----------------------	-------------------------------------	-------------

					F	Pin nu	mber					-				,
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
10	17	F3	28	V12	Y12	J4	L18	P1	10	17	F3	28	J4	PC2	I/O	FT_ha
11	18	F4	29	U11	T10	K1	M19	N3	11	18	F4	29	K1	PC3	I/O	FT_ha
12	19	H1	30	W13	AA13	K2	N26	K6	12	19	H1	30	K2	VSSA	S	1
-	-	-	-	-	-	-	N24	K5	-	20	-	31	-	VREF-	S	-
-	20	J1	31	Y12	AB12	L1	P25	L5	ı	21	J1	32	L1	VREF+	S	-
13	21	K1	32	AA13	AC13	L2	R26	L6	13	22	K1	33	L2	VDDA	S	-

									. STN	/132U	59xxx	c pin/	ball d	efinitions ⁽¹⁾	(coı	ntinued)			T
					ı	Pin nu	ımber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
14	22	J2	33	T10	W11	K3	N22	N4	14	23	J2	34	K3	PA0	I/O	FT_hat	-	TIM2_CH1, TIM5_CH1, TIM8_ETR, SPI3_RDY, USART2_CTS, UART4_TX, OCTOSPIM_P2_NCS, SDMMC2_CMD, AUDIOCLK, TIM2_ETR, EVENTOUT	OPAMP1 _VINP, ADC1_IN5, ADC2_IN5, WKUP1, TAMP_IN2/T AMP_OUT1
-	-	HЗ	-	-	-	M1	-	R3	-	-	HЗ	-	M1	OPAMP1_V INM	ı	TT	-	-	-
15	23	G4	34	W11	V10	L3	L16	P3	15	24	G4	35	L3	PA1	I/O	FT_hat	-	LPTIM1_CH2, TIM2_CH2, TIM5_CH2, I2C1_SMBA, SPI1_SCK, USART2_RTS_DE, UART4_RX, OCTOSPIM_P1_DQS, LPGPIO1_P0, TIM15_CH1N, EVENTOUT	OPAMP1 _VINM, ADC1_IN6, ADC2_IN6, WKUP3, TAMP_IN5/ TAMP_OUT4

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
1 6	2 4	K 2	3 5	R 9	R 9	M 2	M 1 7
1 7	2 5	L 1	3 6	V 1 0	N 9	N 2	P 2 3
1 8	2 6	G 7	3 7	A C 1 3	A B 1 0	M 3	B 2 3
1 9	2 7	G 6	3 8	A B 1 2	A 3	N 3	T 2 5
2 0	2 8	L 3	3 9	P 8	M 8	N 1	N 2 0

Pinout, pin description and alternate functions

							Tab	ole 26	. STN	/132U	59xxx	c pin/	ball d	efinitions ⁽¹⁾	(cor	ntinued)
					I	Pin nu	ımber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
21	29	M1	40	AA11	AA11	K4	P21	R4	21	30	M1	41	K4	PA5	I/O	TT_a
22	30	L2	41	U9	U9	N4	N18	P5	22	31	L2	42	N4	PA6	I/O	FT_ha
-	-	M2	_	-	-	H5 P in nu	- be m r	N5	-	-	M2	-	H5	OPAMP2 _VINM	I	TT
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W	S P M S I S D 6 1 2 A G B F T	4 6 P F Q L	0 0 1 P F Q L	2 3 1 A G B F U	4 4 1 P F Q L	9 6 1 A G B F T	P in na me ( fu ion t nc f te t ) a r r es e	e p y t n i P	e r u t c u r t s O I/
2 3	3 1	K 3	4 2	Y 1 0	P 8	J 5	R 2 2	R 5	2 3	3 2	K 3	4 3	J 5	P A 7	I / O	F T_ f ha
-	-	M 3	-	C A 1 1	T 8	L 4	T 2 3	R 6	2 4	3 3	M 3	4 4	L 4	C P 4	/ O I	F T_ ha
-	-	J 3	-	N 7	N 7	M 4	P 1 9	P 6	2 5	3 4	J 3	4 5	M 4	P C 5	I / O	F T_ t a

Pinout, pin description and alternate functions

						Pin nu	Tat		. STN	/132U	59xxx	c pin/	ball d	efinitions ⁽¹⁾	(cor	ntinued)
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
24	32	M4	43	T8	Y10	K5	H13	N6	26	35	M4	46	K5	PB0	I/O	TT_ha
25	33	L4	44	W9	W9	N5	L14	M6	27	36	L4	47	N5	PB1	I/O	FT_ha

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
2 6	3 4	K 4	4 5	A B 1 0	M 6	L 5	M 1 5
-	-	K 5	4 6	R 7	R 7	M 5	N 1 6
-	-	L 5	4 7	V 8	V 8	K 6	T 2 1
-	-	-	8 4	9 A A	8 A B	M 7	B 5
-	-	-	4 9	A C 9	A 7	N 7	T 1 9
-	-	M 5	5 0	P 6	A A 9	M 6	P 1 7

Pinout, pin description and alternate functions

							Tak	ole 26	. STN	/132U	59xxx	pin/l	ball d	efinitions ⁽¹⁾	(cor	ntinued)		,
					ı	Pin nu	mber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
-	1	J5	51	U7	Y8	L6	K13	R8	-	-	J5	54	L6	PF14	I/O	FT_fha	-	I2C4_SCL, LCD_G0, TSC_G8_IO1, FMC_A8, EVENTOUT
-	-	L6	52	Y8	U7	N6	R18	P8	-	-	L6	55	N6	PF15	I/O	FT_fha	-	I2C4_SDA, LCD_G1, TSC_G8_IO2, FMC_A9, EVENTOUT
-	-	M6	53	T6	P6	J6	H11	R9	-	-	M6	56	J6	PG0	I/O	FT_ha	-	OCTOSPIM_P2_IO4, TSC_G8_IO3, FMC_A10, EVENTOUT
-	-	K6	54	W7	W7	H7	J12	N8	-	-	K6	57	H7	PG1	I/O	FT_ha	-	OCTOSPIM_P2_IO5, TSC_G8_IO4, FMC_A11, EVENTOUT
-	35	K7	55	AB8	T6	L7	L12	N9	-	38	K7	58	L7	PE7	I/O	FT_h	_	TIM1_ETR, MDF1_SDI2, LCD_B6, FMC_D4, SAI1_SD_B, EVENTOUT
-	36	J6	56	V6	AA7	K7 P in nu	N14 be m r	M8	-	39	J6	59	K7	PE8	I/O	FT_h	-	TIM1_CH1N, MDF1_CKI2, LCD_B7, FMC_D5, SAI1_SCK_B, EVENTOUT
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W	S P M S I S D 6 1 2 A G B F T	4 6 P F Q L	0 0 1 P F Q L	2 3 1 A G B F U	4 4 1 P F Q L	9 6 1 A G B F T	P in na me ( fu ion t nc f te t ) a r r es e	e p y t n i P	e r u t c u r t s O I/	s e t o N	A l fu ion te te t rn a nc s
-	3 7	M 7	5 7	U 5	V 6	J 7	T 1 7	P 9	-	4 0	M 7	6 0	J 7	P E 9	I / O	F T_ hv	-	T I M 1_ C H 1, A D F 1_ C C K 0, C C M D F 1_ K 0, L C D_ G 2, O C O S C T P I M_ P 1_ N L K F M C_ D 6, , S S_ A I 1_ F B, E V E N T O U T
-	-	-	8 5	A A 7	C 1 1	-	E 4	F 6	-	-	-	6 1	-	V S S	S	-	-	-
-	-	J 4	5 9	C A 7	C A 1	-	T 1 5	L 7	-	-	J 4	6 2	-	V D D	S	-	-	-
-	3 8	J 7	6 0	Y 6	R 5	H 8	M 1 3	P 1 0	-	4 1	J 7	6 3	H 8	P E 1 0	I / O	F T_ ha v	-	T I M 1_ C H 2 N, A D F 1_ S D I 0, M D F 1_ S D I 4, L C D_ G 3, T S C_ G I O 1, 5_ O C T O S P I M_ P 1_ C L K, F M C_ D 7, S A I 1_ M C L K_ B, E V E N T O U T
-	3 9	L 7	6 1	W 5	U 5	M 8	P 1 5	P 1 1	-	4 2	L 7	6 4	M 8	P E 1 1	I / O	F T_ ha	-	C S T I M 1_ H 2, P I 1_ R D Y, M D F 1_ C K I 4, L C D_ G 4, T S C_ G I O 2, 5_ O C T O S P I M_ P 1_ N C S, F M C_ D 8, E V E N T O U T

LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	1	B3	1	A13	D10	A1	G20	E5	-	1	B3	1	A1	PE2	I/O	FT_ha	-	TRACECLK, TIM3_ETR, SAI1_CK1, USART6_CK, LCD_R0, TSC_G7_IO1, LGPPIO1_P14, FMC_A23, SAI1_MCLK_A, EVENTOUT
-	2	A2	2	D10	G9	D3	E22	C3	-	2	A2	2	D3	PE3	I/O	FT_hat	-	TRACED0, TIM3_CH1, OCTOSPIM_P1_DQS, USART6_CTS, LCD_R1, TSC_G7_IO2, LGPPIO1_P15, FMC_A19, SAI1_SD_B, EVENTOUT	TAMP_IN6/ TAMP_OUT3
-	3	B2	3	F10	J9	C2	F21	B2	-	3	B2	3	C2	PE4	I/O	FT_hat	-	TRACED1, TIM3_CH2, SAI1_D2, MDF1_SDI3, USART6_RTS_DE, LCD_B0, TSC_G7_IO3, DCMI_D4/PSSI_D4, FMC_A20, SAI1_FS_A, EVENTOUT	WKUP1, TAMP_IN7/ TAMP_OUT8

					i	Pin nu	mber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS
27	44	K9	66	W3	W5	K9	T13
-	45	L9	67	AA3	AA5	L9	R10
28	46	M10	68	AC5	AC5	N9	T11
29	47	M9	69	AB4	AB4	N10	T9
30	48	L10	70	AC3	AC3	M10	R8
-	-	-	-	-	-	-	-
31	49	M11	71	AB2	AB2	N11	T3

							Tal	ble 26	. STN	/132U	59xxx	pin/	ball d	efinitions ⁽¹⁾	(cor	ntinued)
					I	Pin nu	mber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
32	50	E9	72	AA1	C3	M11	F3	F7	31	49	E9	71	M11	VSS	S	-
33	51	D4	73	AC1	AC11	N12	P1	L8	32	50	D4	72	N12	VDD	S	-
-	-	-	-	-	-	-	T1	-	-	-	-	-	-	VDD	S	-
-	-	L11	-	Y2	AA3	L10	T5	M11	33	51	L11	73	L10	PB12	I/O	FT_hav
34	52	K10	74	R5	Y4	N13	T7	M12	34	52	K10	74	N13	PB13	I/O	FT_fa

					ı	Pin nu	mber									,
I OFD64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
3:	5 53	K11	75	T4	V4	M12	R6	P13	35	53	K11	75	M12	PB14	I/O	FT_fda
30	3 54	K12	76	N5	Y2	L11	P11	R14	36	54	K12	76	L11	PB15	I/O	FT_c
_	-	-	-	-	H12	-	G24	G5	-	-	-	-	1	VDDDSI	S	-
_	-	-	-	-	M12	-	J24	H5	-	-	-	-	-	VDD11DSI	S	-
	-	-	-	-	E13	-	E26	G1	=	-	-	-	-	DSI_D0P	I/O	DSI

Pinout, pin description and alternate functions

							Tal	ole 26	. STN	/132U	59xxx	pin/	ball d	efinitions ⁽¹⁾	(00)	ntinued)
					ı	Pin nu	ımber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
-	-	ı	1	-	G13	-	F25	G2	ı	-	-	1	-	DSI_D0N	I/O	DSI
-	-	i	1	-	K12	-	E24	G6	ı	-	-	ı	-	VSSDSI	S	1
-	-	-	-	-	-	-	H23	H6	-	-	-	-	-	VSSDSI	S	-
-	-	-	-	-	J13	-	G26	H1	•	-	-	-	-	DSI_CKP	I/O	DSI
-		-	-	-	L13	-	H25	J1	-	-	-	-	-	DSI_CKN	I/O	DSI
-	-	-	-	-	N13	-	J26	K2	-	-	-	-	-	DSI_D1P	I/O	DSI
-	-	-	-	-	R13	-	K25	K1	-	-	-	-	-	DSI_D1N	I/O	DSI
-	-	-	-	-	P12	-	F23	H2	-	-	-	-	-	VSSDSI	S	-
-	-	-	-	-	-	-	-	J2	-	-	-	-	-	VSSDSI	S	-
-	55	L12	77	W1	W3	L12	P9	N13	-	55	L12	77	L12	PD8	I/O	FT_h
-	56	J10	78	V2	U3	L13 P in nu	P7 be m r	P15	-	56	J10	78	L13	PD9	I/O	FT_h
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W	S P M S I S D 6 1 2 A G B F T	4 6 P F Q L	0 0 1 P F Q L	2 3 1 A G B F U	4 4 1 P F Q L	9 6 1 A G B F T	P in na me ( fu ion t nc f te t ) a r r es e	e p y t n i P	e r u t c u r t s O I/
-	5 7	M 1 2	7 9	U 3	W 1	K 1 1	P 5	P 1 4	-	5 7	M 1 2	7 9	K 1 1	P D 1 0	I / O	F T_ ha
-	8 5	1 1 J	8 0	P 4	3 R	1 3 M	1 1 M	1 2 L	-	8 5	1 1 J	8 0	1 3 M	1 1 P D	/ O I	F T_ ha
-	5 9	J 1 2	8 1	R 3	T 2	K 1 0	L 1 0	M 1 3	-	5 9	J 1 2	8 1	K 1 0	P D 1 2	I / O	F T_ f ha

							Tal	ole 26	. STN	/132U	59xxx	pin/	ball d	efinitions ⁽¹⁾	(cor	ntinued)
					ı	Pin nu	mber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
-	60	H11	82	U1	N3	K12	K11	N14	-	60	H11	82	K12	PD13	I/O	FT_fha
-	-	-	83	T2	C7	J12	G4	F9	-	-	-	83	J12	VSS	S	-
-	-	-	84	R1	AC9	A11	R2	L9	-	-	-	84	J13	VDD	S	ı
-	61	H10	85	N3	P2	J10	N10	N15	-	61	H10	85	J10	PD14	I/O	FT_h
-	62	H12	86	P2	R1	J11	K9	K12	-	62	H12	86	J11	PD15	I/O	FT_h
-	-	G10	87	N1	N1	K13	F9	G12	-	-	G10	87	K13	PG2	I/O	FT_hs

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
-	-	G 1 1	8 8	M 4	L 1	J 8	H 9
-	-	G 9	8 9	M 2	M 2	H 1 1	J 1 0
-	-	G 1 2	9 0	L 3	L 3	J 9	G 1 2
-	-	F 9	9 1	M 6	M 4	H 1 0	G 1 0
-	-	F 1 0	9 2	L 1	J 1	G 8	G 1 4

							Tal	ole 26	. STN	/132U	59xxx	pin/	ball d	efinitions ⁽¹⁾	(cor	ntinued)
					1	Pin nu	mber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
-	-	F12	93	K4	K2	H9	F11	E13	-	-	F12	93	H9	PG8	I/O	FT_fs
-	-	-	94	K2	-	-	N4	G10	-	-	-	94	-	VSS	S	-
-	-	-	95	J1	G1	H12	E2	G11	-	-	1	95	H12	VDDIO2	S	-
37	63	F11	96	J3	N5	H13	D5	C15	37	63	F11	96	H13	PC6	I/O	FT_a
38	64	E10	97	L5	J3	G12 P in nu	D3 be m r	B15	38	64	E10	97	G12	PC7	I/O	FT_a
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W	S P M S I S D 6 1 2 A G B F T	4 6 P F Q L	0 0 1 P F Q L	2 3 1 A G B F U	4 4 1 P F Q L	9 6 1 A G B F T	P in na me ( fu t ion nc f te t ) a r r es e	e p y t n i P	e r u t c u r t s O I/
3 9	6 5	E 1 2	9 8	G 1	K 4	G 1 0	D 7	A 1 4	3 9	6 5	E 1 2	9 8	G 1 0	P C 8	I / O	F T_ a
0 4	6 6	1 1 E	9 9	2 H	L 5	G 9	9 D	C 1 4	0 4	6 6	1 1 E	9 9	G 9	C 9 P	/ O I	F T_ a
4 1	6 7	D 1 2	1 0 0	G 3	H 4	G 7	C 8	A 1 3	4 1	6 7	D 1 2	1 0 0	G 7	P A 8	I / O	F T_ hv

							Tal	ole 26	. STN	/132U	59xxx	pin/l	ball d	efinitions ⁽¹⁾	100)	ntinued)
					ı	Pin nu	mber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
42	68	D10	101	F2	F2	G11	C6	E12	42	68	D10	101	G11	PA9	I/O	FT_u
43	69	D11	102	E3	G3	F11	C4	D12	43	69	D11	102	F11	PA10	I/O	FT_u
-	-	-	-	-	-	-	D1	F11	-	-	-	-	-	VDD11USB	S	-
44	70	C12	103	E1	E1	G13 P in nu	C2 be m r	B14	44	70	C12	103	G13	PA11	I/O	TT
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W	S P M S I S D 6 1 2 A G B F T	4 6 P F Q L	0 0 1 P F Q L	2 3 1 A G B F U	4 4 1 P F Q L	9 6 1 A G B F T	P in na me ( fu ion t nc f te t ) a r r es e	e p y t n i P	e r u t c u r t s O I/
4 5	1 7	1 2 B	1 0 4	C 1	C 1	1 3 F	1 B	1 3 B	4 5	1 7	1 2 B	1 0 4	1 3 F	1 2 P A	/ O I	T T
4 6	7 2	C 1 0	1 0 5	D 2	E 3	F 1 2	B 3	C 1 3	4 6	7 2	C 1 0	1 0 5	F 1 2	1 3 P A ( J T M S / S W D I O )	I / O	F T
4 7	-	-	-	C 3	A A 1	-	P 3	-	4 7	-	-	-	-	V S S	S	-
4 8	7 3	A 1 2	1 0 6	A 1	A 1	E 1 3	A 2	E 9	4 8	7 3	A 1 2	1 0 6	E 1 3	V D D U S B	S	-
-	7 4	H 4	1 0 7	-	D 2	E 1 2	R 1 6	H 1 0	-	7 4	H 4	1 0 7	E 1 2	V S S	S	-
-	7 5	D 9	1 0 8	-	U 1	D 1 3	A 6	-	-	7 5	D 9	1 0 8	D 1 3	V D D	S	-
4 9	7 6	C 1 1	1 0 9	H 4	F 4	C 1 0	D 1 1	A 1 2	4 9	7 6	C 1 1	1 0 9	C 1 0	P A 1 4 ( J T C K / S C ) W L K	I / O	F T

| LQFP64 SMPS | LQFP100 SMPS | UFBGA132 SMPS | LQFP144 SMPS | WLCSP150 SMPS | WLCSP150 DSI SMPS | TFBGA169 SMPS | WLCSP208 DSI SMPS | TFBGA216 DSI SMPS | LQFP64 | LQFP100 | UFBGA132 | LQFP144 | TFBGA169 | Pin name (function after reset) | Pin type | I/O structure | Notes | Alternate functions | Additional functions | |---|---|---|---|---|---|---|---|---|---|---|---|---|---|

3
---

Table 26. STM32U59xxx pin/ball definitions⁽¹⁾ (continued) Pin number WLCSP150 DSI SMPS WLCSP208 DSI SMPS TFBGA216 DSI SMPS MLCSP150 SMPS UFBGA132 SMPS TFBGA169 SMPS /O structure LQFP100 SMPS LQFP144 SMPS LQFP64 SMPS Pin name UFBGA132 LQFP100 TFBGA169 Additional LQFP144 LQFP64 (function Alternate functions functions after reset) LPTIM3 IN1, ADF1 SDI0. DCMI D2/PSSI D2, OCTOSPIM P1 NCS, SPI3 MISO, USART3_RX(boot), UART4 RX, 79 A10 112 J5 C10 B10 52 PC11 I/O FT ha 79 A10 112 TSC G3 103, DCMI D4/PSSI D4, UCPD1 FRSTX2, SDMMC1 D3, SAI2_MCLK_B, EVENTOUT TRACED3. SPI3 MOSI, USART3 CK, UART5 TX, TSC G3 IO4. E14 C10 80 B10 113 Α5 53 80 B10 113 PC12 I/O FT hav DCMI D9/PSSI D9, LPGPIO1 P10. SDMMC1 CK. SAI2_SD_B, EVENTOUT I2C6 SDA, TIM8 CH4N, I/O F15 FT fh I2C5 SDA, SPI2 NSS, C9 114 G5 C5 D9 C9 114 B9 PD0 LCD B4, FDCAN1 RX, FMC D2, EVENTOUT

							Tak	ole 26	. STN	/132U	59xxx	c pin/l	ball d	efinitions ⁽¹⁾	(cor	ntinued)
					ı	Pin nu	ımber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
-	82	B9	115	E5	E5	F6	A10	C9	1	82	B9	115	F6	PD1	I/O	FT_fh
54	83	A9	116	C5	G5	F7	D13	B9	54	83	A9	116	F7	PD2	I/O	FT
-	84	C8	117	A5	K6	D8 P in nu	C12 be m r	A9	1	84	C8	117	D8	PD3	I/O	FT_hv
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W	S P M S I S D 6 1 2 A G B F T	4 6 P F Q L	0 0 1 P F Q L	2 3 1 A G B F U	4 4 1 P F Q L	9 6 1 A G B F T	P in na me ( fu t ion nc f te t ) a r r es e	e p y t n i P	e r u t c u r t s O I/
-	8 5	B 8	1 1 8	H 6	B 6	C 8	D 1 5	A 8	-	8 5	B 8	1 1 8	C 8	P D 4	O I /	F T_ h
-	8 6	A 8	1 1 9	F 6	D 6	E 7	E 1 6	B 8	-	8 6	A 8	1 1 9	E 7	P D 5	/ O I	F T_ h
-	-	-	1 2 0	D 6	H 2	B 8	R 2 0	H 1 5	-	-	-	1 2 0	B 8	V S S	S	-
-	-	-	1 2 1	B 6	U 1 3	A 8	A 1 2	-	-	-	-	1 2 1	A 8	V D D	S	-
-	8 7	A 7	1 2 2	K 6	F 6	B 7	F 1 7	C 8	-	8 7	A 7	1 2 2	B 7	P D 6	I / O	F T_ hv

Pinout, pin description and alternate functions

							Tak	ole 26	. STN	/132U	59xx>	c pin/	ball d	efinitions ⁽¹⁾	(cor	ntinued)
						Pin nu	ımber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
-	88	D7	123	L7	H6	D7	C14	D8	-	88	D7	123	D7	PD7	I/O	FT_h
-	-	B7	124	J7	-	A7	B13	A7	-	-	B7	124	A7	PG9	I/O	FT_hs
-	-	C7	125	E7	-	C7	F19	B7	-	-	C7	125	C7	PG10	I/O	FT_hs

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
-	-	-	-	C 7	-	-	E 1 8
-	-	A 6	1 2 6	A 7	-	E 6	D 1 7
-	-	-	1 2 7	G 7	-	-	A 1 4
-	-	-	1 2 8	F 8	-	-	C 1 6
-	-	H 9	1 2 9	D 8	-	-	R 2 4
-	-	D 8	1 3 0	B 8	-	A 6	A 1 6

Pinout, pin description and alternate functions

Ta b le 2 6. S T M 3 2 U 5 9x xx	( 1) in / ba l l de f in i t io p ns	( t in d ) co n ue
-------------------------------------------------------------------------	--------------------------------------------------------------------------------	-----------------------------------------

							P in nu	be m r
	S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
DS13633 Rev 2	5 6	9 0	B 6	1 3 3	L 9	E 7	B 6	G 1 8
145/386
							Tab	ole 26
-------------	--------------	---------------	--------------	---------------	------------------- ı	--------------- Pin nu	------------------- mber	-------------------
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS
57	91	D6	134	A9	A9	C6	C18	B5
58	92	A5	135	E9	D8	B5	A18	A4

					I	Pin nu	mber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS
59	93	D5	136	C9	G7	F5	D19
60	94	B5	137	G9	J7	C5	E20
61	95	C5	138	J9	C9	E5	B19

14								Tab	ole 26	. STN	/132U	59xxx	pin/l	oall d	efinitions ⁽¹⁾	(cor	ntinued)
148/386						i	Pin nu	mber
	LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
DS13633 Rev 2	-	96	A4	139	B10	F8	D5	C20	C5	62	96	A4	140	D5	PB9	I/O	FT_f
2	-	97	C4	140	M10	H8	D4	A20	A2	-	97	C4	141	D4	PE0	I/O	FT_h
	-	-	A3	141	K10	E9	C4	B21	B3	-	98	A3	142	C4	PE1	I/O	FT_h
7	-	-	-	-	-	-	-	-	-	-	-	-	-	A4	VCAP	S	-
7	62	98	B4	142	A11	B10	A4	A22	E6	-	-	-	-	-	VDD11	S	-

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
6 3	9 9	E 4	1 4 3	C 1 1	T 1 2	B 4	R 4
6 4	1 0 0	J 9	1 4 4	B 1 2	A C 7	A 3	A 2 4
-	-	-	-	-	-	-	A 2 6
-	-	-	-	B 2	B 2	-	A 4
-	-	-	-	-	-	F 1 0	B 7
-	-	-	-	-	-	E 1 0	E 1 0
-	-	-	-	-	-	F 9	F 1 3
-	-	-	-	-	-	E 1 1	H 1 5
-	-	-	-	-	-	F 8	E 1 2

LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
-	1	B3	1	A13	D10	A1	G20	E5	-	1	B3	1	A1	PE2	I/O	FT_ha	-	TRACECLK, TIM3_ETR, SAI1_CK1, USART6_CK, LCD_R0, TSC_G7_IO1, LPGPIO1_P14, FMC_A23, SAI1_MCLK_A, EVENTOUT
-	2	A2	2	D10	G9	D3	E22	C3	-	2	A2	2	D3	PE3	I/O	FT_hat	-	TRACED0, TIM3_CH1, OCTOSPIM_P1_DQS, USART6_CTS, LCD_R1, TSC_G7_IO2, LPGPIO1_P15, FMC_A19, SAI1_SD_B, EVENTOUT	TAMP_IN6/ TAMP_OUT3
-	3	B2	3	F10	J9	C2	F21	B2	-	3	B2	3	C2	PE4	I/O	FT_hat	-	TRACED1, TIM3_CH2, SAI1_D2, MDF1_SDI3, USART6_RTS_DE, LCD_B0, TSC_G7_IO3, DCMI_D4/PSSI_D4, FMC_A20, SAI1_FS_A, EVENTOUT	WKUP1, TAMP_IN7/ TAMP_OUT8

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
-	-	-	-	-	-	B 1 3	M 5
-	-	-	-	-	-	C 1 2	M 7
-	-	-	-	-	-	-	J 4
-	-	-	-	-	-	-	G 2
-	-	-	-	-	-	C 1 1	L 6
-	-	-	-	-	-	A 1 3	L 8

	LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
1	-	1	B3	1	A13	D10	A1	G20	E5	PE2	I/O	FT_ha	-	TRACECLK, TIM3_ETR, SAI1_CK1, USART6_CK, LCD_R0, TSC_G7_IO1, LPGPIO1_P14, FMC_A23, SAI1_MCLK_A, EVENTOUT
2	-	2	A2	2	D10	G9	D3	E22	C3	PE3	I/O	FT_hat	-	TRACED0, TIM3_CH1, OCTOSPIM_P1_DQS, USART6_CTS, LCD_R1, TSC_G7_IO2, LPGPIO1_P15, FMC_A19, SAI1_SD_B, EVENTOUT	TAMP_IN6/ TAMP_OUT3
3	-	3	B2	3	F10	J9	C2	F21	B2	PE4	I/O	FT_hat	-	TRACED1, TIM3_CH2, SAI1_D2, MDF1_SDI3, USART6_RTS_DE, LCD_B0, TSC_G7_IO3, DCMI_D4/PSSI_D4, FMC_A20, SAI1_FS_A, EVENTOUT	WKUP1, TAMP_IN7/ TAMP_OUT8

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
-	-	-	-	-	-	B 1 0	J 2
-	-	-	-	-	-	B 3	C 2 2
-	-	-	-	-	-	A 2	D 2 1
-	-	-	-	-	-	C 3	J 1 8
-	-	-	-	-	-	-	J 8
-	-	-	-	-	-	B 2	L 2 4
-	-	-	-	-	-	B 1	L 2
-	-	-	-	-	-	-	H 5
-	-	-	-	-	-	-	H 7

							Tal	ole 26	. STN	/132U	59xxx	c pin/	ball d	efinitions ⁽¹⁾	(cor	ntinued)
					ı	Pin nu	ımber
LQFP64 SMPS	LQFP100 SMPS	UFBGA132 SMPS	LQFP144 SMPS	WLCSP150 SMPS	WLCSP150 DSI SMPS	TFBGA169 SMPS	WLCSP208 DSI SMPS	TFBGA216 DSI SMPS	LQFP64	LQFP100	UFBGA132	LQFP144	TFBGA169	Pin name (function after reset)	Pin type	I/O structure
-	-	-	1	ı	-	-	G6	G14	-	-	-	-	-	PI11	I/O	FT_hv
-	-	-	1	-	-	-	G8	G13	-	-	-	-	-	PI12	I/O	FT_hv
-	-	ı	-	ı	-	-	L4	K9	ı	-	-	-	-	VSS	S	-
-	ı	ı	-	ı	-	-	M1	-	ı	-	-	-	-	VDD	S	ı
-	-	1	1	1	-	-	F7	F15	ı	-	-	-	-	PI13	I/O	FT_hv
-	-	-	-	-	-	-	F5	F14	-	-	-	-	-	PI14	I/O	FT_hv
-	-	-	-	-	-	-	E8	F13	-	-	-	-	-	PI15	I/O	FT_hv
-	-	-	-	-	-	-	E6	E15	-	-	-	-	-	PJ0	I/O	FT_hv
-	-	-	-	-	-	-	MЗ	L10	1	-	-	-	-	VSS	S	-
-	-	-	-	-	-	-	N2	-	1	-	-	-	-	VDD	S	-
-	-	-	-	-	-	-	-	G4	-	-	-	-	-	PJ1	I/O	FT_fhv
-	-	-	-	-	-	-	-	D2	i	-	-	-	-	PJ2	I/O	FT_fhv

						P in nu	be m r
S P M S 4 6 P F Q L	S P M S 0 0 1 P F Q L	S P M S 2 3 1 A G B F U	S P M S 4 4 1 P F Q L	S P M S 0 5 1 P S C L W	S P M S I S D 0 5 1 P S C L W	S P M S 9 6 1 A G B F T	S P M S I S D 8 0 2 P S C L W
-	-	-	-	-	-	-	-
-	-	-	-	-	-	-	-
-	-	-	-	M 1 2	V 2	B 1 1	-
-	-	-	-	-	-	-	-
-	-	-	-	-	-	-	-
-	-	-	-	-	-	-	-
-	-	-	-	-	-	-	-
-	-	-	-	-	-	-	-
-	-	-	-	-	-	-	-
-	-	-	-	-	-	-	-
-	-	-	-	-	-	-	-
-	-	-	-	A 3	-	-	-

^1. Function availability depends on the chosen device.

2. PC13, PC14, and PC15 are supplied through the power switch (by V_SW). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs in output mode is limited:
- The speed must not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (for example to drive a LED).
3. After a backup domain power-up, PC13, PC14, and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
4. After reset, a pull-down resistor (Rd = 5.1 kΩ from UCPD peripheral) can be activated on PA15 and PB15 (UCPD1_CC1, UCPD1_CC2). The pull-down on PA15 (UCPD1_CC1) is activated by high level on PB5 (UCPD1_DBCC1). The pull-down on PB15 (UCPD1_CC2) is activated by high level on PB14 (UCPD1_DBCC2). This pull-down control (dead battery support on UCPD) can be disabled by setting UCPD_DBDIS = 1 in the PWR_UCPDR register.
5. GPIO is 5V-tolerant when the USB PHY is powered on.
6. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

Pinout, pin description and alternate functions

4.3 Alternate functions

Table 27. Alternate function AF0 to AF7⁽¹⁾

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
	CRS/LPTIM1/ SYS_AF	LPTIM1/ TIM1/2/5/8	I2C5/6/ LPTIM1/2/3/ TIM1/2/3/4/5	ADF1/I2C4/ OCTOSPIM_P1/ OTG_HS/SAI1/ SPI2/TIM1/8/ USART2	DCMI/ I2C1/2/3/4/5/ LPTIM3	DCMI/I2C4/MDF1/ OCTOSPIM_P1/2/ SPI1/2/3	I2C3/MDF1/ OCTOSPIM_P2/ SPI3	LCD/ USART1/2/3/6
PA0	-	TIM2_CH1	TIM5_CH1	TIM8_ETR	-	-	SPI3_RDY	USART2_CTS
PA1	LPTIM1_CH2	TIM2_CH2	TIM5_CH2	-	I2C1_SMBA	SPI1_SCK	-	USART2_RTS_ DE
PA2	-	TIM2_CH3	TIM5_CH3	-	-	SPI1_RDY	-	USART2_TX
PA3	-	TIM2_CH4	TIM5_CH4	SAI1_CK1	-	-	-	USART2_RX
PA4	-	-	-	OCTOSPIM_P1 _NCS	-	SPI1_NSS	SPI3_NSS	USART2_CK
PA5	CSLEEP	TIM2_CH1	TIM2_ETR	TIM8_CH1N	PSSI_D14	SPI1_SCK	-	USART3_RX
PA6	CDSTOP	TIM1_BKIN	TIM3_CH1	TIM8_BKIN	DCMI_ PIXCLK/ PSSI_PDCK	SPI1_MISO	-	USART3_CTS
PA7	SRDSTOP	TIM1_CH1N	TIM3_CH2	TIM8_CH1N	I2C3_SCL	SPI1_MOSI	-	USART3_TX
PA8	MCO	TIM1_CH1	-	SAI1_CK2	-	SPI1_RDY	-	USART1_CK
PA9	-	TIM1_CH2	-	SPI2_SCK	-	DCMI_D0/PSSI_D0	-	USART1_TX
PA10	CRS_SYNC	TIM1_CH3	LPTIM2_IN2	SAI1_D1	-	DCMI_D1/PSSI_D1	-	USART1_RX
PA11	-	TIM1_CH4	TIM1_BKIN2	-	-	SPI1_MISO	-	USART1_CTS
PA12	-	TIM1_ETR	-	-	-	SPI1_MOSI	OCTOSPIM_P2 _NCS	USART1_RTS_ DE
PA13	JTMS/SWDIO	IR_OUT	-	-	-	-	-	-
PA14	JTCK/SWCLK	LPTIM1_CH1	-	-	I2C1_SMBA	I2C4_SMBA	-	-
PA15	JTDI	TIM2_CH1	TIM2_ETR	USART2_RX	-	SPI1_NSS	SPI3_NSS	USART3_RTS_ DE

Table 27. Alternate function AF0 to AF7⁽¹⁾ (continued)

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
	Port	CRS/LPTIM1/ SYS_AF	LPTIM1/ TIM1/2/5/8	I2C5/6/ LPTIM1/2/3/ TIM1/2/3/4/5	ADF1/I2C4/ OCTOSPIM_P1/ OTG_HS/SAI1/ SPI2/TIM1/8/ USART2	DCMI/ I2C1/2/3/4/5/ LPTIM3	DCMI/I2C4/MDF1/ OCTOSPIM_P1/2/ SPI1/2/3	I2C3/MDF1/ OCTOSPIM_P2/ SPI3	LCD/ USART1/2/3/6
	PB0	-	TIM1_CH2N	TIM3_CH3	TIM8_CH2N	LPTIM3_CH1	SPI1_NSS	-	USART3_CK
	PB1	-	TIM1_CH3N	TIM3_CH4	TIM8_CH3N	LPTIM3_CH2	-	MDF1_SDI0	USART3_RTS_ DE
	PB2	-	LPTIM1_CH1	-	TIM8_CH4N	I2C3_SMBA	SPI1_RDY	MDF1_CKI0	-
	PB3	JTDO/ TRACESWO	TIM2_CH2	LPTIM1_CH1	ADF1_CCK0	I2C1_SDA	SPI1_SCK	SPI3_SCK	USART1_RTS_ DE
	PB4	NJTRST	LPTIM1_CH2	TIM3_CH1	ADF1_SDI0	I2C3_SDA	SPI1_MISO	SPI3_MISO	USART1_CTS
	PB5	-	LPTIM1_IN1	TIM3_CH2	OCTOSPIM_P1 _NCLK	I2C1_SMBA	SPI1_MOSI	SPI3_MOSI	USART1_CK
B	PB6	-	LPTIM1_ETR	TIM4_CH1	TIM8_BKIN2	I2C1_SCL	I2C4_SCL	MDF1_SDI5	USART1_TX
Port	PB7	-	LPTIM1_IN2	TIM4_CH2	TIM8_BKIN	I2C1_SDA	I2C4_SDA	MDF1_CKI5	USART1_RX
	PB8	-	-	TIM4_CH3	SAI1_CK1	I2C1_SCL	MDF1_CCK0	SPI3_RDY	LCD_B1
	PB9	-	IR_OUT	TIM4_CH4	SAI1_D2	I2C1_SDA	SPI2_NSS	-	-
	PB10	-	TIM2_CH3	LPTIM3_CH1	I2C4_SCL	I2C2_SCL	SPI2_SCK	-	USART3_TX
	PB11	1	TIM2_CH4	-	I2C4_SDA	I2C2_SDA	SPI2_RDY	-	USART3_RX
	PB12	-	TIM1_BKIN	I2C6_SMBA	-	I2C2_SMBA	SPI2_NSS	MDF1_SDI1	USART3_CK
	PB13	-	TIM1_CH1N	LPTIM3_IN1	-	I2C2_SCL	SPI2_SCK	MDF1_CKI1	USART3_CTS
	PB14	-	TIM1_CH2N	LPTIM3_ETR	TIM8_CH2N	I2C2_SDA	SPI2_MISO	MDF1_SDI2	USART3_RTS_ DE
	PB15	RTC_REFIN	TIM1_CH3N	LPTIM2_IN2	TIM8_CH3N	-	SPI2_MOSI	MDF1_CKI2	-

Table 27. Alternate function AF0 to AF7(1) (continued)

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7
	CRS/LPTIM1/SYS_AF	LPTIM1/TIM1/2/5/8	I2C5/6/LPTIM1/2/3/TIM1/2/3/4/5	ADF1/I2C4/OCTOSPIM_P1/OTG_HS/SAI1/SPI2/TIM1/8/USART2	DCMI/I2C1/2/3/4/5/LPTIM3	DCMI/I2C4/MDF1/OCTOSPIM_P1/2/SPI1/2/3	I2C3/MDF1/OCTOSPIM_P2/SPI3	LCD/USART1/2/3/6
PA0	-	TIM2_CH1	TIM5_CH1	TIM8_ETR	-	-	SPI3_RDY	USART2_CTS
PA1	LPTIM1_CH2	TIM2_CH2	TIM5_CH2	-	I2C1_SMBA	SPI1_SCK	-	USART2_RTS_DE
PA2	-	TIM2_CH3	TIM5_CH3	-	-	SPI1_RDY	-	USART2_TX
	CRS/LPTIM1/SYS_AF	LPTIM1/TIM1/2/5/8	I2C5/6/LPTIM1/2/3/TIM1/2/3/4/5	ADF1/I2C4/OCTOSPIM_P1/OTG_HS/SAI1/SPI2/TIM1/8/USART2	DCMI/I2C1/2/3/4/5/LPTIM3	DCMI/I2C4/MDF1/OCTOSPIM_P1/2/SPI1/2/3	I2C3/MDF1/OCTOSPIM_P2/SPI3	LCD/USART1/2/3/6
PB0	-	TIM1_CH2N	TIM3_CH3	TIM8_CH2N	LPTIM3_CH1	SPI1_NSS	-	USART3_CK
PB1	-	TIM1_CH3N	TIM3_CH4	TIM8_CH3N	LPTIM3_CH2	-	MDF1_SDI0	USART3_RTS_DE
PB2	-	LPTIM1_CH1	-	TIM8_CH4N	I2C3_SMBA	SPI1_RDY	MDF1_CKI0	-
PB3	JTDO/TRACESWO	TIM2_CH2	LPTIM1_CH
PA3	-	TIM2_CH4	TIM5_CH4	SAI1_CK1	-	-	-	USART2_RX
PA4	-	-	-	OCTOSPIM_P1_NCS	-	SPI1_NSS	SPI3_NSS	USART2_CK
PA5	CSLEEP	TIM2_CH1	TIM2_ETR	TIM8_CH1N	PSSI_D14	SPI1_SCK	-	USART3_RX
PA6	CDSTOP	TIM1_BKIN	TIM3_CH1	TIM8_BKIN	DCMI_PIXCLK/PSSI_PDCK	SPI1_MISO	-	USART3_CTS
PA7	SRDSTOP	TIM1_CH1N	TIM3_CH2	TIM8_CH1N	I2C3_SCL	SPI1_MOSI	-	USART3_TX
PA8	MCO	TIM1_CH1	-	SAI1_CK2	-	SPI1_RDY	-	USART1_CK
PA9	-	TIM1_CH2	-	SPI2_SC

Ć	ົວ
ç	ᢓ
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160/386 DS13633 Rev 2

Electrical Characteristics

The definition and values of output AC characteristics are given in Figure 35: Output AC characteristics definition and in the table below respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 32.

Table 88. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in VBAT mode(1), and FT_o I/Os)(2)(3)(4)

Speed Symbol Parameter Conditions Min Max Unit
Maximum frequency
all I/Os CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 12.5
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5
Fmax CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 1 MHz
CL = 10 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 12.5
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 1
00 Output rise and fall time
tr/tf
all I/Os CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 17
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33
CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 85 ns
CL = 10 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 12.5
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 25
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 50

Table 88. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in VBAT mode(1), and FT_o I/Os)(2)(3)(4) (continued)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
			CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	- -	55 12.5
		Maximum frequency	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	2.5
	Fmax	all I/Os	CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 10 pF, 1.08 V ≤ VDDIOx ≤<1.58 V	- - -	55 12.5 2.5	MHz
01			CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	- -	5.8 10
		Output rise and fall time	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	18
	tr/tf	all I/Os CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V -	- - 12	4.2 7.5	ns
			CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V	-	100(5)	MHz
		Maximum frequency all I/Os	CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	- -	33(5) 5
	Fmax		CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	- -	133(5) 40(5)
10			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	- 5
			CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	- -	3.3(5) 6.0(5)	ns
		Output rise and fall time	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	13.3
	tr/tf	all I/Os	CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	- - -	2(5) 4.1(5) 9.2
			CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	- -	100(5) 33(5)	MHz
11	Fmax	Maximum frequency	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	5
		All I/Os except FT_c, FT_v, and TT_v	CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	- - -	133(5) 40(5) 5

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
			CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	- -	140(5) 40(5)
		Maximum frequency	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	5
11 (cont'd)	Fmax	FT_v and TT_v I/Os	CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	- - -	166(5) 50(5) 5	MHz
	tr/tf		CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	- -	3.3(5) 6.0(5)
		Output rise and fall time	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	13.3
		All I/Os except FT_c, FT_v, and TT_v	CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	- -	2.0(5) 4.1(5)
			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	9.2	ns
	tr/tf		CL = 30 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V	-	2.5(5)
			Output rise and fall time	CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	- -	5.0(5) 11
		FT_v and TT_v I/Os	CL = 10 pF, 2.7 V ≤ VDDIOx ≤ 3.6 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	- - -	1.66(5) 3.1(5) 7
	Fmax	Maximum frequency	CL = 550 pF, 1.08 V ≤ VDDIOx < 3.6 V CL = 100 pF, 1.58 V ≤ VDDIOx < 3.6 V	- -	1 50	MHz
Fm+		Output fall time(6)	CL = 100 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	80
	tf		CL = 550 pF, 1.58 V ≤ VDDIOx < 3.6 V CL = 550 pF, 1.08 V ≤ VDDIOx < 1.58 V	- -	100 220	ns

^2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

^3. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO port configuration register.

^4. Specified by design. Not tested in production.

^5. Compensation system enabled.

^6. The fall time is defined between 70% and 30% of the output waveform accordingly to I2C specification.

Table 89. Output AC characteristics, HSLV ON (all I/Os except FT_c, FT_t in VBAT mode(1), and FT_o I/Os)(2)(3)(4)

Speed Symbol Parameter Conditions Min Max Unit
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10
CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4 MHz
Fmax Maximum frequency CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 15
00 CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4
CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 18
CL = 50 pF, 1.08 V ≤ VDDIOx < 1.58 V - 32 ns
tr/tf
Output rise and fall time CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 12
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 21
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 50
Fmax Maximum frequency CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10 MHz
CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 67
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10
01 tr/tf CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5.3
CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 10.6
Output rise and fall time CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 3.1 ns
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 5.6
CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 75(5)
Fmax CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
Maximum frequency CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 100(5) MHz
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 15
10 CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V - 4.4(5) ns
Output rise and fall time CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V - 9.6
tr/tf CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V - 2.2(5)
CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V - 4.7

Table 89. Output AC characteristics, HSLV ON (all I/Os except FT_c, FT_t in VBAT mode(1), and FT_o I/Os)(2)(3)(4) (continued)

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
			CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	75(5)
		Maximum frequency	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	15
	All I/Os except FT_c, FT_v, and TT_v	CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	100(5)
			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	15	MHz
Fmax			CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	110(5)
		Maximum frequency FT_v and TT_v I/Os	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V	- -	25 150(5)
11			CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	-	25
		Output rise and fall time All I/Os except FT_c, FT_v, and TT_v	CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	- -	4.4(5) 9.6 2.2(5) 4.7	ns
	tr/tf		CL = 30 pF, 1.58 V ≤ VDDIOx < 2.7 V	-	3.0(5)
		Output rise and fall time FT_v and TT_v I/Os	CL = 30 pF, 1.08 V ≤ VDDIOx < 1.58 V CL = 10 pF, 1.58 V ≤ VDDIOx < 2.7 V CL = 10 pF, 1.08 V ≤ VDDIOx < 1.58 V	- -	6.6 1.6(5) 3.4

Table 90. Output AC characteristics for FT_c I/Os(1)(2)

Speed Symbol Parameter Conditions Min Max Unit
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 10
Fmax
00 Maximum frequency All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 5 MHz
Output rise and fall time All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 33
tr/tf All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 66 ns
All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 25
Fmax Maximum frequency All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 10 MHz
01 All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 13
tr/tf Output rise and fall time All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 33 ns
Speed Symbol Parameter Conditions Min Max Unit
Maximum frequency All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 40
Fmax All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 20 MHz
1x All I/Os, CL = 50 pF, 2.7 V ≤ VDDIOx
≤ 3.6 V - 8
tr/tf Output rise and fall time All I/Os, CL = 50 pF, 1.58 V ≤ VDDIOx < 2.7 V - 17 ns

Table 90. Output AC characteristics for FT_c I/Os(1)(2) (continued)

Table 91. Output AC characteristics for FT_t I/Os in VBAT mode, and for FT_o I/Os(1)

Symbol	Parameter	Conditions	Min	Max	Unit
		CL = 50 pF, 2.7 V ≤ VSW ≤ 3.6 V	-	0.5
Fmax	Maximum frequency	CL = 50 pF, 1.58 V ≤ VSW < 2.7 V	-	0.25	MHz
	Output rise and fall time	CL = 50 pF, 2.7 V ≤ VSW ≤ 3.6 V	-	400	ns
tr/tf		CL = 50 pF, 1.58 V ≤ VSW < 2.7 V	-	900

Figure 35. Output AC characteristics definition

^1. Specified by design. Not tested in production.

^2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the product reference manual for a description of GPIO port configuration register.

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 29, Table 30, and Table 31 may cause permanent damage to the device. These are stress ratings only and the

functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

Table 29. Voltage characteristics⁽¹⁾ (2)

Symbol	Ratings	Min	Max	Unit
V _DDX - V _SS	External main supply voltage (including VDDSMPS, VDDA, VDDUSB, VDDDSI, VBAT, VREF+)	-0.3	4.0
V _DDIOx ⁽³⁾ - V _SS	I/O supply when HSLV = 0	-0.3	4.0
VDDIOx 7- VSS	I/O supply when HSLV = 1	-0.3	2.75
	Input voltage on FT_xx pins except FT_c pins	V _SS - 0.3	Min (min (V _DD , V _DDA , V _DDUSB , V _DDIO2 ) + 4.0, 6.0) ⁽⁵⁾⁽⁶⁾	V
V _IN ⁽⁴⁾	Input voltage on FT_t pins in V _BAT mode	V _SS - 0.3	Min (min (V _BAT , V _DDA , V _DDUSB , V _DDIO2 ) + 4.0, 6.0) ⁽⁵⁾⁽⁶⁾
	Input voltage on FT_c pins	V _SS - 0.3	5.5
	Input voltage on any other pins	V _SS - 0.3	4.0
V _REF+ - V _DDA	Allowed voltage difference for V _REF+ > V _DDA	-	0.4
ΔV _DDx	Variations between different VDDx power pins of the same domain	-	50.0	mV
V _SSx -V _SS	Variations between all the different ground pins ⁽⁷⁾	-	50.0	1110

All main power (VDD, VDDSMPS, VDDA, VDDUSB, VDDIO2, VDDDSI, VBAT) and ground (VSS, VSSA, VSSSMPS) pins must always be connected to the external power supply, in the permitted range.

The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

^3. V_DDIO1 or V_DDIO2 , V_DDIO1 = V_DD .

^4. V_IN maximum must always be respected. Refer to Table 30 for the maximum allowed injected current values.

^5. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.

^6. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.

^7. Including VREF- pin.

Table 30. Current characteristics

Symbol	Ratings	Max	Unit
∑IVDD	power lines (source)(1) Total current into sum of all VDD	200
∑IVSS	ground lines (sink)(1) Total current out of sum of all VSS	200
IVDD	Maximum current into each VDD power pin (source)(1)	100
IVSS	Maximum current out of each VSS ground pin (sink)(1)	100
	Output current sunk by any I/O and control pin	20
IIO	Output current sourced by any I/O and control pin	20	mA
	Total output current sunk by sum of all I/Os and control pins(2)	120
∑I(PIN)	Total output current sourced by sum of all I/Os and control pins(2)	120
IINJ(PIN)(3)(4)	Injected current on FT_xx, TT_xx, RST pins	-5/+0
∑ IINJ(PIN)	Total injected current (sum of all I/Os and control pins)(5)	±25

Table 31. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range
TJ	Maximum junction temperature	140	°C

Thermal Information

The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated using the following equation:

TJ max = TA max + (PD max * ΘJA)

where:

TA max is the maximum ambient temperature in °C.
ΘJA is the package junction-to-ambient thermal resistance in °C/W.
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max).
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins:P_I/O max = sum (V_OL * I_OL) + sum ((V_DDIOx - V_OH) * I_OH)$

taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application.

Table 171. Package thermal characteristics

Symbol	Parameter	Package	Value	Unit
		LQFP64 (10 x10 mm) LQFP100 (14 x 14 mm) UFBGA132 (7 x 7 mm) LQFP144 (20 x 20 mm)	36.0 32.2 30.9 34.1
ΘJA	Thermal resistance junction-ambient	WLCSP150 (5.38 x 5.47 mm) TFBGA169 (7 x 7 mm) WLCSP208 (5.38 x 5.47 mm) TFBGA216 (13 x 13 mm) LQFP64 (10 x10 mm)	31.7 32.2 35.4 26.5 18.3
		LQFP100 (14 x14 mm)	18.0	°C/W
	Thermal resistance junction-board	UFBGA132 (7 x 7 mm) LQFP144 (20 x 20 mm)	15.9 22.9
ΘJB		WLCSP150 (5.38 x 5.47 mm) TFBGA169 (7 x 7 mm) WLCSP208 (5.38 x 5.47 mm) TFBGA216 (13 x 13 mm)	13.5 17.7 12.5 16.0
ΘJC		LQFP64 (10 x 10 mm) LQFP100 (14 x 14 mm) UFBGA132 (7 x 7 mm)	6.8 5.9 6.0
	Thermal resistance junction-case	LQFP144 (20 x 20 mm) WLCSP150 (5.38 x 5.47 mm) TFBGA169 (7 x 7 mm) WLCSP208 (5.38 x 5.47 mm) TFBGA216 (13 x 13 mm)	6.0 0.9 9.0 1.0 7.7

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Package information STM32U59xxx

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STM32U595RJ	STMicroelectronics	—
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