STM32H7X3

Part: STM32H742xI/G, STM32H743xI/G

Type: ARM Cortex-M7 MCU

Key Specs:

• Core Frequency: 480 MHz
• Flash Memory: Up to 2 Mbytes
• RAM: Up to 1 Mbyte
• Application Supply Voltage: 1.62 to 3.6 V
• I/O Ports: Up to 168
• Standby Mode Current: 2.95 μA (Backup SRAM OFF, RTC/LSE ON)

Features:

• 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache
• Up to 2 Mbytes of flash memory with read-while-write support
• Up to 1 Mbyte of RAM (192 Kbytes TCM, up to 864 Kbytes user SRAM, 4 Kbytes Backup SRAM)
• Dual mode Quad-SPI memory interface running up to 133 MHz
• Flexible external memory controller with up to 32-bit data bus
• CRC calculation unit
• Security features: ROP, PC-ROP, active tamper
• Up to 168 I/O ports with interrupt capability
• 3 separate power domains (D1, D2, D3)
• Dedicated USB power embedding a 3.3 V internal regulator
• Embedded regulator (LDO) with configurable scalable output
• Voltage scaling in Run and Stop mode (6 configurable ranges)
• Backup regulator (~0.9 V)
• Low-power modes: Sleep, Stop, Standby, VBAT
• VBAT battery operating mode with charging capability
• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4-48 MHz HSE, 32.768 kHz LSE
• 3× PLLs with Fractional mode
• 3 bus matrices (1 AXI, 2 AHB) and bridges
• 4 DMA controllers (MDMA, dual-port DMAs, basic DMA)
• Up to 35 communication peripherals (I2C, USART/UART, LPUART, SPI/I2S, SAI, SPDIFRX, SWPMI, MDIO Slave, SD/SDIO/MMC, CAN FD, TT-CAN, USB OTG, Ethernet MAC, HDMI-CEC, Camera interface)
• 11 analog peripherals (3× ADCs with 16-bit max. resolution, 1× temperature sensor, 2× 12-bit D/A converters, 2× ultra-low-power comparators, 2× operational amplifiers, 1× digital filters for sigma delta modulator)
• Graphics: LCD-TFT controller up to XGA resolution, Chrom-ART graphical hardware Accelerator (DMA2D

Pe	rip her als	G V 2 4 7 H 2 3 M T S	G G G G G G G G G I G G I I I I V ZI A I X V B A X V A X 2I Z B Z B 2I 3I 2 2 2 3 2 2 2 3 2 2 2 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 H H H H H H H H H H H H H H H H H H 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 M M M M M M M M M M M M M M M M M M T T T T T T T T T T T T T T T T T T S S S S S S S S S S S S S S S S S S								ZI 3 4 7 H 2 3 M T S	I A 3 4 7 H 2 3 M T S	I 3I 4 7 H 2 3 M T S	I B 3 4 7 H 2 3 M T S	I X 3 4 7 H 2 3 M T S
Fla sh me	in K by tes mo ry SR AM d o nto ma ppe AX I bu s SR AM 1 ( D2 dom ain )	384		32		2 x 128	51 2 K	by tes	512			32
SR AM in Kby tes	SR AM 2 ( D2 dom ain ) SR AM 3 ( D2 dom ain ) SR AM 4 ( D3 dom ain )	16		64	32	64		128			-	64		16
TC M R AM	ITC M R AM ( ins tion ) truc				64						64
in K by tes	DT CM RA M ( dat a)			128		128						128
Bac kup SR	AM ( Kby ) tes FM C													4 Yes
	GP IOs	82	114	13 1	140	168		82	114	13 1	140		168	82	114
Qu ad-	SP I in terf ace													Yes
Eth	et ern													Yes

		Ta	b le	2. S T M	3 2 H	7 4 2x	I / G an	d S	T M 3 2	H 7 4	3x I / G	fe a	tu re s	d an	ip p er	he ra	l c ou	( ts n	in t co n	d ue	)
Pe rip	her als h- res Hig olu tion Ge al- pur ner pos e	G V 2 4 7 H 2 3 M T S	G Z 2 4 7 H 2 3 M T S 1	G A 2 4 7 H 2 3 M T S	G 2I 4 7 H 2 3 M T S	G B 2 4 7 H 2 3 M T S	G X 2 4 7 H 2 3 M T S	G V 3 4 7 H 2 3 M T S	G Z 3 4 7 H 2 3 M T S	G A 3 4 7 H 2 3 M T S	G 3I 4 7 H 2 3 M T S	G B 3 4 7 H 2 3 M T S	G X 3 4 7 H 2 3 M T S	I V 2 4 7 H 2 3 M T S 10	ZI 2 4 7 H 2 3 M T S	I A 2 4 7 H 2 3 M T S	I 2I 4 7 H 2 3 M T S	I B 2 4 7 H 2 3 M T S	I X 2 4 7 H 2 3 M T S	I V 3 4 7 H 2 3 M T S	ZI 3 4 7 H 2 3 M T S
Tim ers	Ad ced van - con l ( PW M) tro Bas ic Low -po we r	2	2											5
ins Wa Tam 5 6 5 6 5 6 5 4 4 4 4 per p 2 2 2 2 keu ins 2 3 2 3 2 3 2 p p									6 3
Ra ndo m n um	ber ato ge ner r SP I / I 2S I2C US T/ AR / UA RT LP UA RT SA I	4/4 /1 4	(1) 6/3 4											Yes
Co uni	SP DIF RX												4 in	ts pu
mm cat ion	SW PM I													Yes
inte rfac es	MD IO SD MM C FD CA N/T T FD CA N US B O TG FS US B OT G HS													Yes 2 1/1 Yes Yes

• Description

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Figure 5. LQFP100 pinout

1. The above figure shows the package top view.

	1	2	3	4	5	6	7	8	9	10
A	PC14- OSC32_IN	PC13	PE2	PB9	PB7	PB4	PB3	PA15	PA14	PA13
B	PC15- OSC32_OUT	VBAT	PE3	PB8	PB6	PD5	PD2	PC11	PC10	PA12
C	PH0-OSC_IN	VSS	PE4	PE1	PB5	PD6	PD3	PC12	PA9	PA11
D	PH1- OSC_OUT	VDD	PE5	PE0	BOOT0	PD7	PD4	PD0	PA8	PA10
E	NRST	PC2_C	PE6	VSS	VSS	VSS	VCAP	PD1	PC9	PC7
F	PC0	PC1	PC3_C	VDDLDO	VDD	VDD33USB	PDR_ON	VCAP	PC8	PC6
G	VSSA	PA0	PA4	PC4	PB2	PE10	PE14	PD15	PD11	PB15
H	VDDA	PA1	PA5	PC5	PE7	PE11	PE15	PD14	PD10	PB14
J	VSS	PA2	PA6	PB0	PE8	PE12	PB10	PB13	PD9	PD13
K	VDD	PA3	PA7	PB1	PE9	PE13	PB11	PB12	PD8	PD12

1. The above figure shows the package top view.

Figure 7. LQFP144 pinout

1. The above figure shows the package top view.

	1	2	3	4	5	6	7	8	9	10	11	12	13
A	PE4	PE2	VDD	PI6	PB6	PI2	VDD	PG10	PD5	VDD	PC12	PC10	PI0
B	PC15- OSC32_ OUT	PE3	VSS	VDDLDO	PB8	PB4	PI3	PG11	PD6	VSS	PC11	PA14	PI1
C	PC14- OSC32_ IN	PE6	PE5	PDR_ON	PB9	PB5	PG14	PG9	PD4	PD1	PA15	VSS	VDD
D	VDD	VSS	PC13	PE1	PE0	PB7	PG13	PD7	PD3	PD0	PA13	VDDLDO	VCAP
E	PI11	PI7	VBAT	PF1	PF3	BOOT0	PG15	PG12	PD2	PA10	PA9	PA8	PA12
F	PI13	PI12	PF0	PF2	PF5	PF7	PB3	PG4	PC6	PC7	PC9	PC8	PA11
G	VDD	VSS	PF4	PF6	PF9	NRST	PF13	PE7	PG6	PG7	PG8	VDD50_ USB	VDD33_ USB
H	PH0- OSC_ IN	PH1- OSC_ OUT	PF10	PF8	PJ1	PA4	PF14	PE8	PG2	PG3	PG5	VSS	VDD
J	PC0	PC1	VSSA	PJ0	PA0	PA7	PF15	PE9	PE14	PD11	PD13	PD15	PD14
K	PC3_C	PC2_C	PH4	PA1	PA6	PC4	PG0	PE13	PH10	PH12	PD9	PD10	PD12
L	VDDA	VREF+	PH5	PA5	PB1	PB2	PG1	PE12	PB10	PH11	PB13	VSS	VDD
M	VDD	VSS	PH3	VSS	PB0	PF11	VSS	PE10	PB11	VDDLDO	VSS	PD8	PB15
N	PA2	PH2	PA3	VDD	PC5	PF12	VDD	PE11	PE15	VCAP	VDD	PB12	PB14

Figure 8. UFBGA169 ballout

1. The above figure shows the package top view.

Figure 9. LQFP176 pinout

1. The above figure shows the package top view.

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
A	PE3	PE2	PE1	PE0	PB8	PB5	PG14	PG13	PB4	PB3	PD7	PC12	PA15	PA14	PA13
B	PE4	PE5	PE6	PB9	PB7	PB6	PG15	PG12	PG11	PG10	PD6	PD0	PC11	PC10	PA12
C	VBAT	PI7	PI6	PI5	VDD	PDR_ON	VDD	VDD	VDD	PG9	PD5	PD1	PI3	PI2	PA11
D	PC13	PI8	PI9	PI4	VSS	BOOT0	VSS	VSS	VSS	PD4	PD3	PD2	PH15	PI1	PA10
E	PC14- OSC32_ IN	PF0	PI10	PI11							PH13	PH14	PI0	PA9
F	PC15- OSC32_ OUT	VSS	VDD	PH2	VSS	VSS	VSS	VSS	VSS	VSS	VSS	VCAP	PC9	PA8
G	PH0- OSC_IN	VSS	VDD	PH3	VSS	VSS	VSS	VSS	VSS	VSS	VSS	VDD	PC8	PC7
H	PH1- OSC_ OUT	PF2	PF1	PH4	VSS	VSS	VSS	VSS	VSS	VSS	VSS	VDD 3.3USB	PG8	PC6
J	NRST	PF3	PF4	PH5	VSS	VSS	VSS	VSS	VSS	VSS	VDD	VDD	PG7	PG6
K	PF7	PF6	PF5	VDD	VSS	VSS	VSS	VSS	VSS	VSS	PH12	PG5	PG4	PG3
L	PF10	PF9	PF8	VSS							PH11	PH10	PD15	PG2
M	VSSA	PC0	PC1	PC2_C	PC3_C	PB2	PG1	VSS	VSS	VCAP	PH6	PH8	PH9	PD14	PD13
N	VREF-	PA1	PA0	PA4	PC4	PF13	PG0	VDD	VDD	VDD	PE13	PH7	PD12	PD11	PD10
P	VREF+	PA2	PA6	PA5	PC5	PF12	PF15	PE8	PE9	PE11	PE14	PB12	PB13	PD9	PD8
R	VDDA	PA3	PA7	PB1	PB0	PF11	PF14	PE7	PE10	PE12	PE15	PB10	PB11	PB14	PB15

Figure 10. UFBGA176+25 ballout

1. The above figure shows the package top view.

STM32H742xI/G STM32H743xI/G Pin descriptions

Figure 11. LQFP208 pinout

1. The above figure shows the package top view.

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17
A	VSS	PI6	PI5	PI4	PB5	VDD LDO	VCAP	PK5	PG10	PG9	PD5	PD4	PC10	PA15	PI1	PI0	VSS
B	VBAT	VSS	PI7	PE1	PB6	VSS	PB4	PK4	PG11	PJ15	PD6	PD3	PC11	PA14	PI2	PH15	PH14
C	PC15- OSC32_ OUT	PC14- OSC32_ IN	PE2	PE0	PB7	PB3	PK6	PK3	PG12	VSS	PD7	PC12	VSS	PI3	PA13	VSS	VDD LDO
D	PE5	PE4	PE3	PB9	PB8	PG15	PK7	PG14	PG13	PJ14	PJ12	PD2	PD0	PA10	PA9	PH13	VCAP
E	NC(2)	PI9	PC13	PI8	PE6	VDD	PDR_ ON	BOO T0	VDD	PJ13	VDD	PD1	PC8	PC9	PA8	PA12	PA11
F	VSS(3)	VSS(4)	PI10	PI11	VDD								PC7	PC6	PG8	PG7	VDD33 USB
G	PF2	VSS(4)	PF1	PF0	VDD		VSS	VSS	VSS	VSS	VSS		VDD	PG5	PG6	VSS	VDD50 USB
H	PI12	PI13	PI14	PF3	VDD		VSS	VSS	VSS	VSS	VSS		VDD	PG4	PG3	PG2	PK2
J	PH1- OSC_ OUT	PH0- OSC_IN	VSS	PF5	PF4		VSS	VSS	VSS	VSS	VSS		VDD	PK0	PK1	VSS	VSS
K	NRST	PF6	PF7	PF8	VDD		VSS	VSS	VSS	VSS	VSS		VDD	PJ11	VSS	NC	NC
L	VDDA	PC0	PF10	PF9	VDD		VSS	VSS	VSS	VSS	VSS		VDD	PJ10	VSS	NC	NC
M	VREF+	PC1	PC2	PC3	VDD								VDD	PJ9	VSS	NC	NC
N	VREF-	PH2	PA2	PA1	PA0	PJ0	VDD	VDD	PE10	VDD	VDD	VDD	PJ8	PJ7	PJ6	VSS	NC
P	VSSA	PH3	PH4	PH5	PI15	PJ1	PF13	PF14	PE9	PE11	PB10	PB11	PH10	PH11	PD15	PD14	VDD
R	PC2_C	PC3_C	PA6	VSS	PA7	PB2	PF12	VSS	PF15	PE12	PE15	PJ5	PH9	PH12	PD11	PD12	PD13
T	PA0_C	PA1_C	PA5	PC4	PB1	PJ2	PF11	PG0	PE8	PE13	PH6	VSS	PH8	PB12	PB15	PD10	PD9
U	VSS	PA3	PA4	PC5	PB0	PJ3	PJ4	PG1	PE7	PE14	VCAP	VDD LDO	PH7	PB13	PB14	PD8	VSS

Figure 12. TFBGA240+25 ballout

1. The above figure shows the package top view.

2. This ball should remain floating.

3. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.

4. This ball should be connected to VSS.

Name	Abbreviation	Definition
Pin name		Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
	S	Supply pin
	I	Input only pin
Pin type	I/O	Input / output pin
	ANA	Analog-only Input
	FT	5 V tolerant I/O
	TT	3.3 V tolerant I/O
	B	Dedicated BOOT0 pin
	RST	Bidirectional reset pin with embedded weak pull-

Table 9 and Table 10 to Table 20 show STM32H743xI/G pin/ball definition and alternate functions, respectively. Refer to Table 2 for the features and peripherals available on STM32H742xI/G devices.

			Table 9. Pin/ball definition
--	--	--	------------------------------

LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	-	M4	H10
-	-	-	A3	-
6	B2	6	E3	C1
-	-	-	-	J6
-	-	-	-	D2
7	A2	7	D3	D1
-	-	-	-	J7

• LQFP100
• 8
• 9

Table 9. Pin/ball definition (continued)

LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	-	M4	H10
-	-	-	A3	-

Table 9. Pin/ball definition (continued)

LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	-	M4	H10
-	-	-	A3	-

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	-	M4	H10
-	-	-	A3	-
6	B2	6	E3	C1
-	-	-	J6	-
-	-	-	D2	7
7	A2	7	D3	D1
-	-	-	J7	-

Table 9. Pin/ball definition (continued)

68/357 DS12110 Rev 10

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
25	K2	37	N3	R2
26	-	38	G2	K6
-	-	-	-	L4
27	-	39	-	K4
28	G3	40	H6	N4
29	H3	41	L4	P4
30	J3	42	K5	P3
31	K3	43	J6	R3

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
32	G4	44	K6	N5
33	H4	45	N5	P5
-	-	-	N4	-
-	-	-	H12	J9
34	J4	46	M5	R5
35	K4	47	L5	R4
36	G5	48	L6	M6
-	-	-	-	-
-	-	-	J4	-
-	-	-	H5	-
-	-	-	-	-

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	-	-	-
-	-	-	-	-
-	-	49	M6	R6
-	-	50	N6	P6
-	-	51	M11	M8
-	-	52	-	N8
-	-	53	G7	N6
-	-	54	H7	R7
-	-	55	J7	P7
-	-	56	K7	N7
-	-	-	M2	F6
-	-	-	A10	-
-	-	57	L7	M7
37	H5	58	G8	R8
38	J5	59	H8	P8
39	K5	60	J8	P9

Table 9. Pin/ball definition (continued)

• LQFP100
• 40
• 41
• 42
• 43
• 44
• 45

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
46	J7	69	L9	R12
47	K7	70	M9	R13
48	F8	71	N10	M10
49	E4	-	-	K7
-	-	-	M10	-
50	-	72	M1	N10
-	-	-	-	-
-	-	-	-	M11
-	-	-	-	N12
-	-	-	-	M12
-	-	-	-	F8
-	-	-	L13	-

Table 9. Pin/ball definition (continued)

• LQFP100
• 51
• 52

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	H10	-	M4	H10
-	-	-	A3	-

Table 9. Pin/ball definition (continued)

LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25	Pin/ball name
1	A3	1	A2	A2	PE2
2	B3	2	B2	A1	PE3
3	C3	3	A1	B1	PE4
4	D3	4	C3	B2	PE5
5	E3	5	C2	B3	PE6
-	-	-

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	-

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	-	-	-
-	-	89	F8	K14
-	-	90	H11	K13
-	-	91	G9	J15
-	-	92	G10	J14
-	-	93	G11	H14
-	-	94	-	G12
-	-	-	G12	-
-	F6	95	G13	H13
-	-	-	-	-
63	F10	96	F9	H15

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-

			Table 9. Pin/ball definition (continued)
--	--	--	------------------------------------------

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
69	D10	102	E10	D15
70	C10	103	F13	C15
71	B10	104	E13	B15
72	A10	105	D11	A15
73	E7	106	D13	F13
74	E5	107	-	F12
-	-	-	D12	-
75	-	108	-	G13
-	-	-	-	E12
-	-	-	-	E13

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	-

Table 9. Pin/ball definition (continued)

• 1
• 2
• 3
• 4
• 5
• 6
• 7

Table 9. Pin/ball definition (continued)

• 1
• 2
• 3
• 4
• 5
• 6
• 7

Table 9. Pin/ball definition (continued)

LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
1	A3	1	A2	A2
2	B3	2	B2	A1
3	C3	3	A1	B1
4	D3	4	C3	B2
5	E3	5	C2	B3
-	-	-	M4	H10
-	-	-	A3

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	132	E7	B7
89	A7	133	F7	A10
90	A6	134	B6	A9
91	C5	135	C6	A6
-	-	-	-	H8
92	B5	136	A5	B6

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
93	A5	137	D6	B5
94	D5	138	E6	D6
95	B4	139	B5	A5
96	A4	140	C5	B4
97	D4	141	D5	A4
98	C4	142	D4	A3
-	-	-	-	-
99	-	-	-	D5

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	F7	143	C4	C6
-	F4	-	B4	-
100	-	144	-	C5
-	-	-	-	D4
-	-	-	-	C4
-	-	-	A4	C3
-	-	-	E2	C2
-	-	-	-	H9
-	-	-	-	K9
-	-	-	-	K10

Table 9. Pin/ball definition (continued)

1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is valid for all resets except for power-on reset.

2. This ball should remain floating.

1. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.

4. This ball should be connected to VSS.

5. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits.

6. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits.

• 1. VREF+ pin, and consequently the internal voltage reference, are not available on the TFBGA100 package. On this package, this pin is double-bonded to VDDA which can be connected to an external reference. The internal voltage reference buffer is not available and must be kept disabled
• 8. When it is not available on a package, the VDDLDO pin is internally tied to VDD.
• 9. When the pin is used in USB configuration (OTG_HS_ID/OTG_HS_VBUS), the I/O is supplied by VDD33USB, otherwise it is supplied by VDD.
• 1. When it is not available on a package, the VDD50USB pin is internally tied to VDD33USB.

88/357 DS12110 Rev 10

		AF0	AF 1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF 10	AF 11	AF 12	AF 13	AF 14	AF 15
Por t		SYS	16/ 17/L TIM 1/2/ M1/ HRT PTI IM1	SAI / 4/5/ 1/T IM3 12/ HRT IM1	LPU / TIM ART 8/ LPT / 5/H IM2 /3/4 M1/ DFS RTI DM 1	I2C 3/4/ USA 1/2/ / TIM RT1 15/ LPT / DFS IM2 1/ CEC DM	SPI 3/4/ 5/6/ 1/2/ CEC	SPI 1/ 3/I2 2/3/ SAI C4/ UAR T4/ DFS DM 1	6/ USA SPI 2/3/ /2/ 3/6/ RT1 T7/ SD UAR MM C1	/ 4/U SPI 6/S AI2 4/5/ 8/L ART RT/ SD PUA C1/ SPD MM IFR X1	4/ FDC SAI 1/2/ TIM AN 4/ QU 13/1 / FM SPI AD C/ SD C2/ LCD MM / SPD IFR X1	SAI 2/4/ TIM 8/ QU / SD AD SPI C2/ OTG MM S/ OTG 1_H S/ LCD 2_F	4/ UAR I2C T7/ SW I1/ TIM PM 1/8/ DFS 1/ SD DM C2/ MD MM / ETH IOS	TIM C /SD 1/8/ FM C1/ MD MM / OTG IOS S/ LCD 1_F	TIM I /LC 1/D CM D/ CO MP	T5/ LCD UAR	SYS
	PA0	-	TIM H1/ TIM 2_C 2_E TR	5_C TIM H1	TIM 8_E TR	TIM 15_ BKI N	-	-	USA RT2 CTS / USA RT2 NSS	UAR T4_ TX	SD C2_ CM MM D	SAI 2_S D_B	ETH II_ CR _M S	-	-	-	EVE NT- OU T
	PA1	-	TIM 2_C H2	TIM 5_C H2	LPT IM3 _ OU T	TIM 15_ CH 1N	-	-	USA RT2 RTS / USA RT2 DE	UAR T4_ RX	QU AD SPI _ BK1 _IO 3	SAI 2_M CLK _B	ETH M II RX_ CLK / ETH RM II REF _CL K	-	-	LCD _R2	EVE NT- OU T
	PA2	-	TIM 2_C H3	TIM 5_C H3	LPT IM4 _ OU T	TIM 15_ CH 1	-	-	USA RT2 _ TX	SAI 2_S CK_ B	-	-	ETH _M DIO	IOS MD _ MD IO	-	LCD _R1	EVE NT- OU T
	PA3	-	TIM 2_C H4	TIM 5_C H4	LPT IM5 _ OU T	TIM 15_ CH 2	-	-	USA RT2 _ RX	-	LCD _B2	OTG HS ULP I_D 0	ETH II_ CO _M L	-	-	LCD _B5	EVE NT- OU T
	PA4	D1 PW REN	-	TIM 5_E TR	-	-	SPI SS/ I2S 1_N 1_W S	SPI SS/ I2S 3_N 3_W S	USA RT2 _ CK	SPI 6_N SS	-	-	-	OTG HS SO F	MI_ HSY DC NC	LCD _ VSY NC	EVE NT- OU T
	PA5	D2 PW REN	TIM H1/ TIM 2_C 2_E TR	-	TIM 8_ CH 1N	-	SPI CK /I2S 1_S 1_C K	-	-	SP I6_S CK	-	OTG HS ULP I_C K	-	-	-	LCD _R4	EVE NT- OU T
	PA6	-	TIM 1_B KIN	TIM 3_C H1	TIM 8_B KIN	-	SPI ISO /I2S 1_M 1_S DI	-	-	SP I6_M ISO	TIM 13_ CH 1	TIM 8_B KIN _CO MP 12	MD IOS _ MD C	TIM 1_B KIN _CO MP 12	DC PIX CLK MI_	LCD _G2	EVE NT- OU T
	PA7	-	TIM 1_C H1N	TIM 3_C H2	8_C TIM H1 N	-	SPI OS 1_M I /I2S 1_S DO	-	-	SP I6_M OS I	TIM 14_ CH 1	-	ETH M II DV/ RX_ ETH RM II CR S_D V	C_S FM DN WE	-	-	EVE NT OU T
	PA8	MC O1	TIM 1_C H1	HRT CH B2 IM_	TIM 8_B KIN 2	I2C 3_S CL	-	-	USA RT1 _ CK	-	-	OTG FS SO F	UAR T7_ RX	KIN 2_C TIM 8_B OM P12	LCD _B3	LCD _R6	EVE NT- OU T
	PA9	-	1_C TIM H2	HRT CH C1 IM_	LPU 1_ TX ART	I2C 3_S MB A	SPI CK/ I2S 2_S 2_C K	-	USA RT1 _ TX	-	-	-	-	-	DC MI_ D0	LCD _R5	EVE NT- OU T
	PA1 0	-	TIM 1_C H3	HRT CH C2 IM_	LPU 1_ RX ART	-	-	-	USA RT1 _ RX	-	-	OT G_F S_I D	MD IOS _ MD IO	LCD _B4	DC MI_ D1	LCD _B1	EVE NT- OU T
	PA1 1	-	TIM 1_C H4	HRT CH D1 IM_	LPU 1_ CTS ART	-	SPI SS /I2S 2_N S 2_W	UAR T4_ RX	USA RT1 CTS / USA RT1 NSS	-	FDC AN 1_ RX	OTG FS DM	-	-	-	LCD _R4	EVE NT- OU T
	PA1 2	-	TIM 1_E TR	HRT CH D2 IM_	LPU ART 1_ RTS / LPU ART 1_ DE	-	SPI 2_S CK/ I2S 2_C K	UAR T4_ TX	USA RT1 RTS / USA RT1 DE	SAI 2_F S_B	FDC 1_ TX AN	OTG FS DP	-	-	-	LCD _R5	EVE NT- OU T

STM32H742xI/G STM32H743xI/G Pin descriptions

ુદ્દાદક

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at TJ = 25 °C and TJ = TJmax (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V (for the 1.7 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 13.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 14.

102/357 DS12110 Rev 10

6.1.6 Power supply scheme

Figure 15. Power supply scheme

1. N corresponds to the number of VDD pins available on the package.

2. A tolerance of +/- 20% is acceptable on decoupling capacitors.

Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the

device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.

6.1.7 Current consumption measurement

Figure 16. Current consumption measurement scheme

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics, Table 22: Current characteristics, and Table 23: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Symbols	Ratings	Min	Max	Unit
VDDX - VSS	External main supply voltage (including VDD, VDDLDO, VDDA, VDD33USB, VBAT)	-0.3	4.0	V
VIN(2)	Input voltage on FT_xxx pins	VSS-0.3	Min(VDD, VDDA, VDD33USB, VBAT) +4.0(3)(4)	V
	Input voltage on TT_xx pins	VSS-0.3	4.0	V
	Input voltage on BOOT0 pin	VSS	9.0	V
	Input voltage on any other pins	VSS-0.3	4.0	V
∆VDDX	Variations between different VDDX power pins of the same domain	-	50	mV
|VSSx-VSS|	Variations between all the different ground pins	-	50	mV

Symbols	Ratings	Min	Max	Unit
VDDX - VSS	External main supply voltage (including VDD, VDDLDO, VDDA, VDD33USB, VBAT)	-0.3	4.0	V
VIN(2)	Input voltage on FT_xxx pins	VSS - 0.3	Min(VDD, VDDA, VDD33USB, VBAT) +4.0(3)(4)	V
	Input voltage on TT_xx pins	VSS - 0.3	4.0	V
	Input voltage on BOOT0 pin	VSS	9.0	V
	Input voltage on any other pins	VSS - 0.3	4.0	V
	Variations between different VDDX power pins of the same domain	-	50	mV
	Variations between all the different ground pins	-	50	mV

1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. VIN maximum must always be respected. Refer to Table 59 for the maximum allowed injected current values.

• 1. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
• 1. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.

Symbols	Ratings	Max	Unit
ΣIVDD	Total current into sum of all VDD power lines (source)(1)	620	mA
ΣIVSS	Total current out of sum of all VSS ground lines (sink)(1)	620	mA
IVDD	Maximum current into each VDD power pin (source)(1)	100	mA
IVSS	Maximum current out of each VSS ground pin (sink)(1)	100	mA
IIO	Output current sunk by any I/O and control pin, except Px_C	20	mA
	Output current sunk by Px_C pins	1	mA
ΣI(PIN)	Total output current sunk by sum of all I/Os and control pins(2)	140	mA
	Total output current sourced by sum of all I/Os and control pins(2)	140	mA
IINJ(PIN)(3)(4)	Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5	-5/+0	mA
	Injected current on PA4, PA5	-0/0	mA
ΣIINJ(PIN)	Total injected current (sum of all I/Os and control pins)(5)	±25	mA

Table 22. Current characteristics

1. All main power (VDD, VDDA, VDD33USB) and ground (VSS, VSSA) pins must always be connected to the external power supplies, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.

1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.

• 1. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer also to Table 21: Voltage characteristics for the maximum allowed input voltage values.
• 1. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	- 65 to +150	°C
TJ	Maximum junction temperature	125	°C

Table 23. Thermal characteristics

6.3 Operating conditions

6.3.1 General operating conditions

Symbol	Parameter	Operating conditions	Min	Max	Unit
VDD	Standard operating voltage	-	1.62(1)	3.6
VDDLDO	Supply voltage for the internal regulator	VDDLDO ≤ VDD	1.62(1)	3.6
VDD33USB	Standard operating voltage, USB domain	USB used	3.0	3.6
		USB not used	0	3.6
VDDA	Analog operating voltage	ADC or COMP used	1.62	3.6	V

Table 24. General operating conditions

1. When RESET is released functionality is guaranteed down to VBOR0 min

1. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.

2. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must be disabled.

4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.10: Thermal characteristics).

6.3.2 VCAP external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP pin. CEXT is specified in Table 25. Two external capacitors can be connected to VCAP pins.

Figure 17. External capacitor CEXT

1. Legend: ESR is the equivalent series resistance.

Table 25. VCAP operating conditions(1)

Symbol	Parameter	Conditions
CEXT	Capacitance of external capacitor	2.2 μF(2)
ESR	ESR of external capacitor	< 100 mΩ

1. When bypassing the voltage regulator, the two 2.2 μF VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors.

2. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.

6.3.3 Operating conditions at power-up / power-down

Subject to general operating conditions for TA.

Symbol	Parameter	Min	Max	Unit
tVDD	VDD rise time rate	0	∞
	VDD fall time rate	10	∞
tVDDA	VDDA rise time rate	0	∞
	VDDA fall time rate	10	∞	μs/V
tVDDUSB	VDDUSB rise time rate	0	∞
	VDDUSB fall time rate	10	∞

Table 26. Operating conditions at power-up / power-down (regulator ON)

6.3.4 Embedded reset and power control block characteristics

The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tRSTTEMPO(1)	Reset temporization after BOR0 released	-	-	377	-	μs
	Brown-out reset threshold 0	Rising edge(1)	1.62	1.67	1.71
VBOR0/POR/PDR	(VPOR/VPDR thresholds)	Falling edge	1.58	1.62	1.68
	Brown-out reset threshold 1	Rising edge	2.04	2.10	2.15
VBOR1		Falling edge	1.95	2.00	2.06
		Rising edge	2.34	2.41	2.47
VBOR2	Brown-out reset threshold 2	Falling edge	2.25	2.31	2.37
	Brown-out reset threshold 3	Rising edge	2.63	2.70	2.78
VBOR3		Falling edge	2.54	2.61	2.68
	Programmable Voltage Detector threshold 0	Rising edge	1.90	1.96	2.01
VPVD0		Falling edge	1.81	1.86	1.91
	Programmable Voltage Detector threshold 1	Rising edge	2.05	2.10	2.16
VPVD1		Falling edge	1.96	2.01	2.06	V
	Programmable Voltage Detector threshold 2	Rising edge	2.19	2.26	2.32
VPVD2		Falling edge	2.10	2.15	2.21
	Programmable Voltage Detector threshold 3	Rising edge	2.35	2.41	2.47
VPVD3		Falling edge	2.25	2.31	2.37
	Programmable Voltage	Rising edge	2.49	2.56	2.62
VPVD4	Detector threshold 4	Falling edge	2.39	2.45	2.51
VPVD5	Programmable Voltage Detector threshold 5	Rising edge	2.64	2.71	2.78
		Falling edge	2.55	2.61	2.68
VPVD6	Programmable Voltage Detector threshold 6	Rising edge	2.78	2.86	2.94
		Falling edge in Run mode	2.69	2.76	2.83
Vhyst_BOR_PVD	Hysteresis voltage of BOR Hysteresis in Run mode (unless BOR0) and PVD		-	100	-	mV
IDD_BOR_PVD(1)	BOR(2) (unless BOR0) and PVD consumption from VDD	-	-	-	0.630	μA

			Table 27. Reset and power control block characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tRSTTEMPO$^{(1)}$	Reset temporization after BOR0 released	-	-	377	-	µs
VBOR0/POR/PDR	Brown-out reset threshold 0 (VPOR/VPDR thresholds)	Rising edge$^{(1)}$	1.62	1.67	1.71	V
VBOR0/POR/PDR	Brown-out reset threshold 0 (VPOR/VPDR thresholds)	Falling edge	1.58	1.62	1.

Table 27. Reset and power control block characteristics (continued)

1. Guaranteed by design.

1. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to Section 6.3.6: Supply current characteristics).

6.3.5 Embedded reference voltage

The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VREFINT	Internal reference voltages	-40°C < TJ < 105°C, VDD = 3.3 V	1.180	1.216	1.255	V
tS_vrefint(1)(2)	ADC sampling time when reading the internal reference voltage	-	4.3	-	-	μs
tS_vbat(1)(2)	VBAT sampling time when reading the internal VBAT reference voltage	-	9	-	-	μs
Irefbuf(2)	Reference Buffer consumption for ADC	VDDA=3.3 V	9	13.5	23	μA
ΔVREFINT(2)	Internal reference voltage spread over the temperature range	-40°C < TJ < 105°C	-	5	15	mV
Tcoeff(2)	Average temperature coefficient	Average temperature coefficient	-	20	70	ppm/°C
VDDcoeff(2)	Average Voltage coefficient	3.0V < VDD < 3.6V	-	10	1370	ppm/V

	Table 28. Embedded reference voltage
--	--------------------------------------

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VREFINT	Internal reference voltages	-40°C < TJ < 105°C, VDD = 3.3 V	1.180	1.216	1.255	V
tS_vrefint^(1)(2)	ADC sampling time when reading the internal reference voltage	-	4.3	-	-	µs
tS_vbat^(1)(2)	VBAT sampling time when reading the internal VBAT reference voltage	-	9	-	-
Irefbuf^(2)	Reference Buffer consumption for ADC	VDDA=3.3 V	9	13.5	23	µA
ΔVREFINT^(2)	Internal reference voltage spread over the temperature range	-40°C < TJ < 105°C	-	5	15	mV
Tcoeff^(2)	Average temperature coefficient	Average temperature coefficient	-	20	70	ppm/°C
VDDcoeff^(2)	Average Voltage coefficient	3.0V < VDD < 3.6V	-	10	1370	ppm/V

Table 28. Embedded reference voltage (continued)

1. The shortest sampling time for the application can be determined by multiple iterations.

2. Guaranteed by design.

Table 29. Internal reference voltage calibration values

Symbol	Parameter	Memory address
VREFIN_CAL	Raw data acquired at temperature of 30 °C, VDDA = 3.3 V	1FF1E860 - 1FF1E861

6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 16: Current consumption measurement scheme.

All the run-mode current consumption measurements given in this section are performed with a CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The flash memory access time is adjusted with the minimum wait states number, depending on the fACLK frequency (refer to the table "Number of wait states according to CPU clock (frcc_c_ck) frequency and VCORE range" available in the reference manual).
• When the peripherals are enabled, the AHB clock frequency is the CPU frequency divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.

The parameters given in Table 30 to Table 38 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions.

Symbol		Conditions		frcc_c_ck (MHz)
	Parameter
		All peripherals disabled	VOS1	400
				300
			VOS2	300
	Supply current in Run mode			216
				200
				200
				180
			VOS3	168
IDD				144
				60
				25
		All peripherals		400
			VOS1	300
				300
		enabled	VOS2	200
			VOS3	200

Table 30. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator ON(1)

1. Data are in DTCM for best computation performance, cache has no influence on consumption in this case.

2. Guaranteed by characterization results unless otherwise specified.

3. Guaranteed by test in production.

		Conditions		frcc_c_ck (MHz)
Symbol	Parameter
			VOS1	400
				300
				300
		All peripherals disabled	VOS2	216
				200
	Supply current in Run mode			200 180 30 - - -
			VOS3	168
IDD				144
				60
				25
		VOS1 All peripherals VOS2 enabled		400
				300
				300
				200
			VOS3	200

Table 31. Typical and maximum current consumption in Run mode, code with data processing running from flash memory, cache ON, regulator ON

1. Guaranteed by characterization results unless otherwise specified.

Table 32. Typical and maximum current consumption in Run mode, code with data processing running from flash memory, cache OFF, regulator ON

Symbol	Parameter	Conditions
IDD	Supply current in Run mode	All peripherals disabled
		All peripherals

1. Guaranteed by characterization results.

Symbol	Parameter	Peripheral	Code	frcc_c_ck (MHz)	CoreMark	Typ	Unit	IDD/CoreMark	Unit
	Supply current in Run mode	All peripherals disabled, cache ON	ITCM	400	2012	71		35	μA/ CoreMark
			FLASH A	400	2012	105		52
			AXI SRAM	400	20

Table 33. Typical consumption in Run mode and corresponding performance versus code position

Table 34. Typical current consumption batch acquisition mode

Symbol	Parameter	Conditions	frcc_ahb_ck(AHB4) (MHz)	Typ	unit
IDD	Supply current in batch acquisition mode	D1Standby, D2Standby, D3Run VOS3	64	6.5	mA
		D1Stop, D2Stop, D3Run VOS3	64	12

Table 35. Typical and maximum current consumption in Sleep mode, regulator ON

		Conditions
Symbol	Parameter
Supply IDD(Sleep) current in		All peripherals disabled
	Sleep mode

Symbol	Parameter	Conditions	Typ	TJ = 25°C	TJ = 85°C	TJ = 105°C	TJ = 125°C	unit
	D1Stop, D2Stop, D3Stop	Flash memory in low-power mode, no IWDG	SVOS5	1.4	7.2(2)	49	75(2) 140
			SVOS4	1.95	11	66	110	200
IDD(Stop)			SVOS3	2.85	16(2)	91	150(2)	240
		Flash	SVOS5	1.65	7.2	49	75	140
		memory ON,	SVOS4	2.2	11	66	110	180
		no IWDG	SVOS3	3.15	16	91	150	300
	D1Stop, D2Standby, D3Stop	Flash memory OFF, no IWDG	SVOS5	0.99	5.1	35	60	97
			SVOS4	1.4	7.5	47	79	130
			SVOS3	2.05	12	64	110	170
		Flash memory ON,	SVOS5	1.25	5.5	35	61	98
			SVOS4	1.65	7.8	47	80	130
		no IWDG	SVOS3	2.3	12	65	110	170
	D1Standby,		SVOS5	0.57	3	21	36	57
	D2Stop,	Flash OFF,	SVOS4	0.805	4.5	27	47	74
	D3Stop		SVOS3	1.2	6.7	37	63	99
	D1Standby,	no IWDG	SVOS5	0.17	1.1(2)	8	13(2)	20
	D2Standby,		SVOS4	0.245	1.5	11	17	26
	D3Stop		SVOS3	0.405	2.4(2)	15	23(2)	35
Table 36. Typical and maximum current consumption in Stop mode, regulator ON
------------------------------------------------------------------------------	--	--	--	--
------------------------------------------------------------------------------	--	--	--	--

1. Guaranteed by characterization results.

2. Guaranteed by test in production.

Table 37. Typical and maximum current consumption in Standby mode

Symbol	Parameter	Conditions		Typ(3)				Max (3 V)(1)
		Backup SRAM	RTC & LSE	1.62 V	2.4 V	3 V	3.3 V	TJ = 25°C
IDD (Standby)	Supply current in Standby mode	OFF	OFF	1.8	1.9	1.95	2.05	4(2)
		ON	OFF	3.4	3.4	3.5	3.7	8.2(3)
		OFF	ON	2.4	3.5	3.86	4.12	-
		ON	ON	3.95	5.1	5.46	5.97	-

2. Guaranteed by test in production.

3. Guaranteed by characterization results.

Symbol	Parameter	Conditions		Typ(1)				Max (3 V)
		Backup SRAM	RTC & LSE	1.2 V	2 V	3 V	3.4 V	TJ = 25°C
IDD (VBAT)	Supply current in standby mode	OFF	OFF	0.024	0.035	0.062	0.096	0.5(1)
		ON	OFF	1.4	1.6	1.8	1.8	4.4(1)
		OFF	ON	0.24	0.45	0.62	0.73	-
		ON	ON	1.97	2.37	2.57	2.77	-

1. Guaranteed by characterization results.

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up or pull-down generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 60: I/O static characteristics.

For the output pins, any internal or external pull-up or pull-down, and any external load must also be considered to estimate the current consumption.

An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 39: Peripheral current consumption in Run mode), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the internal or external capacitive load connected to the pin:

$mathfrak{l}_mathsf{SW} = mathsf{V}_mathsf{DDx} × mathfrak{f}_mathsf{SW} × mathsf{C}_mathsf{L}where

ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDDx is the MCU supply voltage fSW is the I/O switching frequency

CL is the total capacitance seen by the I/O pin: C = CINT+ CEXT

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

On-chip peripheral current consumption

The MCU is placed under the following conditions:

• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• The I/O compensation cell is enabled.
• frcc_cck is the CPU clock. fPCLK = frcc_cck/4, and fHCLK = frcc_cck/2. The given value is calculated by measuring the difference of current consumption
  • with all peripherals clocked off
  • with only one peripheral clocked on
  • frcc_cck = 400 MHz (Scale 1), frcc_cck = 300 MHz (Scale 2), frcc_cck = 200 MHz (Scale 3)
• The ambient operating temperature is 25 °C and VDD=3.3 V.

Peripheral	IDD(Typ)			Unit
	VOS1	VOS2	VOS3
	MDMA	8.3	7.6	7
	DMA2D	21	20	18
	JPEG	24	23	21
	FLASH	9.9	9	8.3
	FMC registers	0.9	0.9	0.8
	FMC kernel	6.1	5.5	5.3

Peripheral		IDD(Typ)
		VOS1
	DCMI	1.7
	RNG registers	1.8
	RNG kernel	-
	SDMMC2 registers	13
	SDMMC2 kernel	2.7
AHB2	D2SRAM1	3.3
	D2SRAM2	2.9
	D2SRAM3	1.9
	AHB2 bridge	0.1
	GPIOA	1.1
	GPIOB	1
	GPIOC	1.4
	GPIOD	1.1
	GPIOE	1
	GPIOF	0.9
	GPIOG	0.9
	GPIOH	1
AHB4	GPIOI	0.9
	GPIOJ	0.9
	GPIOK	0.9
	CRC	0.5
	BDMA	6.2
	ADC3 registers	1.8
	ADC3 kernel	0.1
	Backup SRAM	1.9
	Bridge AHB4	0.1
	LCD-TFT	12
APB3	WWDG1	0.5
	APB3 bridge Table 39. Peripheral current consumption in Run mode (continued)	0.5
--	------------------------------------------------------------------	--

		IDD(Typ)
	Peripheral	VOS1
	TIM2	3.5
APB1	TIM3	3.4
	TIM4	2.7
	TIM5	3.2
	TIM6	1
	TIM7	1
	TIM12	1.7
	TIM13	1.5
	TIM14	1.4
	LPTIM1 registers	0.7
	LPTIM1 kernel	2.3
	WWDG2	0.6
	SPI2 registers	1.8
	SPI2 kernel	0.6
	SPI3 registers	1.5
	SPI3 kernel	0.6
	SPDIFRX1 registers	0.6
	SPDIFRX1 kernel	2.9
	USART2 registers	1.4
	USART2 kernel	4.7
	USART3 registers	1.4
	USART3 kernel	4.2
	UART4 registers	1.5
	UART4 kernel	3.7

Peripheral		IDD(Typ)
		VOS1
	UART5 registers	1.4
	UART5 kernel	3.6
	I2C1 registers	0.8
	I2C1 kernel	2
	I2C2 registers	0.7
	I2C2 kernel	1.9
	I2C3 registers	0.9
	I2C3 kernel	2.1
	HDMI-CEC registers	0.5
	DAC1/2	1.4
APB1	USART7 registers	1.9
(continued)	USART7 kernel	4
	USART8 registers	1.6
	USART8 kernel	4
	CRS	3.4
	SWPMI registers	2.3
	SWPMI kernel	0.1
	OPAMP	0.5
	MDIO	2.7
	FDCAN registers	16
	FDCAN kernel	7.8
	Bridge APB1	0.1
Table 39. Peripheral current consumption in Run mode (continued)
------------------------------------------------------------------	--

Peripheral			IDD(Typ)
		VOS1	VOS2
	TIM1	5.1	4.8
	TIM8	5.4	4.9
APB2	USART1 registers	2.7	2.6
	USART1 kernel	0.1	0.1
	USART6 registers	2.6	2.5
	USART6 kernel	0.1	0.1
	SPI1 registers	1.8	1.6
	SPI1 kernel	1	0.8
	SPI4 registers	1.6	1.5
	SPI4 kernel	0.5	0.4
	TIM15	3.1	2.8
	TIM16	2.4	2.1
	TIM17	2.2	2
	SPI5 registers	1.8	1.7
	SPI5 kernel	0.6	0.5
	SAI1 registers	1.5	1.4
	SAI1 kernel	2	1.7
	SAI2 registers	1.5	1.5
	SAI2 kernel	2.2	1.9
	SAI3 registers	1.8	1.6
	SAI3 kernel	2.5	2.3
	DFSDM1 registers	6	5.4
	DFSDM1 kernel	0.9	0.8
	HRTIM	40	37
	Bridge APB2	0.1	0.1

Peripheral			IDD(Typ)
		VOS1	VOS2
	SYSCFG	1	0.7
	LPUART1 registers	1.1	1.1
	LPUART1 kernel	2.6	2.4
	SPI6 registers	1.6	1.5
	SPI6 kernel	0.2	0.2
	I2C4 registers	0.1	0.1
	I2C4 kernel	2.4	2.1
	LPTIM2 registers	0.5	0.5
	LPTIM2 kernel	2.3	2.1
	LPTIM3 registers	0.5	0.5
APB4	LPTIM3 kernel	2	2.1
	LPTIM4 registers	0.5	0.5
	LPTIM4 kernel	2	2
	LPTIM5 registers	0.5	0.5
	LPTIM5 kernel	2	1.8
	COMP1/2	0.7	0.5
	VREFBUF	0.6	0.4
	RTC	1.2	1.1
	SAI4 registers	1.6	1.5
	SAI4 kernel	1.3	1.3
	Bridge APB4	0.1	0.1

Table 40. Peripheral current consumption in Stop, Standby and VBAT mode

Symbol	Parameter	Conditions	Typ	Unit
			3 V
	RTC+LSE low drive	-	2.32	μA
	RTC+LSE medium low drive	-	2.4
IDD	RTC+LSE medium high drive	-	2.7
	RTC+LSE High drive	-	3

6.3.7 Wakeup time from low-power modes

The wakeup times given in Table 41 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and VDD=3.3 V.

Symbol	Parameter	Conditions		Max(1)	Unit
tWUSLEEP(2)	Wakeup from Sleep	-	9	10	CPU clock cycles
		VOS3, HSI, flash memory in normal mode	4.4	5.6
		VOS3, HSI, flash memory in low-power mode	12	15
		VOS4, HSI, flash memory in normal mode	15	20
tWUSTOP(2)		VOS4, HSI, flash memory in low-power mode	23	28
		VOS5, HSI, flash memory in normal mode	30	71
	Wakeup from Stop	VOS5, HSI, flash memory in low-power mode	38	47
		VOS3, CSI, flash memory in normal mode	27	37
		VOS3, CSI, flash memory in low power mode	36	50	μs
		VOS4, CSI, flash memory in normal mode	38	48
		VOS4, CSI, flash memory in low-power mode	47	61
		VOS5, CSI, flash memory in normal mode	52	64
		VOS5, CSI, flash memory in low-power mode		62	77
tWUSTOP2(2)	Wakeup from Stop,	VOS3, HSI, flash memory in normal mode	2.6	3.4
	clock kept running	VOS3, CSI, flash memory in normal mode	26	36
tWUSTDBY(2)	Wakeup from Standby mode	-	390	500

Table 41. Low-power mode wakeup timings

1. Guaranteed by characterization results.

2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.

6.3.8 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.

The external clock signal has to respect the Table 60: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 18.

Symbol	Parameter	Min	Typ	Max	Unit
fHSEext	User external clock source frequency	4	25	50	MHz
VHSEH	Digital OSCIN input high-level voltage	0.7 VDD	-	VDD	V
VHSEL	Digital OSCIN input low-level voltage	VSS	-	0.3 VDD
tW(HSE)	OSCIN high or low time	7	-	-	ns

Table 42. High-speed external user clock characteristics(1)

1. Guaranteed by design.

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 60: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 19.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fLSEext	User external clock source frequency	-	-	32.768	1000	kHz
VLSEH	OSC32IN input pin high level voltage	-	0.7 VDDIOx	-	VDDIOx	V
VLSEL	OSC32IN input pin low level voltage	-	VSS	-	0.3 VDDIOx
tw(LSEH) tw(LSEL)	OSC32IN high or low time	-	250	-	-	ns

	Table 43. Low-speed external user clock characteristics(1)
--	------------------------------------------------------------

1. Guaranteed by design.

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs" available from the ST website www.st.com.

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 44. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol	Parameter	Operating conditions(2)	Min	Typ	Max	Unit
F	Oscillator frequency	-	4	-	48	MHz
RF	Feedback resistor	-	-	200	-	kΩ
		During startup(3)	-	-	4
IDD(HSE) HSE current consumption		VDD=3 V, Rm=30 Ω CL=10pF@4MHz	-	0.35	-
		VDD=3 V, Rm=30 Ω CL=10 pF at 8 MHz	-	0.40	-
	VDD=3 V, Rm=30 Ω CL=10 pF at 16 MHz	-	0.45	-	mA
		VDD=3 V, Rm=30 Ω CL=10 pF at 32 MHz	-	0.65	-
		VDD=3 V, Rm=30 Ω CL=10 pF at 48 MHz	-	0.95	-
Gmcritmax	Maximum critical crystal gm	Startup	-	-	1.5	mA/V
tSU(4)	Start-up time	VDD is stabilized	-	2	-	ms

Table 44. 4-48 MHz HSE oscillator characteristics(1)

1. Guaranteed by design.

2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.

• 1. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
• 1. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors, designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 20). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. The PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2.

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs" available from the ST website www.st.com.

Figure 20. Typical application with an 8 MHz crystal

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 45. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol	Parameter	Operating conditions(2)	Min	Typ	Max	Unit
F	Oscillator frequency	-	-	32.768	-	kHz
LSE current IDD consumption		LSEDRV[1:0] = 00, Low drive capability	-	290	-
		LSEDRV[1:0] = 01, Medium Low drive capability	-	390	-
	LSEDRV[1:0] = 10, Medium high drive capability	-	550	-	nA
	LSEDRV[1:0] = 11, High drive capability	-	900	-
Gmcritmax gm		LSEDRV[1:0] = 00, Low drive capability	-	-	0.5
	Maximum critical crystal	LSEDRV[1:0] = 01, Medium Low drive capability	-	-	0.75	μA/V
		LSEDRV[1:0] = 10, Medium high drive capability	-	-	1.7
		LSEDRV[1:0] = 11, High drive capability	-	-	2.7
tSU(3)	Startup time	VDD is stabilized	-	2	-	s

Table 45. Low-speed external user clock characteristics(1)

1. Guaranteed by design.

DS12110 Rev 10 127/357

• 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for STM8AL/AF/S, STM32 MCUs and MPUs".
• 1. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
• Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for STM8AL/AF/S, STM32 MCUs and MPUs" available from the ST website www.st.com.

Figure 21. Typical application with a 32.768 kHz crystal

1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

6.3.9 Internal clock source characteristics

The parameters given in Table 46 and Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

48 MHz high-speed internal RC oscillator (HSI48)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI48	HSI48 frequency	VDD=3.3 V, TJ=30 °C	47.5(1)	48	48.5(1)	MHz
TRIM(2)	USER trimming step	-	-	0.17	-	%
USER TRIM COVERAGE(3)	USER TRIMMING Coverage	± 32 steps	-	±5.45	-	%
DuCy(HSI48)(2)	Duty Cycle	-	45	-	55	%
ACCHSI48REL(3)	Accuracy of the HSI48 oscillator over temperature (factory calibrated)	VDD=1.62 to 3.6 V, TJ=-40 to 125 °C	–4.5	-	3.5	%
∆VDD(HSI48)(3)	HSI48 oscillator frequency drift with	VDD=3 to 3.6 V	-	0.025	0.05
	VDD(4)	VDD=1.62 V to 3.6 V	-	0.05	0.1	%
tsu(HSI48)(2)	HSI48 oscillator start-up time	-	-	2.1	3.5	μs
IDD(HSI48)(2)	HSI48 oscillator power consumption	-	-	350	400	μA
NT jitter	Next transition jitter Accumulated jitter on 28 cycles(5)	-	-	± 0.15	-	ns
Paired transition jitter PT jitter Accumulated jitter on 56 cycles(5)		-	-	± 0.25	-	ns

Table 46. HSI48 oscillator characteristics

128/357 DS12110 Rev 10

• 1. Guaranteed by test in production.

• 2. Guaranteed by design.

• 3. Guaranteed by characterization.

• 1. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) / Freq(1.62V).

• 5. Jitter measurements are performed without clock source activated in parallel.

64 MHz high-speed internal RC oscillator (HSI)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI	HSI frequency	VDD=3.3 V, TJ=30 °C	63.7(2)	64	64.3(2)	MHz
	TRIM HSI user trimming step	Trimming is not a multiple of 32	-	0.24	0.32
		Trimming is 128, 256 and 384	-5.2	-1.8	-
		Trimming is 64, 192, 320 and 448	-1.4	-0.8	-	%
		Other trimming are a multiple of 32 (not including multiple of 64 and 128)	-0.6	-0.25	-
DuCy(HSI)	Duty Cycle	-	45	-	55	%
ΔVDD (HSI)	HSI oscillator frequency drift over VDD (reference is 3.3 V)	VDD=1.62 to 3.6 V	-0.12	-	0.03	%
ΔTEMP (HSI)	HSI oscillator frequency drift over	TJ=-20 to 105 °C	-1(3)	-	1(3)	%
	temperature (reference is 64 MHz)	TJ=-40 to TJmax °C	-2(3)	-	1(3)
tsu(HSI)	HSI oscillator start-up time	-	-	1.4	2	μs
tstab(HSI)	HSI oscillator stabilization time	at 1% of target frequency	-	4	8	μs
IDD(HSI)	HSI oscillator power consumption	-	-	300	400	μA

		Table 47. HSI oscillator characteristics(1)
--	--	---------------------------------------------

1. Guaranteed by design unless otherwise specified.

2. Guaranteed by test in production.

3. Guaranteed by characterization.

4 MHz low-power internal RC oscillator (CSI)

		Table 48. CSI oscillator characteristics(1)
--	--	---------------------------------------------

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fCSI	CSI frequency	VDD=3.3 V, TJ=30 °C	3.96(2)	4	4.04(2)	MHz
TRIM	Trimming step	-	-	0.35	-	%
DuCy(CSI)	Duty Cycle	-	45	-	55	%

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	CSI oscillator frequency drift over	TJ = 0 to 85 °C	-	-3.7(3)	4.5(3)
∆TEMP (CSI)	temperature	TJ = -40 to 125 °C	-	-11(3)	7.5(3)	%
DVDD (CSI)	CSI oscillator frequency drift over VDD	VDD = 1.62 to 3.6 V	-	-0.06	0.06	%
tsu(CSI)	CSI oscillator startup time	-	-	1	2	μs
tstab(CSI)	CSI oscillator stabilization time (to reach ±3% of fCSI)	-	-	4	8	cycle
IDD(CSI)	CSI oscillator power consumption	-	-	23	30	μA

			Table 48. CSI oscillator characteristics(1) (continued)
--	--	--	---------------------------------------------------------

1. Guaranteed by design.

2. Guaranteed by test in production.

3. Guaranteed by characterization.

Low-speed internal (LSI) RC oscillator

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fLSI(1)		VDD = 3.3 V, TJ = 25 °C	31.4	32	32.6	kHz
	LSI frequency	TJ = –40 to 105 °C, VDD = 1.62 to 3.6 V	29.76	-	33.60
tsu(LSI)(2)	LSI oscillator startup time	-	-	80	130
tstab(LSI)(2)	LSI oscillator stabilization time (5% of final value)	-	-	120	170	μs
IDD(LSI)(2)	LSI oscillator power consumption	-	-	130	280	nA

1. Guaranteed by characterization results.

2. Guaranteed by design.

6.3.10 PLL characteristics

The parameters given in Table 50 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

	Table 50. PLL characteristics (wide VCO frequency range)(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fPLLIN	PLL input clock	-	2	-	16	MHz
	PLL input clock duty cycle	-	10	-	90	%

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
		VOS1		1.5	-	400(2)	MHz
fPLLPOUT	PLL multiplier output clock P	VOS2 VOS3		1.5	- -	300 200
		VOS1		1.5	-	400(2)
fPLLQOUT	PLL multiplier output clock Q/R	VOS2		1.5	-	300
		VOS3		1.5	-	200
fVCOOUT	PLL VCO output	-		192	-	836
tLOCK		Normal mode		-	50(3)	150(3)
	PLL lock time	Sigma-delta mode (CKIN ≥ 8 MHz)		-	58(3)	166(3)	μs
	Cycle-to-cycle jitter(4)	VCO = 192 MHz		-	134	-	±ps
		VCO = 200 MHz		-	134	-
		VCO = 400 MHz		-	76	-
Jitter		VCO = 800 MHz		-	39	-
		Normal mode		-	±0.7	-
	Long term jitter	Sigma-delta mode (CKIN = 16 MHz)		-	±0.8	-	%
IDD(PLL)(3)	PLL power consumption on VDD	VCO freq = 420 MHz	VDDA	-	440	1150	μA
			VCORE	-	530	-
		VCO freq = 150 MHz	VDDA	-	180	500
			VCORE	-	200	-

1. Guaranteed by design unless otherwise specified.

2. This value must be limited to the maximum frequency due to the product limitation (400 MHz for VOS1, 300 MHz for VOS2, 200 MHz for VOS3).

3. Guaranteed by characterization results.

1. Integer mode only.

Table 51. PLL characteristics (medium VCO frequency range)(1)
---------------------------------------------------------------

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	PLL input clock	-	1	-	2	MHz
fPLLIN	PLL input clock duty cycle	-	10	-	90	%
fPLLOUT	PLL multiplier output clock P, Q, R	VOS1	1.17	-	210	MHz
		VOS2	1.17	-	210
		VOS3	1.17	-	200
fVCOOUT	PLL VCO output -		150	-	420	MHz
tLOCK	PLL lock time	Normal mode	-	60(2)	100(2)	μs
		Sigma-delta mode	forbidden	-	-	μs

DS12110 Rev 10 131/357

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
Jitter	Cycle-to-cycle jitter(3)	-	VCO = 150 MHz	-	145	-	+/- ps
			VCO = 300 MHz	-	91	-
			VCO = 400 MHz	-	64	-
			VCO = 420 MHz	-	63	-
	Period jitter	fPLLOUT = 50 MHz	VCO = 150 MHz	-	55	-	+/- ps
			VCO = 400 MHz	-	30	-
	Long term jitter	Normal mode	VCO = 150 MHz	-	-	-
			VCO = 300 MHz	-	-	-	%
			VCO = 400 MHz	-	+/-0.3	-
I(PLL)(2)	PLL power consumption on VDD	VCO freq = 420MHz	VDD	-	440	1150	μA
			VCORE	-	530	-
		VCO freq = 150MHz	VDD	-	180	500
			VCORE	-	200	-

1. Guaranteed by design unless otherwise specified.

2. Guaranteed by characterization results.

1. Integer mode only.

6.3.11 Memory characteristics

Flash memory

The characteristics are given at TJ = –40 to 125 °C unless otherwise specified.

The devices are shipped to customers with the flash memory erased.

		Table 52. Flash memory characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
IDD	Supply current	Write / Erase 8-bit mode	-	6.5	-	mA
		Write / Erase 16-bit mode	-	11.5	-
		Write / Erase 32-bit mode	-	20	-
		Write / Erase 64-bit mode	-	35	-

Symbol	Parameter	Conditions	Min(1)	Typ	Max(1)	Unit
tprog		Program/erase parallelism x 8	-	290	580(2)
	Word (266 bits) programming time	Program/erase parallelism x 16	-	180	360	μs
		Program/erase parallelism x 32	-	130	260
		Program/erase parallelism x 64	-	100	200
		Program/erase parallelism x 8	-	2	4
tERASE128KB	Sector (128 KB) erase time	Program/erase parallelism x 16	-	1.8	3.6
		Program/erase parallelism x 32	-	1.1	2.2
		Program/erase parallelism x 64	-	1	2
tME		Program/erase parallelism x 8	-	13	26	s
		Program/erase parallelism x 16	-	8	16
	Mass erase time	Program/erase parallelism x 32	-	6	12
		Program/erase parallelism x 64 Program parallelism x 8	-	5	10
Vprog	Programming voltage	Program parallelism x 16 Program parallelism x 32	1.62	-	3.6	V
		Program parallelism x 64	1.8	-	3.6

Table 53. Flash memory programming

1. Guaranteed by characterization results.

1. The maximum programming time is measured after 10K erase operations.

Symbol			Value	Unit
	Parameter	Conditions	Min(1)
NEND	Endurance	TJ = –40 to +125 °C (6 suffix versions)	10	kcycles
tRET	Data retention	1 kcycle at TA = 85 °C 10 kcycles at TA = 55 °C	30 20	Years

Table 54. Flash memory endurance and data retention

1. Guaranteed by characterization results.

6.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 55. They are based on the EMS levels and classes defined in application note AN1709.

Symbol	Parameter	Conditions	Level/ Class
VFESD	Voltage limits to be applied on any I/O pin to induce a functional disturbance	VDD = 3.3 V, TA = +25 °C,	3B
VFTB	Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance	UFBGA240, frcccck = 400 MHz, conforms to IEC 61000-4-2	4B

Table 55. EMS characteristics

As a consequence, it is recommended to add a serial resistor (1 kΏ) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

Symbol	Parameter	Conditions	Monitored frequency band	Max vs. [fHSE/fCPU]	Unit
				8/400 MHz
SEMI	Peak (1)	VDD = 3.6 V, TA = 25 °C, UFBGA240 package, compliant with IEC61967-2	0.1 MHz to 30 MHz	6
			30 MHz to 130 MHz 130 MHz to 1 GHz 1 GHz to 2 GHz	5 13 7	dBμV
	Level (2)		0.1 MHz to 2 GHz	2.5	-

Table 56. EMI characteristics for fHSE = 8 MHz and fCPU = 400 MHz

1. Refer to AN1709 "EMI radiated test" chapter.

2. Refer to AN1709 "EMI level classification" chapter.

6.3.13 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards.

Symbol	Ratings	Conditions	Packages	Class	Maximum value(1)	Unit
VESD(HBM)	Electrostatic discharge voltage (human body model)	TA = +25 °C conforming to ANSI/ESDA/JEDEC JS 001	All	1C	1000	V
VESD(CDM)	Electrostatic discharge voltage (charge device model)	TA = +25 °C conforming to ANSI/ESDA/JEDEC JS 002	All	C1	250

Table 57. ESD absolute maximum ratings

1. Guaranteed by characterization results.

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with JESD78 IC latchup standard.

Table 58. Electrical sensitivities

Symbol	Parameter	Conditions	Class
LU	Static latchup class	TA = +25 °C conforming to JESD78	II level A

6.3.14 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during the normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when an abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out

of –5 μA/+0 μA range), or other functional failure (for example reset, oscillator frequency deviation).

The following tables are the compilation of the SIC1/SIC2 and functional ESD results.

Negative induced A negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

Symbol		Functional susceptibility
	Description	Negative injection
IINJ	PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15, PJ12, PB4	5
	PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11	0
	PA0, PAC, PA1, PA1C, PC2, PC2C, PC3, PC3C, PA4, PA5, PH4, PH5, BOOT0	0
	All other I/Os	5

Table 59. I/O current injection susceptibility(1)

1. Guaranteed by characterization.

6.3.15 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 60: I/O static characteristics are derived from tests performed under the conditions summarized in Table 24: General operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).

For information on GPIO configuration, refer to the application note AN4899 "STM32 GPIO configuration for hardware settings and low-power consumption" available from the ST website www.st.com.

</vddiox<3.6> </vddiox<3.6>

Symbol	Parameter	Condition	Min	Typ	Max	Unit
VIL	I/O input low level voltage except BOOT0	1.62 V <vddiox<3.6 td="" v<="">	-	-	0.3VDD(1)		-	-	0.3VDD(1)
	I/O input low level voltage except BOOT0		-	-	0.4VDD- 0.1(2)	V
	BOOT0 I/O input low level voltage		-	-	0.19VDD+ 0.1(2)
VIH	I/O input high level voltage except BOOT0		0.7VDD(1)	-	-
	I/O input high level voltage except BOOT0(3)	1.62 V <vddiox<3.6 td="" v<="">	0.47VDD+ 0.25(2)	-	-	V	0.47VDD+ 0.25(2)	-	-	V
	BOOT0 I/O input high level voltage(3)		0.17VDD+ 0.6(2)	-	-

Table 60. I/O static characteristics

Symbol	Parameter	Condition	Min	Typ	Max	Unit
VHYS(2)	TTxx, FTxxx and NRST I/O input hysteresis	1.62 V< VDDIOx <3.6 V	-	250	-	mV
	BOOT0 I/O input hysteresis		-	200	-
	FTxx Input leakage current(2)	(9) 0< VIN ≤ Max(VDDXXX)	-	-	+/-250	nA
Ilkg(4)		Max(VDDXXX) < VIN ≤ 5.5 V (5)(6)(9)	-	-	1500
	FTu IO	(9) 0< VIN ≤ Max(VDDXXX)	-	-	+/- 350
		Max(VDDXXX) < VIN ≤ 5.5 V (5)(6)(9)	-	-	5000(7)
	TTxx Input leakage current	(9) 0< VIN ≤ Max(VDDXXX)	-	-	+/-250
	VPP (BOOT0 alternate function)	0< VIN ≤ VDDIOX	-	-	15
		VDDIOX < VIN ≤ 9 V	-	-	35
RPU	Weak pull-up equivalent resistor(8)	VIN=VSS	30	40	50	kΩ
RPD	Weak pull-down equivalent resistor(8)	VIN=VDD(9)	30	40	50
CIO	I/O pin capacitance	-	-	5	-	pF

Table 60. I/O static characteristics (continued)

1. Compliant with CMOS requirement.

2. Guaranteed by design.

3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.

1. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula: ITotal_Ikg_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).

5. All FT_xx IO except FT_lu, FT_u and PC3.

6. VIN must be less than Max(VDDXXX) + 3.6 V.

1. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be disabled.

8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).

9. Max(VDDXXX) is the maximum value of all the I/O supplies.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 22.

Figure 22. VIL/VIH for all I/Os except BOOT0

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH).

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular:

• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 22).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating ΣIVSS (see Table 22).

Output voltage levels

Unless otherwise specified, the parameters given in Table 61 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions. All I/Os are CMOS and TTL compliant.

Table 61. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1)

Symbol	Parameter	Conditions(3)	Min	Max	Unit
VOL	Output low level voltage	CMOS port(2) IIO=8 mA 2.7 V≤ VDD ≤3.6 V	-	0.4
VOH	Output high level voltage	CMOS port(2) IIO=-8 mA 2.7 V≤ VDD ≤3.6 V	VDD-0.4	-
VOL(3)	Output low level voltage	TTL port(2) IIO=8 mA 2.7 V≤ VDD ≤3.6 V	-	0.4
VOH(3)	Output high level voltage	TTL port(2) IIO=-8 mA 2.7 V≤ VDD ≤3.6 V	2.4	-
VOL(3)	Output low level voltage	IIO=20 mA 2.7 V≤ VDD ≤3.6 V	-	1.3	V
VOH(3)	Output high level voltage	IIO=-20 mA 2.7 V≤ VDD ≤3.6 V	VDD-1.3	-
VOL(3)	Output low level voltage	IIO=4 mA 1.62 V≤ VDD ≤3.6 V	-	0.4
(3) VOH	Output high level voltage	IIO=-4 mA 1.62 V≤VDD<3.6 V	VDD--0.4	-
VOLFM+(3)	Output low level voltage for an FTf I/O pin in FM+ mode	IIO= 20 mA 2.3 V≤ VDD≤3.6 V	-	0.4
		IIO= 10 mA 1.62 V≤ VDD ≤3.6 V	-	0.4

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Symbol	Parameter	Conditions(3)	Min	Max	Unit
VOL	Output low level voltage	CMOS port(2) IIO=3 mA 2.7 V≤ VDD ≤3.6 V	-	0.4
VOH	Output high level voltage	CMOS port(2) IIO=-3 mA 2.7 V≤ VDD ≤3.6 V	VDD-0.4	-
VOL(3)	Output low level voltage	TTL port(2) IIO=3 mA 2.7 V≤ VDD ≤3.6 V	-	0.4	V
VOH(3)	Output high level voltage	TTL port(2) IIO=-3 mA 2.7 V≤ VDD ≤3.6 V	2.4	-
VOL(3)	Output low level voltage	IIO=1.5 mA 1.62 V≤ VDD ≤3.6 V	-	0.4
VOH(3)	Output high level voltage	IIO=-1.5 mA 1.62 V≤ VDD ≤3.6 V	VDD-0.4	-

Table 62. Output voltage characteristics for PC13, PC14, PC15 and PI8(1)

1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always respect the absolute maximum ratings ΣIIO.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. Guaranteed by design.

Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the product voltage is below 2.5 V.

Speed	Symbol	Parameter	conditions	Min	Max	Unit
	Fmax(3)		C=50 pF, 2.7 V≤ VDD≤3.6 V C=50 pF, 1.62 V≤VDD≤2.7 V	- -	12 3
			C=30 pF, 2.7 V≤VDD≤3.6 V	-	12	MHz
		Maximum frequency	C=30 pF, 1.62 V≤VDD≤2.7 V C=10 pF, 2.7 V≤VDD≤3.6 V C=10 pF, 1.62 V≤VDD≤2.7 V	- - -	3 16 4
00		Output high to low level fall time and output low to high level rise time	C=50 pF, 2.7 V≤ VDD≤3.6 V C=50 pF, 1.62 V≤VDD≤2.7 V	- -	16.6 33.3
	(4)		C=30 pF, 2.7 V≤VDD≤3.6 V	-	13.3	ns
01	tr/tf		C=30 pF, 1.62 V≤VDD≤2.7 V C=10 pF, 2.7 V≤VDD≤3.6 V C=10 pF, 1.62 V≤VDD≤2.7 V	- - -	25 10 20
	Fmax(3)	Maximum frequency	C=50 pF, 2.7 V≤ VDD≤3.6 V C=50 pF, 1.62 V≤VDD≤2.7 V C=30 pF, 2.7 V≤VDD≤3.6 V C=30 pF, 1.62 V≤VDD≤2.7 V C=10 pF, 2.7 V≤VDD≤3.6 V C=10 pF, 1.62 V≤VDD≤2.7 V	- - - - - -	60 15 80 15 110 20	MHz
	(4) tr/tf	Output high to low level fall time and output low to high level rise time	C=50 pF, 2.7 V≤ VDD≤3.6 V C=50 pF, 1.62 V≤VDD≤2.7 V C=30 pF, 2.7 V≤VDD≤3.6 V C=30 pF, 1.62 V≤VDD≤2.7 V C=10 pF, 2.7 V≤VDD≤3.6 V C=10 pF, 1.62 V≤VDD≤2.7 V	- - - - - -	5.2 10 4.2 7.5 2.8 5.2	ns

Table 63. Output timing characteristics (HSLV OFF)(1)(2)

Speed	Symbol	Parameter	conditions	Min	Max	Unit
	Fmax(3)	Maximum frequency	C=50 pF, 2.7 V≤VDD≤3.6 V(5) C=50 pF, 1.62 V≤VDD≤2.7 V(5) C=30 pF, 2.7 V≤VDD≤3.6 V(5) C=30 pF, 1.62 V≤VDD≤2.7 V(5) C=10 pF, 2.7 V≤VDD≤3.6 V(5) C=10 pF, 1.62 V≤VDD≤2.7 V(5)	- - - - - -	85 35 110 40 166 85	MHz
10			C=50 pF, 2.7 V≤VDD≤3.6 V(5)	-	3.8
		Output high to low level fall time and output low to high level rise time	C=50 pF, 1.62 V≤VDD≤2.7 V(5)	-	6.9
	(4)		C=30 pF, 2.7 V≤VDD≤3.6 V(5)	-	2.8	ns
11	tr/tf		C=30 pF, 1.62 V≤VDD≤2.7 V(5) C=10 pF, 2.7 V≤VDD≤3.6 V(5) C=10 pF, 1.62 V≤VDD≤2.7 V(5)	- - -	5.2 1.8 3.3
	Fmax(3)	Maximum frequency	C=50 pF, 2.7 V≤VDD≤3.6 V(5) C=50 pF, 1.62 V≤VDD≤2.7 V(5) C=30 pF, 2.7 V≤VDD≤3.6 V(5) C=30 pF, 1.62 V≤VDD≤2.7 V(5) C=10 pF, 2.7 V≤VDD≤3.6 V(5) C=10 pF, 1.62 V≤VDD≤2.7 V(5)	- - - - - -	100 50 133 66 220 100	MHz
	(4) tr/tf	Output high to low level fall time and output low to high level rise time	C=50 pF, 2.7 V≤VDD≤3.6 V(5) C=50 pF, 1.62 V≤VDD≤2.7 V(5) C=30 pF, 2.7 V≤VDD≤3.6 V(5) C=30 pF, 1.62 V≤VDD≤2.7 V(5) C=10 pF, 2.7 V≤VDD≤3.6 V(5) C=10 pF, 1.62 V≤VDD≤2.7 V(5) Table 63. Output timing characteristics (HSLV OFF)(1)(2) (continued)	- - - - - -	3.3 6.6 2.4 4.5 1.5 2.7	ns
--	--	--	----------------------------------------------------------------------	--	--	--
--	--	--	----------------------------------------------------------------------	--	--	--

1. Guaranteed by design.

2. The frequency of the GPIOs that can be supplied in VBAT mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz

3. The maximum frequency is defined with the following conditions: (tr+tf ) ≤ 2/3 T Skew ≤ 1/20 T

45%<Duty cycle<55%

4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.

5. Compensation system enabled.

Output buffer timing characteristics (HSLV option enabled)

Speed	Symbol	Parameter	conditions	Min	Max	Unit
00			C=50 pF, 1.62 V≤VDD≤2.7 V	-	10
	Fmax(2)	Maximum frequency	C=30 pF, 1.62 V≤VDD≤2.7 V C=10 pF, 1.62 V≤VDD≤2.7 V	- -	10 10	MHz
		Output high to low level (3) fall time and output low	C=50 pF, 1.62 V≤VDD≤2.7 V	-	11
	tr/tf		C=30 pF, 1.62 V≤VDD≤2.7 V	-	9	ns
		to high level rise time	C=10 pF, 1.62 V≤VDD≤2.7 V	-	6.6
		Maximum frequency	C=50 pF, 1.62 V≤VDD≤2.7 V	-	50
	Fmax(2)		C=30 pF, 1.62 V≤VDD≤2.7 V C=10 pF, 1.62 V≤VDD≤2.7 V	- -	58 66	MHz
01	(3) tr/tf	Output high to low level fall time and output low to high level rise time	C=50 pF, 1.62 V≤VDD≤2.7 V C=30 pF, 1.62 V≤VDD≤2.7 V C=10 pF, 1.62 V≤VDD≤2.7 V	- - -	6.6 4.8 3	ns
10	Fmax(2)	Maximum frequency	C=50 pF, 1.62 V≤VDD≤2.7 V(4) (4) C=30 pF, 1.62 V≤VDD≤2.7 V C=10 pF, 1.62 V≤VDD≤2.7 V(4)	- - -	55 80 133	MHz
	(3) tr/tf			Output high to low level	C=50 pF, 1.62 V≤VDD≤2.7 V(4)	-
		fall time and output low	(4) C=30 pF, 1.62 V≤VDD≤2.7 V	-	4	ns
		to high level rise time	C=10 pF, 1.62 V≤VDD≤2.7 V(4)	-	2.4
11	Fmax(2)	Maximum frequency	C=50 pF, 1.62 V≤VDD≤2.7 V(4)	-	60
			(4) C=30 pF, 1.62 V≤VDD≤2.7 V C=10 pF, 1.62 V≤VDD≤2.7 V(4)	- -	90 175	MHz
	(3) tr/tf	Output high to low level fall time and output low	C=50 pF, 1.62 V≤VDD≤2.7 V(4)	-	5.3
			(4) C=30 pF, 1.62 V≤VDD≤2.7 V	-	3.6	ns
		to high level rise time	C=10 pF, 1.62 V≤VDD≤2.7 V(4)	-	1.9

Table 64. Output timing characteristics (HSLV ON)(1)

1. Guaranteed by design.

2. The maximum frequency is defined with the following conditions: (tr+tf ) ≤ 2/3 T Skew ≤ 1/20 T

45%<Duty cycle<55%

3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.

4. Compensation system enabled.

6.3.16 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 60: I/O static characteristics).

Unless otherwise specified, the parameters given in Table 65 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
RPU(2)	Weak pull-up equivalent resistor(1)	VIN = VSS	30	40	50	㏀
VF(NRST)(2)	NRST Input filtered pulse	1.71 V < VDD < 3.6 V	-	-	50
VNF(NRST)(2)	NRST Input not filtered pulse	1.71 V < VDD < 3.6 V	300	-	-	ns
		1.62 V < VDD < 3.6 V	1000	-	-

1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order).

2. Guaranteed by design.

Figure 23. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 60. Otherwise the reset is not taken into account by the device.

6.3.17 FMC characteristics

Unless otherwise specified, the parameters given in Table 66 to Table 79 for the FMC interface are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

Asynchronous waveforms and timings

Figure 24 through Figure 27 represent asynchronous waveforms and Table 66 through Table 73 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capcitive load CL = 30 pF

In all timing tables, the TKERCK is the fmc_ker_ck clock period.

Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	2Tfmckerck - 1	2 Tfmckerck +1
tv(NOENE)	FMCNEx low to FMCNOE low	0	0.5
tw(NOE)	FMCNOE low time	2Tfmckerck - 1	2Tfmckerck + 1
th(NENOE)	FMCNOE high to FMCNE high hold time	0	-
tv(ANE)	FMCNEx low to FMCA valid	-	0.5
th(ANOE)	Address hold time after FMCNOE high	0	-
tv(BLNE)	FMCNEx low to FMCBL valid	-	0.5
th(BLNOE)	FMCBL hold time after FMCNOE high	0	-	ns
tsu(DataNE)	Data to FMCNEx high setup time	11	-
tsu(DataNOE)	Data to FMCNOEx high setup time	11	-
th(DataNOE)	Data hold time after FMCNOE high		-
th(DataNE)	Data hold time after FMCNEx high	0	-
tv(NADVNE)	FMCNEx low to FMCNADV low	-	0
tw(NADV)	FMCNADV low time	-	Tfmckerck + 1

1. Guaranteed by characterization results.

	Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1)(2)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	7Tfmckerck +1	7Tfmckerck +1
tw(NOE)	FMCNWE low time	5Tfmckerck -1	5Tfmckerck +1	ns
tw(NWAIT)	FMCNWAIT low time	Tfmckerck -0.5
tsu(NWAITNE)	FMCNWAIT valid before FMCNEx high	4Tfmckerck +11	-
th(NENWAIT)	FMCNEx hold time after FMCNWAIT invalid	3Tfmckerck+11.5	-

1. NWAIT pulse width is equal to 1 AHB cycle.

Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
------------------------------------------------------------------------

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	3Tfmckerck - 1	3Tfmckerck
tv(NWENE)	FMCNEx low to FMCNWE low	Tfmckerck	Tfmckerck + 1
tw(NWE)	FMCNWE low time	Tfmckerck - 0.5	Tfmckerck + 0.5
th(NENWE)	FMCNWE high to FMCNE high hold time	Tfmckerck	-
tv(ANE)	FMCNEx low to FMCA valid	-	2
th(ANWE)	Address hold time after FMCNWE high	Tfmckerck - 0.5	-
tv(BLNE)	FMCNEx low to FMCBL valid	-	0.5	ns
th(BLNWE)	FMCBL hold time after FMCNWE high		-
tv(DataNE)	Data to FMCNEx low to Data valid		Tfmckerck + 2.5
th(DataNWE)	Data hold time after FMCNWE high Tfmckerck+0.5 -
tv(NADVNE)	FMCNEx low to FMCNADV low - 0
tw(NADV)	FMCNADV low time	- Tfmckerck + 1

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	8Tfmckerck - 1	8Tfmckerck + 1
tw(NWE)	FMCNWE low time	6Tfmckerck - 1.5	6Tfmckerck + 0.5	ns
tsu(NWAITNE)	FMCNWAIT valid before FMCNEx high 5Tfmckerck + 13 -
th(NENWAIT)	FMCNEx hold time after FMCNWAIT invalid Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2)	4Tfmckerck+ 13	-
--	-----------------------------------------------------------------------------------	--

1. NWAIT pulse width is equal to 1 AHB cycle.

Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	3Tfmckerck - 1	3Tfmckerck + 1
tv(NOENE)	FMCNEx low to FMCNOE low	2Tfmckerck	2Tfmckerck + 0.5
ttw(NOE)	FMCNOE low time	Tfmckerck - 1	Tfmckerck + 1
th(NENOE)	FMCNOE high to FMCNE high hold time	0	-
tv(ANE)	FMCNEx low to FMCA valid	-	0.5
tv(NADVNE)	FMCNEx low to FMCNADV low	0	0.5
tw(NADV)	FMCNADV low time	Tfmckerck - 0.5	Tfmckerck+1
th(ADNADV)	FMCAD(address) valid hold time after FMCNADV high	Tfmckerck + 0.5	-	ns
th(ANOE)	Address hold time after FMCNOE high	Tfmckerck - 0.5	-
th(BLNOE)	FMCBL time after FMCNOE high	0	-
tv(BLNE)	FMCNEx low to FMCBL valid	-	0.5
tsu(DataNE)	Data to FMCNEx high setup time	Tfmckerck - 2	-
tsu(DataNOE)	Data to FMCNOE high setup time	Tfmckerck - 2	-
th(DataNE)	Data hold time after FMCNEx high	0	-
th(DataNOE)	Data hold time after FMCNOE high	0	-

1. Guaranteed by characterization results.

Table 71. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	8Tfmckerck - 1	8Tfmckerck
tw(NOE)	FMCNWE low time	5Tfmckerck - 1.5	5Tfmckerck + 0.5	ns
tsu(NWAITNE)	FMCNWAIT valid before FMCNEx high	5Tfmckerck + 3	-
th(NENWAIT)	FMCNEx hold time after FMCNWAIT invalid	4Tfmckerck	-

Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms

Table 72. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	4Tfmckerc - 1	4Tfmckerck
tv(NWENE)	FMCNEx low to FMCNWE low	Tfmckerc - 1	Tfmckerck + 0.5
tw(NWE)	FMCNWE low time	2Tfmckerck- 0.5	2Tfmckerck+ 0.5
th(NENWE)	FMCNWE high to FMCNE high hold time	Tfmckerck - 0.5	-
tv(ANE)	FMCNEx low to FMCA valid	-	0
tv(NADVNE)	FMCNEx low to FMCNADV low	0	0.5
tw(NADV)	FMCNADV low time	Tfmckerck	Tfmckerck+ 1	ns
th(ADNADV)	FMCAD(address) valid hold time after FMCNADV high	Tfmckerck+0.5	-
th(ANWE)	Address hold time after FMCNWE high	Tfmckerck+0.5	-
th(BLNWE)	FMCBL hold time after FMCNWE high	Tfmckerck - 0.5	-
tv(BLNE)	FMCNEx low to FMCBL valid	-	0.5
tv(DataNADV)	FMCNADV high to Data valid	-	Tfmckerck + 2
th(DataNWE)	Data hold time after FMCNWE high	Tfmckerck+0.5	-

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	9Tfmckerck – 1	9Tfmckerck
t w(NWE)	FMCNWE low time	7Tfmckerck – 0.5	7Tfmckerck + 0.5	ns
tsu(NWAITNE)	FMCNWAIT valid before FMCNEx high	6Tfmckerck + 3	-
th(NENWAIT)	FMCNEx hold time after FMCNWAIT invalid	4Tfmckerck	-

1. Guaranteed by characterization results.

Synchronous waveforms and timings

Figure 28 through Figure 31 represent synchronous waveforms and Table 74 through Table 77 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM

In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK maximum values:

• For 2.7 V<VDD<3.6 V, FMC_CLK =100 MHz at 20 pF
• For 1.8 V<VDD<1.9 V, FMC_CLK =100 MHz at 20 pF
• For 1.62 V<VDD<1.8 V, FMC_CLK =100 MHz at 15 pF

Figure 28. Synchronous multiplexed NOR/PSRAM read timings

Symbol	Parameter	Min	Max	Unit
tw(CLK)	FMCCLK period	2Tfmckerck - 1	-
td(CLKL-NExL)	FMCCLK low to FMCNEx low (x=02)	-	1
td(CLKHNExH)	FMCCLK high to FMCNEx high (x= 0…2)	Tfmckerck + 0.5	-
td(CLKL-NADVL)	FMCCLK low to FMCNADV low	-	1.
td(CLKL-NADVH)	FMCCLK low to FMCNADV high	0	-
td(CLKL-AV)	FMCCLK low to FMCAx valid (x=16…25)	-	2.5
td(CLKH-AIV)	FMCCLK high to FMCAx invalid (x=16…25)	Tfmckerck	-
td(CLKL-NOEL)	FMCCLK low to FMCNOE low	-	1.5	ns
td(CLKH-NOEH)	FMCCLK high to FMCNOE high	Tfmckerck - 0.5	-
td(CLKL-ADV)	FMCCLK low to FMCAD[15:0] valid	-	3
td(CLKL-ADIV)	FMCCLK low to FMCAD[15:0] invalid	0	-
tsu(ADV-CLKH)	FMCA/D[15:0] valid data before FMCCLK high	3	-
th(CLKH-ADV)	FMCA/D[15:0] valid data after FMCCLK high	0	-
tsu(NWAIT-CLKH)	FMCNWAIT valid before FMCCLK high	3	-
th(CLKH-NWAIT)	FMCNWAIT valid after FMCCLK high	1	-

1. Guaranteed by characterization results.

Figure 29. Synchronous multiplexed PSRAM write timings

Symbol	Parameter	Min	Max	Unit
tw(CLK)	FMCCLK period	2Tfmckerck - 1	-
td(CLKL-NExL)	FMCCLK low to FMCNEx low (x=02)	-	1
td(CLKH-NExH)	FMCCLK high to FMCNEx high (x= 0…2)	Tfmckerck + 0.5	-
td(CLKL-NADVL)	FMCCLK low to FMCNADV low	-	1.5
td(CLKL-NADVH)	FMCCLK low to FMCNADV high	0	-
td(CLKL-AV)	FMCCLK low to FMCAx valid (x=16…25)	-	2
td(CLKH-AIV)	FMCCLK high to FMCAx invalid (x=16…25)	Tfmckerck	-
td(CLKL-NWEL)	FMCCLK low to FMCNWE low	-	1.5
t(CLKH-NWEH)	FMCCLK high to FMCNWE high	Tfmckerck + 0.5	-	ns
td(CLKL-ADV)	FMCCLK low to FMCAD[15:0] valid	-	2.5
td(CLKL-ADIV)	FMCCLK low to FMCAD[15:0] invalid	0	-
td(CLKL-DATA)	FMCA/D[15:0] valid data after FMCCLK low	-	2.5
td(CLKL-NBLL)	FMCCLK low to FMCNBL low	-	2
td(CLKH-NBLH)	FMCCLK high to FMCNBL high	Tfmckerck + 0.5	-
tsu(NWAIT-CLKH)	FMCNWAIT valid before FMCCLK high	2	-
th(CLKH-NWAIT)	FMCNWAIT valid after FMCCLK high	2	-
Table 75. Synchronous multiplexed PSRAM write timings(1)
----------------------------------------------------------
----------------------------------------------------------

1. Guaranteed by characterization results.

Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings

Symbol	Parameter	Min	Max	Unit
tw(CLK)	FMCCLK period	2Tfmckerck - 1	-
t(CLKL-NExL)	FMCCLK low to FMCNEx low (x=02)	-	2
td(CLKH-NExH)	FMCCLK high to FMCNEx high (x= 0…2)	Tfmckerck + 0.5	-
td(CLKL-NADVL)	FMCCLK low to FMCNADV low	-	0.5
td(CLKL-NADVH)	FMCCLK low to FMCNADV high	0	-
td(CLKL-AV)	FMCCLK low to FMCAx valid (x=16…25)	-	2
td(CLKH-AIV)	FMCCLK high to FMCAx invalid (x=16…25)	Tfmckerck	-	ns
td(CLKL-NOEL)	FMCCLK low to FMCNOE low	-	1.5
td(CLKH-NOEH)	FMCCLK high to FMCNOE high	Tfmckerck + 0.5	-
tsu(DV-CLKH)	FMCD[15:0] valid data before FMCCLK high	3	-
th(CLKH-DV)	FMCD[15:0] valid data after FMCCLK high	0	-
tSU(NWAIT-CLKH)	FMCNWAIT valid before FMCCLK high	3	-
th(CLKH-NWAIT)	FMCNWAIT valid after FMCCLK high	1	-

Table 77. Synchronous non-multiplexed PSRAM write timings(1)
--------------------------------------------------------------

Symbol	Parameter	Min	Max	Unit
t(CLK)	FMCCLK period	2Tfmckerck - 1	-
td(CLKL-NExL)	FMCCLK low to FMCNEx low (x=02)	-	2
t(CLKH-NExH)	FMCCLK high to FMCNEx high (x= 0…2)	Tfmckerck + 0.5	-
td(CLKL-NADVL)	FMCCLK low to FMCNADV low	-	0.5
td(CLKL-NADVH)	FMCCLK low to FMCNADV high	0	-
td(CLKL-AV)	FMCCLK low to FMCAx valid (x=16…25)	-	2
td(CLKH-AIV)	FMCCLK high to FMCAx invalid (x=16…25)	Tfmckerck	-
td(CLKL-NWEL)	FMCCLK low to FMCNWE low	-	1.5	ns
td(CLKH-NWEH)	FMCCLK high to FMCNWE high	Tfmckerck + 1	-
td(CLKL-Data)	FMCD[15:0] valid data after FMCCLK low	-	3.5
td(CLKL-NBLL)	FMCCLK low to FMCNBL low	-	2
td(CLKH-NBLH)	FMCCLK high to FMCNBL high	Tfmckerck + 1	-
tsu(NWAIT-CLKH)	FMCNWAIT valid before FMCCLK high	2	-
th(CLKH-NWAIT)	FMCNWAIT valid after FMCCLK high	2	-

NAND controller waveforms and timings

Figure 32 through Figure 35 represent synchronous waveforms, and Table 78 and Table 79 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration:

• COM.FMC_SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC_HoldSetupTime = 0x02
• COM.FMC_HiZSetupTime = 0x01
• ATT.FMC_SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth₁6b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize₅12Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
• CL = 30 pF

In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.

Figure 32. NAND controller waveforms for read access

Figure 33. NAND controller waveforms for write access

Figure 34. NAND controller waveforms for common memory read access

Figure 35. NAND controller waveforms for common memory write access

	Table 78. Switching characteristics for NAND flash read cycles(1)

Symbol	Parameter	Min	Max	Unit
tw(N0E)	FMCNOE low width	4Tfmckerck –0.5	4Tfmckerck + 0.5
tsu(D-NOE)	FMCD[15-0] valid data before FMCNOE high	8	-
th(NOE-D)	FMCD[15-0] valid data after FMCNOE high	0	-	ns
td(ALE-NOE)	FMCALE valid before FMCNOE low	-	3Tfmckerck + 1
th(NOE-ALE)	FMCNWE high to FMCALE invalid	4Tfmckerck - 2	-

Table 79. Switching characteristics for NAND flash write cycles(1)

Symbol	Parameter	Min	Max	Unit
tw(NWE)	FMCNWE low width	4Tfmckerck - 0.5	4Tfmckerck + 0.5
tv(NWE-D)	FMCNWE low to FMCD[15-0] valid	0	-
th(NWE-D)	FMCNWE high to FMCD[15-0] invalid	2Tfmckerck - 0.5	-	ns
td(D-NWE)	FMCD[15-0] valid before FMCNWE high	5Tfmckerck - 1	-
td(ALE-NWE)	FMCALE valid before FMCNWE low	-	3Tfmckerck + 0.5
th(NWE-ALE)	FMCNWE high to FMCALE invalid	2Tfmckerck - 1	-

SDRAM waveforms and timings

In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values:

• For 1.8 V < VDD < 3.6V: FMC_SDCLK = 100 MHz at 20 pF
• For 1.62 V< VDD < 1.8 V, FMC_SDCLK = 100 MHz at 15 pF

Table 80. SDRAM read timings(1)

Symbol	Parameter	Min	Max	Unit
tw(SDCLK)	FMCSDCLK period	2Tfmckerck - 1	2Tfmckerck + 0.5
tsu(SDCLKH Data)	Data input setup time	3	-
th(SDCLKHData)	Data input hold time	0	-
td(SDCLKLAdd)	Address valid time	-	1.5
td(SDCLKL- SDNE)	Chip select valid time	-	1.5	ns
th(SDCLKLSDNE)	Chip select hold time	0.5	-
td(SDCLKLSDNRAS)	SDNRAS valid time	-	1
th(SDCLKLSDNRAS)	SDNRAS hold time	0.5	-
td(SDCLKLSDNCAS)	SDNCAS valid time	-	0.5
th(SDCLKLSDNCAS)	SDNCAS hold time	0	-

Symbol	Parameter	Min	Max	Unit
tW(SDCLK)	FMCSDCLK period	2Tfmckerck - 1	2Tfmckerck + 0.5
tsu(SDCLKHData)	Data input setup time	3	-
th(SDCLKHData)	Data input hold time	0.5	-
td(SDCLKLAdd)	Address valid time	-	2.5
td(SDCLKLSDNE)	Chip select valid time	-	2.5	ns
th(SDCLKLSDNE)	Chip select hold time	0	-
td(SDCLKLSDNRAS	SDNRAS valid time	-	0.5
th(SDCLKLSDNRAS)	SDNRAS hold time	0	-
td(SDCLKLSDNCAS)	SDNCAS valid time	-	1.5
th(SDCLKLSDNCAS)	SDNCAS hold time	0	-

Table 81. LPSDR SDRAM read timings(1)

1. Guaranteed by characterization results.

164/357 DS12110 Rev 10

Symbol	Parameter	Min	Max	Unit
tw(SDCLK)	FMCSDCLK period	2Tfmckerck - 1	2Tfmckerck + 0.5
td(SDCLKL Data)	Data output valid time	-	3
th(SDCLKL Data)	Data output hold time	0	-
td(SDCLKLAdd)	Address valid time	-	1.5
td(SDCLKLSDNWE)	SDNWE valid time	-	1.5
th(SDCLKLSDNWE)	SDNWE hold time	0.5	-	ns
td(SDCLKL_ SDNE)	Chip select valid time	-	1.5
th(SDCLKL-SDNE)	Chip select hold time	0.5	-
td(SDCLKLSDNRAS)	SDNRAS valid time	-	1
th(SDCLKLSDNRAS)	SDNRAS hold time	0.5	-
td(SDCLKLSDNCAS)	SDNCAS valid time	-	1
td(SDCLKLSDNCAS)	SDNCAS hold time	0.5	-

Table 82. SDRAM write timings(1)

1. Guaranteed by characterization results.

Symbol	Parameter	Min	Max	Unit
tw(SDCLK)	FMCSDCLK period		2Tfmckerck + 0.5
td(SDCLKL Data)	Data output valid time	-	2.5
th(SDCLKL Data)	Data output hold time	0	-
td(SDCLKLAdd)	Address valid time	-	2.5
td(SDCLKL-SDNWE)	SDNWE valid time	-	2.5
th(SDCLKL-SDNWE)	SDNWE hold time	0	-	ns
td(SDCLKL- SDNE)	Chip select valid time	-	3
th(SDCLKL- SDNE)	Chip select hold time	0	-
td(SDCLKL-SDNRAS)	SDNRAS valid time	-	1.5
th(SDCLKL-SDNRAS)	SDNRAS hold time	0	-
td(SDCLKL-SDNCAS)	SDNCAS valid time	-	1.5
td(SDCLKL-SDNCAS)	SDNCAS hold time	0	-

Table 83. LPSDR SDRAM write timings(1)

1. Guaranteed by characterization results.

6.3.18 Quad-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 84 and Table 85 for QUADSPI are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5VDD
• I/O compensation cell enabled
• HSLV activated when VDD≤2.7 V

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	QUADSPI clock frequency	2.7 V ≤ VDD<3.6 V CL=20 pF	-	-	133
Fck1/TCK		1.62 V <vdd<3.6 v<br="">CL=15 pF</vdd<3.6>	-	-	100	MHz
tw(CKH)	QUADSPI clock high and low	-	TCK/2–0.5	-	TCK/2
tw(CKL)	time		TCK/2	-	TCK/2 + 0.5
	Data input setup time	2.7 V ≤ VDD < 3.6 V	2	-	-
ts(IN)		1.62 V ≤ VDD < 3.6 V	2.5	-	-	ns
th(IN)		2.7 V ≤ VDD < 3.6 V	1	-	-
	Data input hold time	1.62 V ≤ VDD < 3.6 V	1.5	-	-
tv(OUT)	Data output valid time	-	-	1.5	2
th(OUT)	Data output hold time	-	0.5	-	-

Table 84. QUADSPI characteristics in SDR mode(1)

1. Guaranteed by characterization results.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Fck1/t(CK)	QUADSPI clock frequency	2.7 V <vdd<3.6 v<br="">CL=20 pF</vdd<3.6>	-	-	100
		1.62 V <vdd<3.6 v<br="">CL=15 pF</vdd<3.6>	-	-	100	MHz
tw(CKH)	QUADSPI clock high and	-	TCK/2 –0.5	-	TCK/2
tw(CKL)	low time		TCK/2	-	TCK/2+0.5
tsr(IN), tsf(IN)	Data input setup time	2.7 V ≤ VDD < 3.6 V	3	-	-
		1.62 V ≤ VDD < 3.6 V	1	-	-
thr(IN), thf(IN)	Data input hold time	2.7 V ≤ VDD < 3.6 V	1	-	-
		1.62 V ≤ VDD < 3.6 V	1.5	-	-	ns
tvr(OUT), tvf(OUT)		DHHC=0	-	3.5	4
	Data output valid time	DHHC=1 Pres=1, 2	-	TCK/4+3.5	TCK/4+4
thr(OUT), thf(OUT)		DHHC=0	3	-	-
	Data output hold time	DHHC=1 Pres=1, 2	TCK/4+3 Table 85. QUADSPI characteristics in DDR mode(1)	-	-
--	--	--	--------------------------------------------------	--	--
--	--	--	--------------------------------------------------	--	--

1. Guaranteed by characterization results.

6.3.19 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 87 for the delay block are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage summarized in Table 24: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tinit	Initial delay	-	1400	2200	2400
t∆	Unit Delay	-	35	40	45	ps

1. Guaranteed by characterization results.

6.3.20 16-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 87 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 24: General operating conditions.

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
VDDA	Analog power supply	-		1.62	-	3.6
	Positive reference voltage	VDDA	≥ 2 V	2	-	VDDA	V
VREF+		VDDA< 2 V			VDDA
VREF-	Negative reference voltage	-		VSSA
	ADC clock frequency		BOOST = 1	-	-	36	MHz
fADC		2 V ≤ VDDA ≤ 3.3 V	BOOST = 0	-	-	20
		16-bit resolution		-	-	3.60(2)
	Sampling rate for Fast	14-bit resolution		-	-	4.00(2)
fS	channels, BOOST = 1, fADC = 36 MHz(2)	12-bit resolution		-	-	4.50(2)	MSPS
		10-bit resolution		-	-	5.00(2)
		8-bit resolution		-	-	6.00(2)
	Sampling rate for Fast channels, BOOST = 0, fADC = 20 MHz	16-bit resolution		-	-	2.00(2)
		14-bit resolution		-	-	2.20(2)
		12-bit resolution		-	-	2.50(2)
		10-bit resolution		-	-	2.80(2)
		8-bit resolution		-	-	3.30(2)
		16-bit resolution		-	-	1.00
	Sampling rate for Slow channels, BOOST = 0, fADC = 10 MHz	14-bit resolution		-	-	1.00
		12-bit resolution		-	-	1.00
		10-bit resolution		-	-	1.00
		8-bit resolution		-	-	1.00

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fTRIG	External trigger frequency	fADC = 36 MHz	-	-	3.6	MHz
		16-bit resolution	-	-	10	1/fADC
VAIN(3)	Conversion voltage range	-	0 - VREF+
VCMIV	Common mode input voltage	-	VREF/2- 10%	VREF/2	VREF/2+ 10%	V
RAIN	External input impedance	-	-	-	50	㏀
CADC	Internal sample and hold capacitor	-	- 4 -		pF
tADCREG_ STUP	ADC LDO startup time	-	- 5 10			μs
tSTAB	ADC power-up time	LDO already started	1			conversion cycle
tCAL	Offset and linearity calibration time	-	165,010
tOFFCAL	Offset calibration time	-	1,280
	Trigger conversion latency for regular and injected	CKMODE = 00	1.5	2	2.5
		CKMODE = 01	-	-	2
tLATR	channels without aborting	CKMODE = 10			2.25
	the conversion	CKMODE = 11			2.125	1/fADC
	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 00	2.5	3	3.5
		CKMODE = 01	-	-	3
tLATRINJ		CKMODE = 10	-	-	3.25
		CKMODE = 11	-	-	3.125
tS	Sampling time	-	1.5	-	810.5
tCONV	Total conversion time (including sampling time)	N-bit resolution	tS + 0.5 + N/2 (9 to 648 cycles in 14-bit mode)
Table 87. ADC characteristics(1) (continued)
----------------------------------------------	--	--
----------------------------------------------	--	--

1. Guaranteed by design.

2. These values are obtained using the following formula: fS = fADC/ tCONV , where fADC = 36 MHz and tCONV = 1,5 cycle sampling time + tSAR sampling time. Refer to the product reference manual for the value of tSAR depending on resolution.

1. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA.

		Table 88. ADC accuracy(1)(2)(3)
--	--	---------------------------------

Symbol	Parameter		Conditions(4)	Min	Typ	Max	Unit
ET	Total unadjusted error	Single ended	BOOST = 1	-	±6	-
			BOOST = 0	-	±8	-
			BOOST = 1	-	±10	-
		Differential	BOOST = 0	-	±16	-
	Differential	Single	BOOST = 1	-	2	-
		ended	BOOST = 0	-	1	-
ED	linearity error		BOOST = 1	-	8	-
		Differential	BOOST = 0	-	2	-
		Single	BOOST = 1	-	±6	-
	Integral	ended	BOOST = 0	-	±4	-
EL	linearity error		BOOST = 1	-	±6	-
		Differential	BOOST = 0	-	±4	-
	Effective number of bits (2 MSPS)	Single ended	BOOST = 1	-	11.6	-	bits
ENOB(5)			BOOST = 0	-	12	-
			BOOST = 1	-	13.3	-
		Differential	BOOST = 0	-	13.5	-
	Signal-to noise and distortion	Single	BOOST = 1	-	71.6	-
SINAD(5)		ended	BOOST = 0	-	74	-
	ratio		BOOST = 1	-	81.83	±LSB - - - - dB - - - - - -
	(2 MSPS)	Differential	BOOST = 0	-	83
	Signal-to noise ratio (2 MSPS)		Single	BOOST = 1	-	72
SNR(5)		ended	BOOST = 0 BOOST = 1	- -	74 82
		Differential	BOOST = 0	-	83
	Total	Single	BOOST = 1	-	-78
THD(5)		ended	BOOST = 0	-	-80
	harmonic distortion		BOOST = 1	-	-90
			Differential	BOOST = 0	-	-95

1. ADC DC accuracy values are measured after internal calibration.

2. The above table gives the ADC performance in 16-bit mode.

3. ADC clock frequency ≤ 36 MHz, 2 V ≤ VDDA ≤3.3 V, 1.6 V ≤ VREF ≤ VDDA, BOOSTEN (for I/O) = 1.

5. ENOB, SINAD, SNR and THD are specified for VDDA = VREF = 3.3 V.

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion

170/357 DS12110 Rev 10

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC accuracy.

Figure 41. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function

• 1. Refer to Section 6.3.20: 16-bit ADC characteristics for the values of RAIN and CADC.
• 1. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 60: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced.
• 1. Refer to Table 60: I/O static characteristics for the value of Ilkg.
• 1. Refer to Figure 15: Power supply scheme.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 42 or Figure 43, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA)

1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.

1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.

6.3.21 DAC electrical characteristics

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
VDDA	Analog supply voltage	-		1.8	3.3	3.6
VREF+	Positive reference voltage	-		1.80	-	VDDA	V
VREF	Negative reference voltage	-		-	VSSA	-
RL	Resistive Load	DAC output	connected to VSSA	5	-	-	㏀
		buffer ON	connected to VDDA	25	-	-
(2) RO	Output Impedance		DAC output buffer OFF	10.3	13	16
	Output impedance sample		VDD = 2.7 V	-	-	1.6	㏀
RBON	and hold mode, output buffer ON	DAC output buffer ON	VDD = 2.0 V	-	-	2.6
RBOFF	Output impedance sample and hold mode, output buffer OFF	DAC output buffer OFF	VDD = 2.7 V	-	-	17.8	㏀
			VDD = 2.0 V	-	-	18.7
(2) CL			DAC output buffer OFF	-	-	50	pF
CSH(2)	Capacitive Load		Sample and Hold mode	-	0.1	1	μF
VDACOUT	Voltage on DACOUT output		DAC output buffer ON	0.2	-	VREF+ -0.2	V
		DAC output buffer OFF		0	-	VREF+
tSETTLING	Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DACOUT reaches the final value of ±0.5LSB, ±1LSB, ±2LSB, ±4LSB, ±8LSB)	Normal mode, DAC output buffer OFF, ±1LSB CL=10 pF	-	1.7(2)	2(2)	μs
tWAKEUP(3)	Wakeup time from off state (setting the Enx bit in the DAC Control register) until the ±1LSB final value	Normal mode, DAC output buffer ON, CL ≤ 50 pF, RL = 5 ㏀	-	5	7.5	μs
Voffset(2)	Middle code offset for 1	VREF+ = 3.6 V		-	850	-	μV
	trim code step	VREF+ = 1.8 V	-	425	-

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
IDDA(DAC)	DAC quiescent consumption from VDDA	DAC output buffer ON	No load, middle code (0x800)	-	360	-
		No load, DAC output middle/worst - 20 buffer OFF code (0x800)	No load, worst code (0xF1C)	- -	490	-
		Sample and Hold mode, CSH=100 nF	-	360*TON/ (TON+TOFF)	-
IDDV(DAC)	DAC consumption from VREF+	DAC output buffer ON	No load, middle code (0x800)	-	170	-	μA
			No load, worst code (0xF1C)	-	170	-
		DAC output buffer OFF	No load, middle/worst code (0x800)	-	160	-
		Sample and Hold mode, Buffer ON, CSH=100 nF (worst code)		-	170*TON/ (TON+TOFF)	-
		Sample and Hold mode, Buffer OFF, CSH=100 nF (worst code) Table 89. DAC characteristics(1) (continued)		-	160*TON/ (TON+TOFF)	-
--	--	----------------------------------------------	--
--	--	----------------------------------------------	--

1. Guaranteed by characterization results.

2. Guaranteed by design.

1. In buffered mode, the output can overshoot above the final value for low input code (starting from the minimum value).

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
DNL	Differential non linearity(2)	DAC output buffer ON		-	±2	-
		DAC output buffer OFF		-	±2	-
INL	Integral non linearity(3)	DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 ㏀		-	±4	-
		DAC output buffer OFF, CL ≤ 50 pF, no RL		-	±4	-
Offset	Offset error at code 0x800 (3)	DAC output buffer ON,	VREF+ = 3.6 V	-	-	±12
		CL ≤ 50 pF, RL ≥ 5 ㏀	VREF+ = 1.8 V	-	-	±25
		DAC output buffer OFF, CL ≤ 50 pF, no RL		-	-	±8

Table 90. DAC accuracy(1)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
Offset1	Offset error at code 0x001(4)	DAC output buffer OFF, CL ≤ 50 pF, no RL		-	-	±5	LSB
OffsetCal	Offset error at code 0x800 after factory calibration	DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 ㏀	VREF+ = 3.6 V	-	-	±5	LSB
			VREF+ = 1.8 V	-	-	±7
Gain	Gain error(5)	DAC output buffer ON,CL ≤ 50 pF, RL ≥ 5 ㏀		-	-	±1	%
		DAC output buffer OFF, CL ≤ 50 pF, no RL		-	-	±1
TUE	Total unadjusted error	DAC output buffer OFF, CL ≤ 50 pF, no RL		-	-	±12	LSB
SNR	Signal-to-noise ratio(6)	DAC output buffer ON,CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz		-	67.8	-	dB
SINAD	Signal-to-noise and distortion ratio(6)	DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz		-	67.5	-	dB
ENOB	Effective number of bits	DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz		-	10.9	-	bits

Table 90. DAC accuracy(1) (continued)

1. Guaranteed by characterization.

2. Difference between two consecutive codes minus 1 LSB.

3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and last Code 4095.

1. Difference between the value measured at Code (0x001) and the ideal value.

2. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.

6. Signal is -0.5dBFS with Fsampling=1 MHz.

Figure 44. 12-bit buffered /non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

6.3.22 Voltage reference buffer characteristics

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
	Analog supply voltage	Normal mode	VSCALE = 000	2.8	3.3	3.6	V
			VSCALE = 001	2.4	-	3.6
			VSCALE = 010	2.1	-	3.6
			VSCALE = 011	1.8	-	3.6
VDDA		Degraded mode	VSCALE = 000	1.62	-	2.80
			VSCALE = 001	1.62	-	2.40
			VSCALE = 010	1.62	-	2.10
			VSCALE = 011	1.62	-	1.80
	Voltage Reference Buffer Output	Normal mode	VSCALE = 000	-	2.5	-
			VSCALE = 001	-	2.048	-
			VSCALE = 010	-	1.8	-
			VSCALE = 011	-	1.5	-
VREFBUF OUT		Degraded mode(2)	VSCALE = 000	VDDA- 150 mV	-	VDDA
			VSCALE = 001	VDDA- 150 mV	-	VDDA
			VSCALE = 010	VDDA- 150 mV	-	VDDA
			VSCALE = 011	VDDA- 150 mV	-	VDDA
TRIM	Trim step resolution	-	-	-	±0.05	±0.2	%
CL	Load capacitor	-	-	0.5	1	1.50	uF

Table 91. VREFBUF characteristics(1)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
esr	Equivalent Serial Resistor of CL	-	-	-	-	2	Ω
Iload	Static load current	-	-	-	-	4	mA
	Line regulation		Iload = 500 μA	-	200	-	ppm/V
Ilinereg		2.8 V ≤ VDDA ≤ 3.6 V	Iload = 4 mA	-	100	-
Iloadreg	Load regulation	500 μA ≤ ILOAD ≤ 4 mA	Normal Mode	-	50	-	ppm/ mA
Tcoeff	Temperature coefficient	-40 °C < TJ < +125 °C	-	-	-	Tcoeff xVREFINT + 75	ppm/ °C
	Power supply rejection	DC	-	-	60	-	dB
PSRR		100KHz	-	-	40	-
	Start-up time	CL=0.5 μF	-	-	300	-	μs
tSTART		C L=1 μF	-	-	500	-
		CL=1.5 μF	-	-	650	-
IINRUSH	Control of maximum DC current drive on VREFBUFOUT during startup phase(3)	-		-	8	-	mA
IDDA(VRE FBUF)	VREFBUF consumption from VDDA	ILOAD = 0 μA	-	-	15	25	μA
		ILOAD = 500 μA	-	-	16	30
		ILOAD = 4 mA	-	-	32	50

1. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA-drop voltage).

2. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.

6.3.23 Temperature sensor characteristics

Table 92. Temperature sensor characteristics

Symbol	Parameter	Min	Typ	Max	Unit
(1) TL	VSENSE linearity with temperature	-	-	±3	°C
AvgSlope(2)	Average slope	-	2	-	mV/°C
V30(3)	Voltage at 30°C ± 5 °C	-	0.62	-	V
tstartrun(1)	Startup time in Run mode (buffer startup)	-	-	25.2
tStemp(1)	ADC sampling time when reading the temperature	9	-	-	μs
Isens(1)	Sensor consumption	-	0.18	0.31	μA
Isensbuf(1)	Sensor buffer consumption	-	3.8	6.5

• 1. Guaranteed by characterization.
• 1. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.

Symbol	Parameter	Memory address
TSCAL1	Temperature sensor raw data acquired value at 30 °C, VDDA=3.3 V	0x1FF1 E820 -0x1FF1 E821
TSCAL2	Temperature sensor raw data acquired value at 110 °C, VDDA=3.3 V	0x1FF1 E840 - 0x1FF1 E841

Table 93. Temperature sensor calibration values

6.3.24 Temperature and VBAT monitoring

Symbol	Parameter	Min	Typ	Max	Unit
R	Resistor bridge for VBAT	-	26	-	KΩ
Q	Ratio on VBAT measurement	-	4	-	-
Er(1)	Error on Q	–10	-	+10	%
tSvbat(1)	ADC sampling time when reading VBAT input	9	-	-	μs
VBAThigh	High supply monitoring	-	3.55	-	V
VBATlow	Low supply monitoring	-	1.36	-

Table 94. VBAT monitoring characteristics

1. Guaranteed by design.

Table 95. VBAT charging characteristics

Symbol	Parameter	Condition	Min	Typ	Max	Unit
RBC	Battery charging resistor	VBRS in PWRCR3= 0	-	5	-	KΩ
		VBRS in PWRCR3= 1	-	1.5	-

Table 96. Temperature monitoring characteristics

Symbol	Parameter	Min	Typ	Max	Unit
TEMPhigh	High temperature monitoring	-	117	-
TEMPlow	Low temperature monitoring	-	–25	-	°C

6.3.25 Voltage booster for analog switch

Symbol	Parameter	Condition	Min	Typ	Max	Unit
VDD	Supply voltage	-	1.62	2-6	3.6	V
tSU(BOOST)	Booster startup time	-	-	-	50	μs
IDD(BOOST)	Booster consumption	1.62 V ≤ VDD ≤ 2.7 V	-	-	125	μA
		2.7 V < VDD < 3.6 V	-	-	250

1. Guaranteed by characterization results.

6.3.26 Comparator characteristics

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
VDDA	Analog supply voltage		1.62	3.3	3.6
VIN	Comparator input voltage range	-		0	-	VDDA	V
VBG(2)	Scaler input voltage		-		Refer to VREFINT
VSC	Scaler offset voltage		-	-	±5	±10	mV
	Scaler static consumption	BRGEN=0 (bridge disable)		-	0.2	0.3
IDDA(SCALER)	from VDDA		BRGEN=1 (bridge enable)	-	0.8	1	μA
tSTARTSCALER	Scaler startup time		-	-	140	250	μs
	Comparator startup time to		High-speed mode	-	2	5
tSTART	reach propagation delay		Medium mode	-	5	20	μs
	specification		Ultra-low-power mode	-	15	80
	Propagation delay for		High-speed mode	-	50	80	ns
	200 mV step with 100 mV overdrive	Medium mode		-	0.5	1.2
		Ultra-low-power mode		-	2.5	7	μs
tD	Propagation delay for step > 200 mV with 100 mV overdrive only on positive inputs	High-speed mode		-	50	120	ns
		Medium mode		-	0.5	1.2	μs
		Ultra-low-power mode		-	2.5	7
Voffset	Comparator offset error	Full common mode range		-	±5	±20	mV
	Comparator hysteresis	No hysteresis		-	0	-	mV
		Low hysteresis		-	10	-
Vhys		Medium hysteresis		-	20	-
		High hysteresis		-	30	-
	Comparator consumption from VDDA	Ultra-low power mode	Static	-	400	600
IDDA(COMP)			With 50 kHz ±100 mV overdrive square signal	-	800	-	nA
			Static	-	5	7
		Medium mode	With 50 kHz ±100 mV overdrive square signal	-	6	-
			Static	-	70	100	μA
	Table 98. COMP characteristics(1)	High-speed mode	With 50 kHz ±100 mV overdrive square signal	-	75	-
--	-----------------------------------
--	-----------------------------------

1. Guaranteed by design, unless otherwise specified.

2. Refer to Table 28: Embedded reference voltage.

6.3.27 Operational amplifier characteristics

• Symbol
• VDDA
• CMIR
• VIOFFSET
• ΔVIOFFSET
• TRIMOFFSETP
  TRIMLPOFFSETP
• TRIMOFFSETN
  TRIMLPOFFSETN
• ILOAD
• ILOAD_PGA
• CLOAD
• CMRR
• PSRR
• GBW
• SR
• AO
• φm
• GM

Table 99. OPAMP characteristics(1)

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
VOHSAT	High saturation voltage		Iload=max or RLOAD=min(2), Input at VDDA	VDDA -100 mV	-	-	mV
VOLSAT	Low saturation voltage		Iload=max or RLOAD=min(2), Input at 0 V	-	-	100
tWAKEUP	Wake up time from OFF	Normal mode	CLOAD ≤ 50pf, ≥ 4 kΩ(2), RLOAD follower configuration	-	0.8	3.2	μs
	state	High speed	CLOAD ≤ 50pf, ≥ 4 kΩ(2), RLOAD follower configuration	-	0.9	2.8
			-	-	2	-	-
	Non inverting gain value	-		-	4	-	-
		-		-	8	-	-
PGA gain		-		-	16	-	-
	Inverting gain value	-		-	-1	-	-
		-		-	-3	-	-
		-		-	-7	-	-
			-	-	-15	-	-
	R2/R1 internal resistance values in non-inverting PGA mode(3)		PGA Gain=2	-	10/10	-
		PGA Gain=4		-	30/10	-	kΩ/ kΩ
		PGA Gain=8		-	70/10	-
		PGA Gain=16		-	150/10	-
Rnetwork		PGA Gain=-1		-	10/10	-
	R2/R1 internal resistance values in inverting PGA mode(3)	PGA Gain=-3		-	30/10	-
		PGA Gain=-7		-	70/10	-
		PGA Gain=-15		-	150/10	-
Delta R	Resistance variation (R1 or R2)	-		-15	-	15	%
		Gain=2		-	GBW/2	-
	PGA bandwidth for	Gain=4		-	GBW/4	-
PGA BW	different non inverting gain	Gain=8		-	GBW/8	-	MHz
		Gain=16		-	GBW/16	-

Table 99. OPAMP characteristics(1) (continued)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
en	Voltage noise density	at 1 KHz	output loaded with 4 kΩ	-	140	-	nV/√ Hz
		at 10 KHz		-	55	-
IDDA(OPAMP)	OPAMP consumption from VDDA	Normal mode	no Load, quiescent mode, follower	-	570	1000	μA
		High speed mode		-	610	1200

1. Guaranteed by design, unless otherwise specified.

2. RLOAD is the resistive load connected to VSSA or to VDDA.

3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.

6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 100 for DFSDM are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for DFSDMx).

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
fDFSDMCLK	DFSDM clock	1.62 V < VDD < 3.6 V		-	-	250
fCKIN (1/TCKIN)	Input clock frequency	SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 V < VDD < 3.6 V		-	-	20 (fDFSDMCLK/4)
		SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 2.7 < VDD < 3.6 V		-	-	20 (fDFSDMCLK/4)
		SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]≠0), 1.62 < VDD < 3.6 V	SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]≠0), 2.7 < VDD < 3.6 V	-	- -	20 (fDFSDMCLK/4) 20 (fDFSDMCLK/4)	MHz
fCKOUT	Output clock frequency	1.62 < VDD < 3.6 V		-	-	20
DuCyCKOUT	Output clock frequency duty cycle			45	50	55
		1.62 < VDD < 3.6 V		Odd division, CKOUTDIV[7:0] = 2, 4, 6	(((n/2+1)/(n+1))* 100)–5	(((n/2+1)/(n+1)) *100)	(((n/2+1)/(n+1))* 100)+5

Table 100. DFSDM measured timing - 1.62-3.6 V(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
twh(CKIN) twl(CKIN)	Input clock high and low time	SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V	TCKIN/2 - 0.5	TCKIN/2	-
tsu	Data input setup time	SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V	4	-	-
th	Data input hold time	SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V	0.5	-	-	ns
TManchester	Manchester data period (recovered clock period)	Manchester mode (SITP[1:0]=2,3), Internal clock mode (SPICKSEL[1:0]≠0), 1.62 < VDD < 3.6 V	(CKOUTDIV+1) * TDFSDMCLK	-	(2CKOUTDIV) TDFSDMCLK
Table 100. DFSDM measured timing - 1.62-3.6 V(1) (continued)
--------------------------------------------------------------	--	--	--	--	--	--
--------------------------------------------------------------	--	--	--	--	--	--

1. Guaranteed by characterization results.

Figure 45. Channel transceiver timing diagrams

186/357 DS12110 Rev 10

6.3.29 Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 101 for DCMI are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage summarized in Table 24: General operating conditions, with the following configuration:

• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load C=30 pF
• Measurement points are done at CMOS levels: 0.5VDD

Symbol	Parameter		Max	Unit
-	Frequency ratio DCMIPIXCLK/frcccck		0.4	-
DCMIPIXCLK	Pixel clock input		80	MHz
DPixel	Pixel clock input duty cycle	30	70	%
tsu(DATA)	Data input setup time	1	-
th(DATA)	Data input hold time	1	-
tsu(HSYNC) tsu(VSYNC)	DCMIHSYNC/DCMIVSYNC input setup time	1.5	-	ns
th(HSYNC) th(VSYNC)	DCMIHSYNC/DCMIVSYNC input hold time	1	-

Table 101. DCMI characteristics(1)

1. Guaranteed by characterization results.

6.3.30 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 102 for LCD-TFT are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage summarized in Table 24: General operating conditions, with the following configuration:

• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C=30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• I/O compensation cell enabled

Symbol	Parameter	Conditions	Min	Max	Unit
		2.7 V < VDD < 3.6 V, 20 pF	-	150	MHz
fCLK	LTDC clock output frequency	2.7 V < VDD < 3.6 V	-	133
		1.62 V < VDD < 3.6 V	-	90
DCLK	LTDC clock output duty cycle	-	45	55	%
tw(CLKH), tw(CLKL)	Clock High time, low time	-	tw(CLK)/2-0.5	tw(CLK)/2+0.5
tv(DATA)	Data output valid time	-	-	0.5
th(DATA)	Data output hold time	-	0	-
tv(HSYNC), tv(VSYNC), tv(DE)	HSYNC/VSYNC/DE output valid time	-	-	0.5	ns
th(HSYNC), th(VSYNC), th(DE)	HSYNC/VSYNC/DE output hold time	-	0.5	-

Table 102. LTDC characteristics (1)

1. Guaranteed by characterization results.

Figure 47. LCD-TFT horizontal timing diagram

Active width Vertical

One frame

back porch

Figure 48. LCD-TFT vertical timing diagram

VSYNC width

Vertical back porch

MS32750V1

6.3.31 Timer characteristics

The parameters given in Table 103 are guaranteed by design.

Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Symbol	Parameter	Conditions(3)	Min	Max	Unit
tres(TIM)		AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 240 MHz	1	-	tTIMxCLK
	Timer resolution time	AHB/APBx prescaler>4, fTIMxCLK = 140 MHz	1	-	tTIMxCLK
fEXT	Timer external clock frequency on CH1 to CH4 fTIMxCLK = 240 MHz		0	fTIMxCLK/2	MHz
ResTIM	Timer resolution		-	16/32	bit
tMAXCOUNT	Maximum possible count with 32-bit counter	-	-	65536 × 65536	tTIMxCLK

			Table 103. TIMx characteristics(1)(2)
--	--	--	---------------------------------------

1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.

2. Guaranteed by design.

3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx_d2.

6.3.32 Communications interfaces

I 2 C interface characteristics

The I² C interface meets the timings requirements of the I2 C-bus specification and user manual revision 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
• Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.

The I² C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0433 reference manual) and when the i2c_ker_ck frequency is greater than the minimum shown in the table below:

Symbol	Parameter	Condition		Min	Unit
	I2CCLK frequency	Standard-mode		2
f(I2CCLK)		Fast-mode	Analog filter ON DNF=0	8
			Analog filter OFF DNF=1	9	MHz
		Fast-mode Plus	Analog filter ON DNF=0 Analog filter OFF DNF=1	17 16 Table 104. Minimum i2ckerck frequency in all I2C modes
--	--	--	--	----------------------------------------------------------

• The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but still present.
• The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas:

tr(SDA/SCL)=0.8473xRpxCload

Rp(min)= (VDD-VOL(max))/IOL(max)

Where Rp is the I2C lines pull-up. Refer to Section 6.3.15: I/O port characteristics for the I2C I/Os characteristics.

All I2 C SDA and SCL I/Os embed an analog filter. Refer to Table 105 for the analog filter characteristics:

			Table 105. I2C analog filter characteristics(1)
--	--	--	-------------------------------------------------

Symbol	Parameter	Min	Max	Unit
tAF	Maximum pulse width of spikes that are suppressed by the analog filter	50(2)	260(3)	ns

1. Spikes with widths below tAF(min) are filtered.

2. Spikes with widths above tAF(max) are not filtered.

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 106 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• I/O compensation cell enabled
• HSLV activated when VDD ≤ 2.7 V

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fSCK 1/tc(SCK)	SPI clock frequency	Master mode 1.62 V≤VDD≤3.6 V Master mode 2.7 V≤VDD≤3.6 V SPI1,2,3 Master mode 2.7 V≤VDD≤3.6 V SPI4,5,6 Slave receiver mode 1.62 V≤VDD≤3.6 V SPI1,2,3 Slave receiver mode 1.62 V≤VDD≤3.6 V SPI4,5,6 Slave mode transmitter/full duplex 2.7 V≤VDD≤3.6 V Slave mode transmitter/full duplex 1.62 V≤VDD≤3.6 V	-	-	90 133 100 150 100 31 25	MHz
tsu(NSS)	NSS setup time	Slave mode	2	-	-
th(NSS)	NSS hold time		1	-	-	ns
tw(SCKH), tw(SCKL)	SCK high and low time	Master mode	TPLCK - 2	TPLCK	TPLCK + 2

Table 106. SPI dynamic characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tsu(MI)		Master mode	2	-	-
tsu(SI)	Data input setup time	Slave mode	2	-	-
th(MI)	Data input hold time	Master mode	1	-	-
th(SI)		Slave mode	1	-	-
ta(SO)	Data output access time	Slave mode	9	13	27
tdis(SO)	Data output disable time	Slave mode	0	1	5	ns
	Data output valid time	Slave mode, 2.7 V≤VDD≤3.6 V	-	11.5	16
tv(SO)		Slave mode 1.62 V≤VDD≤3.6 V	-	13	20
tv(MO)		Master mode	-	1	3
th(SO)		Slave mode, 1.62 V≤VDD≤3.6 V	9	-	-
th(MO)	Data output hold time	Master mode	0	-	-

1. Guaranteed by characterization results.

1. Measurement points are done at 0.5VDD and with external CL = 30 pF.

Figure 51. SPI timing diagram - master mode(1)

1. Measurement points are done at 0.5VDD and with external CL = 30 pF.

I 2S interface characteristics

Unless otherwise specified, the parameters given in Table 107 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• I/O compensation cell enabled

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS).

Symbol	Parameter	Conditions	Min	Max	Unit
fMCK	I2S Main clock output	-	256x8K	256FS	MHz
	I2S clock frequency	Master data	-	64FS
fCK		Slave data	-	64FS	MHz
tv(WS)	WS valid time	Master mode	-	3.5
th(WS)	WS hold time	Master mode	0	-
tsu(WS)	WS setup time	Slave mode	1	-
th(WS)	WS hold time	Slave mode	1	-
tsu(SDMR)		Master receiver	1	-
tsu(SDSR)	Data input setup time	Slave receiver	1	-
th(SDMR)		Master receiver	4	-	ns
th(SDSR)	Data input hold time	Slave receiver	2	-
tv(SDST)		Slave transmitter (after enable edge)	-	20
tv(SDMT)	Data output valid time	Master transmitter (after enable edge)	-	3
th(SDST)		Slave transmitter (after enable edge)	9	-
th(SDMT)	Data output hold time	Master transmitter (after enable edge)	0	-

Table 107. I2S dynamic characteristics(1)

1. Guaranteed by characterization results.

Figure 52. I2S slave timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 53. I2S master timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

SAI characteristics

Unless otherwise specified, the parameters given in Table 108 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5VDD

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS).

Symbol	Parameter	Conditions	Min Max		Unit
fMCK	SAI Main clock output	-	256 x 8K	256xFs	MHz
	SAI clock frequency(2)	Master data: 32 bits	-	128xFs(3)	MHz
FCK		Slave data: 32 bits	-	128xFs
		Master mode	-	15
tv(FS)	FS valid time	2.7≤VDD≤3.6V
		Master mode 1.71≤VDD≤3.6V	-	20
tsu(FS)	FS setup time FS hold time	Slave mode	7 - Master mode 1 - Slave mode 1 - Master receiver 0.5 - Slave receiver 1 -		ns
th(FS)
tsu(SDAMR)	Data input setup time
tsu(SDBSR)
th(SDAMR)	Data input hold time	Master receiver	3.5	-
th(SDBSR)		Slave receiver	2	-
tv(SDBST)	Data output valid time	Slave transmitter (after enable edge) 2.7≤VDD≤3.6V	-	17
		Slave transmitter (after enable edge) 1.62≤VDD≤3.6V	-	20
th(SDBST)	Data output hold time	Slave transmitter (after enable edge)	7	-
tv(SDAMT)	Data output valid time	Master transmitter (after enable edge) 2.7≤VDD≤3.6V	-	17	ns
		Master transmitter (after enable edge) 1.62≤VDD≤3.6V	-	20
th(SDAMT)	Data output hold time	Master transmitter (after enable edge)	7.55 -

Table 108. SAI characteristics(1)

1. Guaranteed by characterization results.

2. APB clock frequency must be at least twice SAI clock frequency.

3. With FS=192 kHz.

DS12110 Rev 10 197/357

Figure 54. SAI master timing waveforms

MDIO characteristics

Table 109. MDIO Slave timing parameters

Symbol	Parameter	Min	Typ	Max	Unit
FsDC	Management data clock	-	-	40	MHz
td(MDIO)	Management data input/output output valid time	7	8	20
t su(MDIO)	Management data input/output setup time	4	-	-	ns
th(MDIO)	Management data input/output hold time	1	-	-

Figure 56. MDIO Slave timing diagram

SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 110 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• I/O compensation cell enabled
• HSLV activated when VDD ≤ 2.7 V

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)
----------------------------------------------------------------------------------------

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fPP	Clock frequency in data transfer mode	-	0	-	125	MHz
tW(CKL)	Clock low time		9.5	10.5	-	ns
tW(CKH)	Clock high time	fPP =50 MHz	8.5	9.5	-
CMD, D inputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tISU	Input setup time HS		3	-	-
tIH	Input hold time HS	fPP ≥ 50 MHz	0.5	-	-	ns
tIDW(3)	Input valid window (variable window)		3	-	-
CMD, D outputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tOV	Output valid time HS		-	3.5	5	ns
tOH	Output hold time HS	fPP ≥ 50 MHz	2	-	-

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
CMD, D inputs (referenced to CK) in SD default mode
tISUD	Input setup time SD	fPP =25 MHz	3	-	-
tIHD	Input hold time SD		0.5	-	-	ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD	Output valid default time SD	fPP =25 MHz	-	1	2
tOHD	Output hold default time SD		0	-	-	ns

Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)

1. Guaranteed by characterization results.

2. Above 100 MHz, CL = 20 pF.

3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Table 111. Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V(1)(2)
-------------------------------------------------------------------------------------

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fPP	Clock frequency in data transfer mode	-	0	-	120	MHz
tW(CKL)	Clock low time		9.5	10.5	-
tW(CKH)	Clock high time	fPP =50 MHz	8.5	9.5	-	ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU	Input setup time HS		2.5	-	-
t IH	Input hold time HS	fPP ≥ 50 MHz	1	-	-	ns
tIDW(3)	Input valid window (variable window)		3.5	-	-
CMD, D outputs (referenced to CK) in eMMC mode
tOV	Output valid time HS		-	5	7
tOH	Output hold time HS	fPP ≥ 50 MHz	3	-	-	ns

1. Guaranteed by characterization results.

2. CL = 20 pF.

3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Figure 57. SDIO high-speed mode

Figure 58. SD default mode

Figure 59. DDR mode

CAN (controller area network) interface

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (FDCANx_TX and FDCANx_RX).

USB OTG_FS characteristics

The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation).

Symbol	Parameter	Condition	Min	Typ	Max	Unit
VDD33USB	USB transceiver operating voltage	-	3.0(1)	-	3.6	V
RPUI	Embedded USBDP pull-up value during idle	-	900	1250	1600
RPUR	Embedded USBDP pull-up value during reception	-	1400	2300	3200	Ω
ZDRV	Output driver impedance(2)	Driver high and low	28	36 Table 112. USB OTGFS electrical characteristics	44
--	--	--	--	--------------------------------------------------
--	--	--	--	--------------------------------------------------

1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7 to 3.0 V voltage range.

2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver.

USB OTG_HS characteristics

Unless otherwise specified, the parameters given in Table 113 for ULPI are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5VDD.

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tSC	Control in (ULPIDIR, ULPINXT) setup time	-	0.5	-	-
tHC	Control in (ULPIDIR, ULPINXT) hold time	-	6.5	-	-
tSD Data in setup time		-	2.5	-	-
tHD	Data in hold time	-	0	-	-
tDC/tDD	Data/control output delay	2.7 V < VDD < 3.6 V, CL = 20 pF -	- -	6.5	8.5	ns
		1.7 V < V DD < 3.6 V, CL = 15 pF	-	6.5	13

1. Guaranteed by characterization results.

Ethernet characteristics

Unless otherwise specified, the parameters given in Table 114, Table 115 and Table 116 for SMI, RMII and MII are derived from tests performed under the ambient temperature, frcc_cck frequency summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5VDD.

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

Table 114 gives the list of Ethernet MAC signals for the SMI and Figure 61 shows the corresponding timing diagram.

Symbol	Parameter	Min	Typ	Max	Unit
tMDC	MDC cycle time(2.5 MHz)	400	400	403
Td(MDIO)	Write data valid time	1	1.5	3
tsu(MDIO)	Read data setup time	8	-	-	ns
th(MDIO)	Read data hold time	0	-	-
Table 114. Dynamics characteristics: Ethernet MAC signals for SMI(1)
----------------------------------------------------------------------	--

Table 115 gives the list of Ethernet MAC signals for the RMII and Figure 62 shows the corresponding timing diagram.

• Symbol

---

• tsu(RXD)
• tih(RXD)
• tsu(CRS)
• tih(CRS)
• td(TXEN)
• td(TXD)

1. Guaranteed by characterization results.

Table 116 gives the list of Ethernet MAC signals for MII and Figure 63 shows the corresponding timing diagram.

Symbol	Parameter	Min	Typ	Max	Unit
tsu(RXD)	Receive data setup time	2	-	-
tih(RXD)	Receive data hold time	3	-	-
tsu(DV)	Data valid setup time	1.5	-	-
tih(DV)	Data valid hold time	1	-	-	ns
tsu(ER)	Error setup time	1.5	-	-
tih(ER)	Error hold time	0.5	-	-
td(TXEN)	Transmit enable valid delay time	4.5	6.5	11
td(TXD)	Transmit data valid delay time	7	7.5	15

1. Guaranteed by characterization results.

6.3.33 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 117 and Table 118 for JTAG/SWD are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 0x10
• Capacitive load C=30 pF
• Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

DS12110 Rev 10 205/357

</vdd<> </vdd<> </vdd<> </vdd<>

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Fpp	TCK clock frequency	2.7 V <vdd< 3.6="" td="" v<="">	-	-	37		-	-	37
1/tc(TCK)		1.62 V <vdd< 3.6="" td="" v<="">	-	-	27.5	MHz	-	-	27.5	MHz
tisu(TMS)	TMS input setup time	-	2	-	-
tih(TMS)	TMS input hold time	-	1	-	-	ns
tisu(TDI)	TDI input setup time	-	1.5	-	-
tih(TDI)	TDI input hold time	-	1	-	-
tov (TDO)	TDO output valid time	2.7 V <vdd< 3.6="" td="" v<="">	-	8	13.5		-	8	13.5
		1.62 V <vdd< 3.6="" td="" v<="">	-	8	18		-	8	18
toh(TDO)	TDO output hold time	-	7	-	-

1. Guaranteed by characterization results.

</vdd<> </vdd<> </vdd<> </vdd<>

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Fpp	SWCLK clock frequency	2.7 V <vdd< 3.6="" td="" v<="">	-	-	71		-	-	71
1/tc(SWCLK)		1.62 V <vdd< 3.6="" td="" v<="">	-	-	55.5	MHz	-	-	55.5	MHz
tisu(SWDIO)	SWDIO input setup time	-	2.5	-	-
tih(SWDIO)	SWDIO input hold time	-	1	-	-
tov (SWDIO)	SWDIO output valid time	2.7 V <vdd< 3.6="" td="" v<="">	-	8.5	14	ns	-	8.5	14	ns
		1.62 V <vdd< 3.6="" td="" v<="">	-	8.5	18		-	8.5	18
toh(SWDIO)	SWDIO output hold time	-	8	-	-

Table 118. Dynamics SWD characteristics(1)

1. Guaranteed by characterization results.