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STM32H74X

Microcontroller Unit (MCU)

The STM32H74X is a microcontroller unit (mcu) from STMicroelectronics. View the full STM32H74X datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

STMicroelectronics

Overview

Part: STM32H742xI/G, STM32H743xI/G from STMicroelectronics

Type: 32-bit Arm® Cortex®-M7 Microcontroller Unit (MCU)

Description: 32-bit Arm® Cortex®-M7 MCU at up to 480 MHz with up to 2 MB Flash, up to 1 MB RAM, and 46 communication and analog interfaces.

Operating Conditions:

  • Supply voltage: 1.62 to 3.6 V
  • Operating temperature: -40 to +125 °C (Junction)
  • Max CPU frequency: 480 MHz

Absolute Maximum Ratings:

  • Max supply voltage: 3.8 V
  • Max junction/storage temperature: -65 to +150 °C (Storage)

Key Specs:

  • Core: 32-bit Arm® Cortex®-M7 with double-precision FPU, up to 480 MHz, 1027 DMIPS, 16 KB data/16 KB instruction L1 cache.
  • Flash Memory: Up to 2 Mbytes with read-while-write support.
  • RAM: Up to 1 Mbyte (192 Kbytes TCM, up to 864 Kbytes user SRAM, 4 Kbytes Backup SRAM).
  • Low-power consumption: 2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON).
  • Analog-to-Digital Converters: 3x 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS).
  • Digital-to-Analog Converters: 2x 12-bit (1 MHz).
  • Communication Interfaces: 4x I2C, 4x USART/4x UART/1x LPUART, 6x SPI, 2x CAN FD, 2x USB OTG, Ethernet MAC.
  • Timers: Up to 22 timers and watchdogs, including 1x high-resolution timer (2.1 ns max resolution).

Features:

  • Voltage scaling in Run and Stop mode (6 configurable ranges)
  • Dedicated USB power with 3.3 V internal regulator
  • Hardware JPEG Codec
  • LCD-TFT controller up to XGA resolution
  • True random number generators (3 oscillators each)

Applications:

Package:

  • TFBGA100 (8 x 8 mm)
  • TFBGA240+25 (14 x 14 mm)
  • LQFP100 (14 x 14 mm)
  • LQFP144 (20 x 20 mm)
  • LQFP176 (24 x 24 mm)
  • LQFP208 (28 x 28 mm)
  • UFBGA169 (7 x 7 mm)
  • UFBGA176+25 (10 x 10 mm)

Pin Configuration

Figure 5. LQFP100 pinout

100

Electrical Characteristics

Unless otherwise specified, the parameters given in Table 77 are derived from tests performed under the ambient temperature, f HCLK frequency and V DDA supply voltage conditions summarized in Table 14: General operating conditions .

Table 77. ADC characteristics (1)

SymbolParameterConditionsMinTypMaxUnit
V DDAAnalog power supply--1.62-3.6 DDAV
V REF+Positive reference voltageV DDA ≥ 2 VV DDA ≥ 2 V2-VV
V REF+Positive reference voltageV DDA < 2 VV DDA < 2 VV DDAV DDAV DDAV
V REF-Negative reference voltage--V SSAV SSAV SSAV
f ADCADC clock frequency2 V ≤ V DDA ≤ 3.3 VBOOST=1--36MHz
f ADCADC clock frequency2 V ≤ V DDA ≤ 3.3 VBOOST = 0--20MHz
f SSampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2)16-bit resolution16-bit resolution--3.60 (2)MSPS
f SSampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2)14-bit resolution14-bit resolution--4.00 (2)MSPS
f SSampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2)12-bit resolution12-bit resolution--4.50 (2)MSPS
f SSampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2)10-bit resolution10-bit resolution--5.00 (2)MSPS
f SSampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2)8-bit resolution8-bit resolution--6.00 (2)MSPS
f SSampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz16-bit resolution16-bit resolution--2.00 (2)MSPS
f SSampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz14-bit resolution14-bit resolution--2.20 (2)MSPS
f SSampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz12-bit resolution12-bit resolution--2.50 (2)MSPS
f SSampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz10-bit resolution10-bit resolution--2.80 (2)MSPS
f SSampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz8-bit resolution8-bit resolution--3.30 (2)MSPS
f SSampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz16-bit resolution16-bit resolution--1.00MSPS
f SSampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz14-bit resolution14-bit resolution--1.00MSPS
f SSampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz12-bit resolution12-bit resolution--1.00MSPS
f SSampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz10-bit resolution10-bit resolution--1.00MSPS
f SSampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz8-bit resolution8-bit resolution--1.00MSPS

Table 77. ADC characteristics (1)

Table 77. ADC characteristics (1) (continued)

SymbolParameterConditionsMinTypMaxUnit
V AIN (3)Conversion voltage range-0-V REF+V
V CMIVCommon mode input voltage-V REF /2 - 10%V REF /2V REF /2+ 10%V
R AINExternal input impedance---50k Ω
C ADCInternal sample and hold capacitor--4-pF
t ADCREG_ STUPADC LDO startup time--510μs
t STABADC power-up timeLDO already started111conversion cycle
t CALOffset and linearity calibration time-165,010165,010165,0101/f ADC
t OFFCALOffset calibration time-1,2801,2801,2801/f ADC
t LATRTrigger conversion latency for regular and injected channels without aborting the conversionCKMODE = 001.522.51/f ADC
t LATRTrigger conversion latency for regular and injected channels without aborting the conversionCKMODE = 01--21/f ADC
t LATRTrigger conversion latency for regular and injected channels without aborting the conversionCKMODE = 102.251/f ADC
t LATRTrigger conversion latency for regular and injected channels without aborting the conversionCKMODE = 112.1251/f ADC
t LATRINJTrigger conversion latency for regular and injected channels when a regular conversion is abortedCKMODE = 002.533.51/f ADC
t LATRINJTrigger conversion latency for regular and injected channels when a regular conversion is abortedCKMODE = 01--31/f ADC
t LATRINJTrigger conversion latency for regular and injected channels when a regular conversion is abortedCKMODE = 10--3.251/f ADC
t LATRINJTrigger conversion latency for regular and injected channels when a regular conversion is abortedCKMODE = 11--3.1251/f ADC
t SSampling time-1.5-810.51/f ADC
t CONVTotal conversion time (including sampling time)N-bit resolutiont S + 0.5 + N/2 (9 to 648 cycles in 14-bit mode)t S + 0.5 + N/2 (9 to 648 cycles in 14-bit mode)t S + 0.5 + N/2 (9 to 648 cycles in 14-bit mode)
t TRIGExternal trigger period16 bits resolutiont CONV + [t LATR or t LATRINJ ]--1/f ADC

316

Table 78. ADC accuracy (1)(2)(3)

SymbolParameterConditions (4)Conditions (4)MinTypMaxUnit
ETTotal unadjusted errorSingle endedBOOST = 1-±6-±LSB
ETTotal unadjusted errorSingle endedBOOST = 0-±8-±LSB
ETTotal unadjusted errorDifferentialBOOST = 1-±10-±LSB
ETTotal unadjusted errorDifferentialBOOST = 0-±16-±LSB
EDDifferential linearity errorSingle endedBOOST = 1-2-±LSB
EDDifferential linearity errorSingle endedBOOST = 0-1-±LSB
EDDifferential linearity errorDifferentialBOOST = 1-8-±LSB
EDDifferential linearity errorDifferentialBOOST = 0-2-±LSB
ELIntegral linearity errorSingle endedBOOST = 1-±6-±LSB
ELIntegral linearity errorSingle endedBOOST = 0-±4-±LSB
ELIntegral linearity errorDifferentialBOOST = 1-±6-±LSB
ELIntegral linearity errorDifferentialBOOST = 0-±4-±LSB
ENOB (5)Effective number of bits (2 MSPS)Single endedBOOST = 1-11.6-bits
ENOB (5)Effective number of bits (2 MSPS)Single endedBOOST = 0-12-bits
ENOB (5)Effective number of bits (2 MSPS)DifferentialBOOST = 1-13.3-bits
ENOB (5)Effective number of bits (2 MSPS)DifferentialBOOST = 0-13.5-bits
SINAD (5)Signal-to- noise and distortion ratio (2 MSPS)Single endedBOOST = 1-71.6-
SINAD (5)Signal-to- noise and distortion ratio (2 MSPS)Single endedBOOST = 0-74-
SINAD (5)Signal-to- noise and distortion ratio (2 MSPS)DifferentialBOOST = 1-81.83-
SINAD (5)Signal-to- noise and distortion ratio (2 MSPS)DifferentialBOOST = 0-83-
SNR (5)Signal-to- noise ratio (2 MSPS)Single endedBOOST = 1-72-
SNR (5)Signal-to- noise ratio (2 MSPS)Single endedBOOST = 0-74-dB
SNR (5)Signal-to- noise ratio (2 MSPS)DifferentialBOOST = 1-82-
SNR (5)Signal-to- noise ratio (2 MSPS)DifferentialBOOST = 0-83-
THD (5)Total harmonic distortionSingle endedBOOST = 1-- 78-
THD (5)Total harmonic distortionSingle endedBOOST = 0-- 80-
THD (5)Total harmonic distortionDifferentialBOOST = 1-- 90-
THD (5)Total harmonic distortionDifferentialBOOST = 0-- 95-

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I INJ(PIN) and Σ I INJ(PIN) in Section 6.3.14 does not affect the ADC accuracy.

Figure 38. ADC accuracy characteristics

Figure 39. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function

  1. Refer to Section 6.3.20: 16-bit ADC characteristics for the values of R AIN and C ADC .
  2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 50: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades conversion accuracy. To remedy this, f ADC should be reduced.
  3. Refer to Table 50: I/O static characteristics for the value of I lkg .
  4. Refer to Figure 15: Power supply scheme .
  5. The R ADC is used to compute the minimum sampling time, refer to Table 175: Minimum sampling time vs RAIN .

316

Absolute Maximum Ratings

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 11. Voltage characteristics (1)

SymbolsRatingsMinMaxUnit
V DDX - V SSExternal main supply voltage (including V DD , V DDLDO , V DDA , V DD33USB , V BAT )- 0.34.0V
V IN (2)Input voltage on FT_xxx pinsV SS - 0.3Min(Min(V DD , V DDA ,V DD33USB , V BAT ) + 4.0, 6 V) (3)(4)(5)V
V IN (2)Input voltage on TT_xx pinsV SS -0.34.0V
V IN (2)Input voltage on BOOT0 pinV SS9.0V
V IN (2)Input voltage on any other pinsV SS -0.34.0V
| ∆ V DDX |Variations between different V DDX power pins of the same domain-50mV
|V SSx -V SS |Variations between all the different ground pins-50mV

316

  1. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
  2. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
  3. When an FT_a pin is used by an analog peripheral such as an ADC, the maximum V IN is 4 V.
  4. All main power (V DD , V DDA , V DD33USB ) and ground (V SS , V SSA ) pins must always be connected to the external power supplies, in the permitted range.
  5. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
  6. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
  7. A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer also to Table 11: Voltage characteristics for the maximum allowed input voltage values.
  8. When several inputs are submitted to a current injection, the maximum ∑ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 12. Current characteristics

SymbolsRatingsMaxUnit
Σ IV DDTotal current into sum of all V DD power lines (source) (1)620mA
Σ IV SSTotal current out of sum of all V SS ground lines (sink) (1)620mA
IV DDMaximum current into each V DD power pin (source) (1)100mA
IV SSMaximum current out of each V SS ground pin (sink) (1)100mA
I IOOutput current sunk by any I/O and control pin, except Px_C20mA
I IOOutput current sunk by Px_C pins1mA
Σ I (PIN)Total output current sunk by sum of all I/Os and control pins (2)140mA
Σ I (PIN)Total output current sourced by sum of all I/Os and control pins (2)140mA
I INJ(PIN) (3)(4)Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5- 5/+0mA
I INJ(PIN) (3)(4)Injected current on PA4, PA5- 0/0mA
Σ I INJ(PIN)Total injected current (sum of all I/Os and control pins) (5)±25mA

Table 13. Thermal characteristics

SymbolRatingsValueUnit
T STGStorage temperature range-65 to +150°C
T JMaximum junction temperature125°C

Table 13. Thermal characteristics

Thermal Information

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max × Θ JA )

Package Information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark.

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