STM32H742ZI
Microcontroller Unit (MCU)The STM32H742ZI is a microcontroller unit (mcu) from STMicroelectronics. View the full STM32H742ZI datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
STMicroelectronics
Category
Microcontrollers (MCU)Overview
Part: STM32H742xI/G, STM32H743xI/G from STMicroelectronics
Type: 32-bit Arm® Cortex®-M7 Microcontroller Unit (MCU)
Description: 32-bit Arm® Cortex®-M7 MCU at up to 480 MHz with up to 2 MB Flash, up to 1 MB RAM, and 46 communication and analog interfaces.
Operating Conditions:
- Supply voltage: 1.62 to 3.6 V
- Operating temperature: -40 to +125 °C (Junction)
- Max CPU frequency: 480 MHz
Absolute Maximum Ratings:
- Max supply voltage: 3.8 V
- Max junction/storage temperature: -65 to +150 °C (Storage)
Key Specs:
- Core: 32-bit Arm® Cortex®-M7 with double-precision FPU, up to 480 MHz, 1027 DMIPS, 16 KB data/16 KB instruction L1 cache.
- Flash Memory: Up to 2 Mbytes with read-while-write support.
- RAM: Up to 1 Mbyte (192 Kbytes TCM, up to 864 Kbytes user SRAM, 4 Kbytes Backup SRAM).
- Low-power consumption: 2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON).
- Analog-to-Digital Converters: 3x 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS).
- Digital-to-Analog Converters: 2x 12-bit (1 MHz).
- Communication Interfaces: 4x I2C, 4x USART/4x UART/1x LPUART, 6x SPI, 2x CAN FD, 2x USB OTG, Ethernet MAC.
- Timers: Up to 22 timers and watchdogs, including 1x high-resolution timer (2.1 ns max resolution).
Features:
- Voltage scaling in Run and Stop mode (6 configurable ranges)
- Dedicated USB power with 3.3 V internal regulator
- Hardware JPEG Codec
- LCD-TFT controller up to XGA resolution
- True random number generators (3 oscillators each)
Applications:
Package:
- TFBGA100 (8 x 8 mm)
- TFBGA240+25 (14 x 14 mm)
- LQFP100 (14 x 14 mm)
- LQFP144 (20 x 20 mm)
- LQFP176 (24 x 24 mm)
- LQFP208 (28 x 28 mm)
- UFBGA169 (7 x 7 mm)
- UFBGA176+25 (10 x 10 mm)
Pin Configuration
Figure 5. LQFP100 pinout
100
Electrical Characteristics
Unless otherwise specified, the parameters given in Table 77 are derived from tests performed under the ambient temperature, f HCLK frequency and V DDA supply voltage conditions summarized in Table 14: General operating conditions .
Table 77. ADC characteristics (1)
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit | |
|---|---|---|---|---|---|---|---|
| V DDA | Analog power supply | - | - | 1.62 | - | 3.6 DDA | V |
| V REF+ | Positive reference voltage | V DDA ≥ 2 V | V DDA ≥ 2 V | 2 | - | V | V |
| V REF+ | Positive reference voltage | V DDA < 2 V | V DDA < 2 V | V DDA | V DDA | V DDA | V |
| V REF- | Negative reference voltage | - | - | V SSA | V SSA | V SSA | V |
| f ADC | ADC clock frequency | 2 V ≤ V DDA ≤ 3.3 V | BOOST=1 | - | - | 36 | MHz |
| f ADC | ADC clock frequency | 2 V ≤ V DDA ≤ 3.3 V | BOOST = 0 | - | - | 20 | MHz |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2) | 16-bit resolution | 16-bit resolution | - | - | 3.60 (2) | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2) | 14-bit resolution | 14-bit resolution | - | - | 4.00 (2) | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2) | 12-bit resolution | 12-bit resolution | - | - | 4.50 (2) | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2) | 10-bit resolution | 10-bit resolution | - | - | 5.00 (2) | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2) | 8-bit resolution | 8-bit resolution | - | - | 6.00 (2) | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 16-bit resolution | 16-bit resolution | - | - | 2.00 (2) | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 14-bit resolution | 14-bit resolution | - | - | 2.20 (2) | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 12-bit resolution | 12-bit resolution | - | - | 2.50 (2) | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 10-bit resolution | 10-bit resolution | - | - | 2.80 (2) | MSPS |
| f S | Sampling rate for Fast channels, BOOST = 0, f ADC = 20 MHz | 8-bit resolution | 8-bit resolution | - | - | 3.30 (2) | MSPS |
| f S | Sampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz | 16-bit resolution | 16-bit resolution | - | - | 1.00 | MSPS |
| f S | Sampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz | 14-bit resolution | 14-bit resolution | - | - | 1.00 | MSPS |
| f S | Sampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz | 12-bit resolution | 12-bit resolution | - | - | 1.00 | MSPS |
| f S | Sampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz | 10-bit resolution | 10-bit resolution | - | - | 1.00 | MSPS |
| f S | Sampling rate for Slow channels, BOOST = 0, f ADC = 10 MHz | 8-bit resolution | 8-bit resolution | - | - | 1.00 | MSPS |
Table 77. ADC characteristics (1)
Table 77. ADC characteristics (1) (continued)
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| V AIN (3) | Conversion voltage range | - | 0 | - | V REF+ | V |
| V CMIV | Common mode input voltage | - | V REF /2 - 10% | V REF /2 | V REF /2+ 10% | V |
| R AIN | External input impedance | - | - | - | 50 | k Ω |
| C ADC | Internal sample and hold capacitor | - | - | 4 | - | pF |
| t ADCREG_ STUP | ADC LDO startup time | - | - | 5 | 10 | μs |
| t STAB | ADC power-up time | LDO already started | 1 | 1 | 1 | conversion cycle |
| t CAL | Offset and linearity calibration time | - | 165,010 | 165,010 | 165,010 | 1/f ADC |
| t OFFCAL | Offset calibration time | - | 1,280 | 1,280 | 1,280 | 1/f ADC |
| t LATR | Trigger conversion latency for regular and injected channels without aborting the conversion | CKMODE = 00 | 1.5 | 2 | 2.5 | 1/f ADC |
| t LATR | Trigger conversion latency for regular and injected channels without aborting the conversion | CKMODE = 01 | - | - | 2 | 1/f ADC |
| t LATR | Trigger conversion latency for regular and injected channels without aborting the conversion | CKMODE = 10 | 2.25 | 1/f ADC | ||
| t LATR | Trigger conversion latency for regular and injected channels without aborting the conversion | CKMODE = 11 | 2.125 | 1/f ADC | ||
| t LATRINJ | Trigger conversion latency for regular and injected channels when a regular conversion is aborted | CKMODE = 00 | 2.5 | 3 | 3.5 | 1/f ADC |
| t LATRINJ | Trigger conversion latency for regular and injected channels when a regular conversion is aborted | CKMODE = 01 | - | - | 3 | 1/f ADC |
| t LATRINJ | Trigger conversion latency for regular and injected channels when a regular conversion is aborted | CKMODE = 10 | - | - | 3.25 | 1/f ADC |
| t LATRINJ | Trigger conversion latency for regular and injected channels when a regular conversion is aborted | CKMODE = 11 | - | - | 3.125 | 1/f ADC |
| t S | Sampling time | - | 1.5 | - | 810.5 | 1/f ADC |
| t CONV | Total conversion time (including sampling time) | N-bit resolution | t S + 0.5 + N/2 (9 to 648 cycles in 14-bit mode) | t S + 0.5 + N/2 (9 to 648 cycles in 14-bit mode) | t S + 0.5 + N/2 (9 to 648 cycles in 14-bit mode) | |
| t TRIG | External trigger period | 16 bits resolution | t CONV + [t LATR or t LATRINJ ] | - | - | 1/f ADC |
316
Table 78. ADC accuracy (1)(2)(3)
| Symbol | Parameter | Conditions (4) | Conditions (4) | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|---|
| ET | Total unadjusted error | Single ended | BOOST = 1 | - | ±6 | - | ±LSB |
| ET | Total unadjusted error | Single ended | BOOST = 0 | - | ±8 | - | ±LSB |
| ET | Total unadjusted error | Differential | BOOST = 1 | - | ±10 | - | ±LSB |
| ET | Total unadjusted error | Differential | BOOST = 0 | - | ±16 | - | ±LSB |
| ED | Differential linearity error | Single ended | BOOST = 1 | - | 2 | - | ±LSB |
| ED | Differential linearity error | Single ended | BOOST = 0 | - | 1 | - | ±LSB |
| ED | Differential linearity error | Differential | BOOST = 1 | - | 8 | - | ±LSB |
| ED | Differential linearity error | Differential | BOOST = 0 | - | 2 | - | ±LSB |
| EL | Integral linearity error | Single ended | BOOST = 1 | - | ±6 | - | ±LSB |
| EL | Integral linearity error | Single ended | BOOST = 0 | - | ±4 | - | ±LSB |
| EL | Integral linearity error | Differential | BOOST = 1 | - | ±6 | - | ±LSB |
| EL | Integral linearity error | Differential | BOOST = 0 | - | ±4 | - | ±LSB |
| ENOB (5) | Effective number of bits (2 MSPS) | Single ended | BOOST = 1 | - | 11.6 | - | bits |
| ENOB (5) | Effective number of bits (2 MSPS) | Single ended | BOOST = 0 | - | 12 | - | bits |
| ENOB (5) | Effective number of bits (2 MSPS) | Differential | BOOST = 1 | - | 13.3 | - | bits |
| ENOB (5) | Effective number of bits (2 MSPS) | Differential | BOOST = 0 | - | 13.5 | - | bits |
| SINAD (5) | Signal-to- noise and distortion ratio (2 MSPS) | Single ended | BOOST = 1 | - | 71.6 | - | |
| SINAD (5) | Signal-to- noise and distortion ratio (2 MSPS) | Single ended | BOOST = 0 | - | 74 | - | |
| SINAD (5) | Signal-to- noise and distortion ratio (2 MSPS) | Differential | BOOST = 1 | - | 81.83 | - | |
| SINAD (5) | Signal-to- noise and distortion ratio (2 MSPS) | Differential | BOOST = 0 | - | 83 | - | |
| SNR (5) | Signal-to- noise ratio (2 MSPS) | Single ended | BOOST = 1 | - | 72 | - | |
| SNR (5) | Signal-to- noise ratio (2 MSPS) | Single ended | BOOST = 0 | - | 74 | - | dB |
| SNR (5) | Signal-to- noise ratio (2 MSPS) | Differential | BOOST = 1 | - | 82 | - | |
| SNR (5) | Signal-to- noise ratio (2 MSPS) | Differential | BOOST = 0 | - | 83 | - | |
| THD (5) | Total harmonic distortion | Single ended | BOOST = 1 | - | - 78 | - | |
| THD (5) | Total harmonic distortion | Single ended | BOOST = 0 | - | - 80 | - | |
| THD (5) | Total harmonic distortion | Differential | BOOST = 1 | - | - 90 | - | |
| THD (5) | Total harmonic distortion | Differential | BOOST = 0 | - | - 95 | - |
Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for I INJ(PIN) and Σ I INJ(PIN) in Section 6.3.14 does not affect the ADC accuracy.
Figure 38. ADC accuracy characteristics
Figure 39. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function
- Refer to Section 6.3.20: 16-bit ADC characteristics for the values of R AIN and C ADC .
- Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 50: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades conversion accuracy. To remedy this, f ADC should be reduced.
- Refer to Table 50: I/O static characteristics for the value of I lkg .
- Refer to Figure 15: Power supply scheme .
- The R ADC is used to compute the minimum sampling time, refer to Table 175: Minimum sampling time vs RAIN .
316
Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics , Table 12: Current characteristics , and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.
Table 11. Voltage characteristics (1)
| Symbols | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DDX - V SS | External main supply voltage (including V DD , V DDLDO , V DDA , V DD33USB , V BAT ) | - 0.3 | 4.0 | V |
| V IN (2) | Input voltage on FT_xxx pins | V SS - 0.3 | Min(Min(V DD , V DDA ,V DD33USB , V BAT ) + 4.0, 6 V) (3)(4)(5) | V |
| V IN (2) | Input voltage on TT_xx pins | V SS -0.3 | 4.0 | V |
| V IN (2) | Input voltage on BOOT0 pin | V SS | 9.0 | V |
| V IN (2) | Input voltage on any other pins | V SS -0.3 | 4.0 | V |
| | ∆ V DDX | | Variations between different V DDX power pins of the same domain | - | 50 | mV |
| |V SSx -V SS | | Variations between all the different ground pins | - | 50 | mV |
316
- This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
- To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
- When an FT_a pin is used by an analog peripheral such as an ADC, the maximum V IN is 4 V.
- All main power (V DD , V DDA , V DD33USB ) and ground (V SS , V SSA ) pins must always be connected to the external power supplies, in the permitted range.
- This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
- Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
- A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer also to Table 11: Voltage characteristics for the maximum allowed input voltage values.
- When several inputs are submitted to a current injection, the maximum ∑ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).
Table 12. Current characteristics
| Symbols | Ratings | Max | Unit |
|---|---|---|---|
| Σ IV DD | Total current into sum of all V DD power lines (source) (1) | 620 | mA |
| Σ IV SS | Total current out of sum of all V SS ground lines (sink) (1) | 620 | mA |
| IV DD | Maximum current into each V DD power pin (source) (1) | 100 | mA |
| IV SS | Maximum current out of each V SS ground pin (sink) (1) | 100 | mA |
| I IO | Output current sunk by any I/O and control pin, except Px_C | 20 | mA |
| I IO | Output current sunk by Px_C pins | 1 | mA |
| Σ I (PIN) | Total output current sunk by sum of all I/Os and control pins (2) | 140 | mA |
| Σ I (PIN) | Total output current sourced by sum of all I/Os and control pins (2) | 140 | mA |
| I INJ(PIN) (3)(4) | Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5 | - 5/+0 | mA |
| I INJ(PIN) (3)(4) | Injected current on PA4, PA5 | - 0/0 | mA |
| Σ I INJ(PIN) | Total injected current (sum of all I/Os and control pins) (5) | ±25 | mA |
Table 13. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | -65 to +150 | °C |
| T J | Maximum junction temperature | 125 | °C |
Table 13. Thermal characteristics
Thermal Information
The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:
T J max = T A max + (P D max × Θ JA )
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark.
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