STM32H

Part: STM32H742xI/G, STM32H743xI/G

Type: ARM Cortex-M7 Microcontroller

Description: 32-bit ARM Cortex-M7 MCU with a 480 MHz core, up to 2 MB Flash, up to 1 MB RAM, and 46 communication and analog interfaces.

Operating Conditions:

• Supply voltage: 1.62–3.6 V
• Operating temperature: -40 to +125 °C (

Includes ST state-of-the-art patented technology

Core

• 32-bit Arm® Cortex®-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

Memories

• Up to 2 Mbytes of flash memory with readwhile-write support
• Up to 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), Up to 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
• Dual mode Quad-SPI memory interface running up to 133 MHz
• Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND flash memory clocked up to 100 MHz in Synchronous mode
• CRC calculation unit

Security

• ROP, PC-ROP, active tamper

General-purpose input/outputs

• Up to 168 I/O ports with interrupt capability

Reset and power management

• 3 separate power domains which can be independently clock-gated or switched off:
  • D1: high-performance capabilities

LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm) LQFP208 (28 x 28 mm)

TFBGA100 (8 x 8 mm)(1) TFBGA240+25 (14 x 14 mm)

UFBGA169 (7 x 7 mm) UFBGA176+25 (10 x 10 mm)

• D2: communication peripherals and timers
• D3: reset/clock control/power management
• 1.62 to 3.6 V application supply and I/Os
• POR, PDR, PVD and BOR
• Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
• Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
• Voltage scaling in Run and Stop mode (6 configurable ranges)
• Backup regulator (~0.9 V)
• Voltage reference for analog peripheral/VREF+
• Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging

Low-power consumption

• VBAT battery operating mode with charging capability
• CPU and domain power state monitoring pins
• 2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON)

Clock management

• Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
• External oscillators: 4-48 MHz HSE, 32.768 kHz LSE

• 3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode

Interconnect matrix

• 3 bus matrices (1 AXI and 2 AHB)
• Bridges (5× AHB2-APB, 2× AXI2-AHB)

4 DMA controllers to unload the CPU

• 1× high-speed master direct memory access controller (MDMA) with linked list support
• 2× dual-port DMAs with FIFO
• 1× basic DMA with request router capabilities

Up to 35 communication peripherals

• 4× I2Cs FM+ interfaces (SMBus/PMBus)
• 4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
• 6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz)
• 4x SAIs (serial audio interface)
• SPDIFRX interface
• SWPMI single-wire protocol master I/F
• MDIO Slave interface
• 2× SD/SDIO/MMC interfaces (up to 125 MHz)
• 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)
• 2× USB OTG interfaces (1FS, 1HS/FS) crystalless solution with LPM and BCD
• Ethernet MAC interface with DMA controller
• HDMI-CEC
• 8- to 14-bit camera interface (up to 80 MHz)

11 analog peripherals

• 3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS)
• 1× temperature sensor
• 2× 12-bit D/A converters (1 MHz)
• 2× ultra-low-power comparators
• 2× operational amplifiers (7.3 MHz bandwidth)
• 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters

Graphics

• LCD-TFT controller up to XGA resolution

• Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load
• Hardware JPEG Codec

Up to 22 timers and watchdogs

• 1× high-resolution timer (2.1 ns max resolution)
• 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz)
• 2× 16-bit advanced motor control timers (up to 240 MHz)
• 10× 16-bit general-purpose timers (up to 240 MHz)
• 5× 16-bit low-power timers (up to 240 MHz)
• 2× watchdogs (independent and window)
• 1× SysTick timer
• RTC with sub-second accuracy and hardware calendar

Debug mode

• SWD & JTAG interfaces
• 4-Kbyte embedded trace buffer

True random number generators (3 oscillators each)

96-bit unique ID

All packages are ECOPACK2 compliant Table 1. Device summary

Reference	Part number
STM32H742xI/G	STM32H742VI, STM32H742ZI, STM32H742II, STM32H742BI, STM32H742XI, STM32H742AI, STM32H742VG, STM32H742ZG, STM32H742IG, STM32H742BG, STM32H742XG, STM32H742AG
STM32H743xI/G	STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI, STM32H743AI, STM32H743VG, STM32H743ZG, STM32H743IG, STM32H743BG, STM32H743XG, STM32H743AG

Figure 5. LQFP100 pinout

Figure 6. TFBGA100 pinout

	1	2	3	4	5	6	7	8	9	10
A	PC14- OSC32_IN	PC13	PE2	PB9	PB7	PB4	PB3	PA15	PA14	PA13
B	PC15- OSC32_OUT	VBAT	PE3	PB8	PB6	PD5	PD2	PC11	PC10	PA12
C	PH0-OSC_IN	VSS	PE4	PE1	PB5	PD6	PD3	PC12	PA9	PA11
D	PH1- OSC_OUT	VDD	PE5	PE0	BOOT0	PD7	PD4	PD0	PA8	PA10
E	NRST	PC2_C	PE6	VSS	VSS	VSS	VCAP	PD1	PC9	PC7
F	PC0	PC1	PC3_C	VDDLDO	VDD	VDD33USB	PDR_ON	VCAP	PC8	PC6
G	VSSA	PA0	PA4	PC4	PB2	PE10	PE14	PD15	PD11	PB15
H	VDDA	PA1	PA5	PC5	PE7	PE11	PE15	PD14	PD10	PB14
J	VSS	PA2	PA6	PB0	PE8	PE12	PB10	PB13	PD9	PD13
K	VDD	PA3	PA7	PB1	PE9	PE13	PB11	PB12	PD8	PD12

Figure 8. UFBGA169 ballout

	1	2	3	4	5	6	7	8	9	10	11	12	13
A	PE4	PE2	VDD	PI6	PB6	PI2	VDD	PG10	PD5	VDD	PC12	PC10	PI0
B	PC15- OSC32_ OUT	PE3	VSS	VDDLDO	PB8	PB4	PI3	PG11	PD6	VSS	PC11	PA14	PI1
C	PC14- OSC32_ IN	PE6	PE5	PDR_ON	PB9	PB5	PG14	PG9	PD4	PD1	PA15	VSS	VDD
D	VDD	VSS	PC13	PE1	PE0	PB7	PG13	PD7	PD3	PD0	PA13	VDDLDO	VCAP
E	PI11	PI7	VBAT	PF1	PF3	BOOT0	PG15	PG12	PD2	PA10	PA9	PA8	PA12
F	PI13	PI12	PF0	PF2	PF5	PF7	PB3	PG4	PC6	PC7	PC9	PC8	PA11
G	VDD	VSS	PF4	PF6	PF9	NRST	PF13	PE7	PG6	PG7	PG8	VDD50_ USB	VDD33_ USB
H	PH0- OSC_ IN	PH1- OSC_ OUT	PF10	PF8	PJ1	PA4	PF14	PE8	PG2	PG3	PG5	VSS	VDD
J	PC0	PC1	VSSA	PJ0	PA0	PA7	PF15	PE9	PE14	PD11	PD13	PD15	PD14
K	PC3_C	PC2_C	PH4	PA1	PA6	PC4	PG0	PE13	PH10	PH12	PD9	PD10	PD12
L	VDDA	VREF+	PH5	PA5	PB1	PB2	PG1	PE12	PB10	PH11	PB13	VSS	VDD
M	VDD	VSS	PH3	VSS	PB0	PF11	VSS	PE10	PB11	VDDLDO	VSS	PD8	PB15
N	PA2	PH2	PA3	VDD	PC5	PF12	VDD	PE11	PE15	VCAP	VDD	PB12	PB14

Figure 9. LQFP176 pinout

Figure 10. UFBGA176+25 ballout

	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
A	PE3	PE2	PE1	PE0	PB8	PB5	PG14	PG13	PB4	PB3	PD7	PC12	PA15	PA14	PA13
B	PE4	PE5	PE6	PB9	PB7	PB6	PG15	PG12	PG11	PG10	PD6	PD0	PC11	PC10	PA12
C	VBAT	PI7	PI6	PI5	VDD	PDR_ON	VDD	VDD	VDD	PG9	PD5	PD1	PI3	PI2	PA11
D	PC13	PI8	PI9	PI4	VSS	BOOT0	VSS	VSS	VSS	PD4	PD3	PD2	PH15	PI1	PA10
E	PC14- OSC32_ IN	PF0	PI10	PI11								PH13	PH14	PI0	PA9
F	PC15- OSC32_ OUT	VSS	VDD	PH2		VSS	VSS	VSS	VSS	VSS		VSS	VCAP	PC9	PA8
G	PH0- OSC_IN	VSS	VDD	PH3		VSS	VSS	VSS	VSS	VSS		VSS	VDD	PC8	PC7
H	PH1- OSC_ OUT	PF2	PF1	PH4		VSS	VSS	VSS	VSS	VSS		VSS	VDD 3.3USB	PG8	PC6
J	NRST	PF3	PF4	PH5		VSS	VSS	VSS	VSS	VSS		VDD	VDD	PG7	PG6
K	PF7	PF6	PF5	VDD		VSS	VSS	VSS	VSS	VSS		PH12	PG5	PG4	PG3
L	PF10	PF9	PF8	VSS								PH11	PH10	PD15	PG2
M	VSSA	PC0	PC1	PC2_C	PC3_C	PB2	PG1	VSS	VSS	VCAP	PH6	PH8	PH9	PD14	PD13
N	VREF-	PA1	PA0	PA4	PC4	PF13	PG0	VDD	VDD	VDD	PE13	PH7	PD12	PD11	PD10
P	VREF+	PA2	PA6	PA5	PC5	PF12	PF15	PE8	PE9	PE11	PE14	PB12	PB13	PD9	PD8
R	VDDA	PA3	PA7	PB1	PB0	PF11	PF14	PE7	PE10	PE12	PE15	PB10	PB11	PB14	PB15

Figure 11. LQFP208 pinout

1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 VDD LDO VSS PB5 VCAP PG10 PD5 PC10 PA15 PI0 VSS PI6 PI4 PK5 PG9 PD4 PI1 PI5 PH14 VRΔT V99 DI7 DF1 PR6 1/99 PR/ PΚΛ PG11 D 115 PD6 PD3 PC11 ΡΔ1/ PI2 DH15 B VDD OSC32 OUT VSS OSC32 PE2 PE0 PB7 PR3 PK6 PK3 PG12 VSS PD7 PC12 VSS PI3 PA13 IN VCAP PE5 PE4 PE3 PB9 PB8 PG15 PK7 PG14 PG13 PJ14 PJ12 PD2 PD0 PA10 PA9 PH13 D PDR_ ON BOO T0 E NC⁽²⁾ PC13 VDD VDD PC9 PA8 PA11 VSS⁽³⁾ VSS⁽⁴⁾ PI10 F VDD50 VSS⁽⁴⁾ PF2 PF1 PF0 VSS VSS VDD PG5 PG6 VSS G USB PI12 PI13 PI14 VDD VSS VSS VSS VDD PK2 PF3 VSS VSS PG4 PG3 PG2 H PH0vss VSS vss vss vss VSS VSS PF5 PF4 VDD VSS PK0 PK1 OSC IN OUT VSS VSS VSS VSS VSS NC NRST PF6 PF7 PF8 VDD VDD PJ11 VSS NC VDDA PC0 PF10 PF9 VDD vss vss VDD PJ10 VSS NC NC L VREF+ NC M VREF-PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS NC Ν PF13 VDD VSSA PH3 PH4 PH5 PI15 P.I1 PF14 PF9 PB10 PR11 PH10 PH11 PD15 PD14 PE11 R PC2_C PD13 PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PA0 C PA1_C PA5 PC4 PR1 P.12 PF11 PG0 PF8 PF13 PH6 VSS PH8 PB12 PB15 PD10 PD9 VCAP VDD U VSS PA3 PA4 PC5 PB0 PJ3 PJ4 PG1 PE7 PE14 PH7 PB13 PB14 PD8 VSS LDO

Figure 12. TFBGA240+25 ballout

MSv41911V5

^1. The above figure shows the package top view.

^2. This ball should remain floating.

^3. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.

^4. This ball should be connected to VSS.

Table 8. Legend/abbreviations used in the pinout table

Name	Abbreviation	Definition
Pin name		Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
	S	Supply pin
	I	Input only pin
Pin type	I/O	Input / output pin
	ANA	Analog-only Input
	FT	5 V tolerant I/O
	TT	3.3 V tolerant I/O
	B	Dedicated BOOT0 pin
	RST	Bidirectional reset pin with embedded weak pull-up resistor
I/O structure		Option for TT and FT I/Os
	_f	I2C FM+ option
	_a	analog option (supplied by VDDA)
	_u	USB option (supplied by VDD33USB)
	_h	High-speed low-voltage I/O
Notes		Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.
Pin functions	Alternate functions	Functions selected through GPIOx_AFR registers
	Additional functions	Functions directly selected/enabled through peripheral registers

Table 9 and Table 10 to Table 20 show STM32H743xI/G pin/ball definition and alternate functions, respectively. Refer to Table 2 for the features and peripherals available on STM32H742xI/G devices.

Table 9. Pin/ball definition

LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25	LQFP176	LQFP208	TFBGA240 +25	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
1	A3	1	A2	A2	1	1	C3	PE2	I/O	FT_h	-	TRACECLK, SAI1_CK1, SPI4_SCK, SAI1_MCLK_A, SAI4_MCLK_A, QUADSPI_BK1_IO2, SAI4_CK1, ETH_MII_TXD3, FMC_A23, EVENTOUT	-
2	B3	2	B2	A1	2	2	D3	PE3	I/O	FT_h	-	TRACED0, TIM15_BKIN, SAI1_SD_B, SAI4_SD_B, FMC_A19, EVENTOUT	-
3	C3	3	A1	B1	3	3	D2	PE4	I/O	FT_h	-	TRACED1, SAI1_D2, DFSDM1_DATIN3, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, SAI4_FS_A, SAI4_D2, FMC_A20, DCMI_D4, LCD_B0, EVENTOUT	-
4	D3	4	C3	B2	4	4	D1	PE5	I/O	FT_h	-	TRACED2, SAI1_CK2, DFSDM1_CKIN3, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, SAI4_SCK_A, SAI4_CK2, FMC_A21, DCMI_D6, LCD_G0, EVENTOUT	-
5	E3	5	C2	B3	5	5	E5	PE6	I/O	FT_h	-	TRACED3, TIM1_BKIN2, SAI1_D1, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, SAI4_SD_A, SAI4_D1, SAI2_MCLK_B, TIM1_BKIN2_COMP12, FMC_A22, DCMI_D7, LCD_G1, EVENTOUT	-
-	-	-	M4	H10	-	-	A1	VSS	S	-	-	-	-
-	-	-	A3	-	-	-	-	VDD	S	-	-	-	-
6	B2	6	E3	C1	6	6	B1	VBAT	S	-	-	-	-
-	-	-	-	J6	-	-	B2	VSS	S	-	-	-	-
-	-	-	-	D2	7	7	E4	PI8	I/O	FT	-	EVENTOUT	RTC_TAMP2/ WKUP3
7	A2	7	D3	D1	8	8	E3	PC13	I/O	FT	-	EVENTOUT	RTC_TAMP1/ RTC_TS/ WKUP4
-	-	-	-	J7	-	-	B6	VSS	S	-	-	-	-

Table 9. Pin/ball definition (continued)

			Pin/ba	all nam	e			I/Dail Gell
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25	LQFP176	LQFP208	TFBGA240 +25	Pin name (function after reset)
8	A1	8	C1	E1	9	9	C2	PC14- OSC32_ IN (OSC32_ IN) (1)
9	B1	9	B1	F1	10	10	C1	PC15- OSC32_ OUT (OSC32_ OUT) (1)
-	-	-	-	D3	11	11	E2	PI9
-	-	-	-	E3	12	12	F3	PI10
-	-	1	E1	E4	13	13	F4	PI11
-	C2	-	D2	F2	14	14	A17	VSS
-	D2	-	D1	F3	15	15	E6	VDD
-	-	-	-	-	-	-	E1 (2)	NC
-	-	-	-	-	-	-	F1 (3)	VSS
-	-	-	-	-	-	-	G2 (4)	VSS
-	-	10	F3	E2	16	16	G4	PF0
-	-	11	E4	HЗ	17	17	G3	PF1
-	-	12	F4	H2	18	18	G1	PF2
-	-	-	F2	-	-	19	H1	PI12
-	-	1	F1	-	-	20	H2	PI13
-	-	-	-	-	-	21	HЗ	PI14
-	-	13	E5	J2	19	22	H4	PF3
-	-	14	G3	J3	20	23	J5	PF4

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	15	F5	K3
10	-	16	B10	G2
11	-	17	G1	G3
-	-	18	G4	K2
-	-	19	F6	K1
-	-	20	H4	L3
-	-	21	G5	L2
-	-	22	H3	L1
12	C1	23	H1	G1
13	D1	24	H2	H1
14	E1	25	G6	J1

Table 9. Pin/ball definition (continued)

			Pin/ba	all nam	e			n/ball dell		. (30
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25	LQFP176	LQFP208	TFBGA240 +25	Pin name (function after reset)	Pin type	I/O structure
15	F1	26	J1	M2	32	35	L2	PC0	I/O	FT_a
16	F2	27	J2	MЗ	33	36	M2	PC1	I/O	FT_ ha
-	1	-	-	-	-	-	M3 (5)	PC2	I/O	FT_a
17 (6)	E2 (6)	28 (6)	K2 (6)	M4 (6)	34 (6)	37 (6)	R1 (5)	PC2_C	ANA	TT_a
-	-	-	-	-	-	-	M4 (5)	PC3	I/O	FT_a
18 (6)	F3 (6)	29 (6)	K1 (6)	M5 (6)	35 (6)	38 (6)	R2 (5)	PC3_C	ANA	TT_a
-	F5	30	-	G3	36	39	E11	VDD	S	-
-	E6	-	B3	J10	-	-	C13	VSS	S	-
19	G1	31	J3	M1	37	40	P1	VSSA	S	-
-	- (7)	-	-	N1	-	-	N1	VREF-	S	-
20	_(7)	32	L2	P1	38	41	M1	VREF+	S	-
21	H1	33	L1	R1	39	42	L1	VDDA	S	-

Table 9. Pin/ball definition (continued)

			Pin/hs	all nam	Δ	1001	.	n/baii deti				aca,
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25	LQFP176	LQFP208	TFBGA240 +25	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions
22	G2	34	J5	N3	40	43	N5 (5)	PA0	I/O	FT_a	-	TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR,
-	1	1	-	-	-	-	T1 (5)	PA0_C	ANA	TT_a	1	TIM15_BKIN, USART2_CTS/USART2_ NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, ETH_MII_CRS, EVENTOUT
23	H2	35	K4	N2	41	44	N4 (5)	PA1	I/O	FT_ ha	1	TIM2_CH2, TIM5_CH2, LPTIM3_OUT,
-	1	1	-	-	-	-	T2 (5)	PA1_C	ANA	TT_a	1	TIM15_CH1N, USART2_RTS/USART2_ DE, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCLK_B, ETH_MII_RX_CLK/ETH_ RMII_REF_CLK, LCD_R2, EVENTOUT
24	J2	36	N1	P2	42	45	N3	PA2	I/O	FT_a	-	TIM2_CH3, TIM5_CH3, LPTIM4_OUT, TIM15_CH1, USART2_TX, SAI2_SCK_B, ETH_MDIO, MDIOS_MDIO, LCD_R1, EVENTOUT
-	1	1	N2	F4	43	46	N2	PH2	I/O	FT_ ha	1	LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, ETH_MII_CRS, FMC_SDCKE0, LCD_R0, EVENTOUT
-	K1	ı	M1	-	-	-	F5	VDD	S	-	1	-
-	J1	-	M7	J8	-	-	C16	VSS	S	-	-
-	-	-	M3	G4	44	47	P2	PH3	I/O	FT_ ha	-	QUADSPI_BK2_IO1, SAI2_MCLK_B, ETH_MII_COL, FMC_SDNE0, LCD_R1, EVENTOUT
-	-	-	K3	H4	45	48	P3	PH4	I/O	FT_fa	-	I2C2_SCL, LCD_G5, OTG_HS_ULPI_NXT, LCD_G4, EVENTOUT
-	-	-	L3	J4	46	49	P4	PH5	I/O	FT_fa	-	I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
25	K2	37	N3	R2
26	-	38	G2	K6
-	-	-	-	L4
27	-	39	-	K4
28	G3	40	H6	N4
29	H3	41	L4	P4
30	J3	42	K5	P3
31	K3	43	J6	R3

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
32	G4	44	K6	N5
33	H4	45	N5	P5
-	-	-	N4	-
-	-	-	H12	J9
34	J4	46	M5	R5
35	K4	47	L5	R4
36	G5	48	L6	M6
-	-	-	-	-
-	-	-	J4	-
-	-	-	H5	-
-	-	-	-	-

Table 9. Pin/ball definition (continued)

			Pin/ba	all nam	e			ii/Daii deii
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25	LQFP176	LQFP208	TFBGA240 +25	Pin name (function after reset)
-	-	-	-	-	-	68	U6	PJ3
-	-	-	-	-	-	69	U7	PJ4
-	ı	49	M6	R6	59	70	T7	PF11
-	-	50	N6	P6	60	71	R7	PF12
-	-	51	M11	M8	61	72	J3	VSS
-	-	52	-	N8	62	73	H5	VDD
-	-	53	G7	N6	63	74	P7	PF13
-	-	54	H7	R7	64	75	P8	PF14
-	- 1	55	J7	P7	65	76	R9	PF15
-	-	56	K7	N7	66	77	T8	PG0
-	-	-	M2	F6	-	-	J16	VSS
-	-	-	A10	-	-	-	H13	VDD
-	-	57	L7	M7	67	78	U8	PG1
37	H5	58	G8	R8	68	79	U9	PE7
38	J5	59	H8	P8	69	80	T9	PE8
39	K5	60	J8	P9	70	81	P9	PE9

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	61	C12	M9
-	-	62	C13	N9
40	G6	63	M8	R9
41	H6	64	N8	P10
42	J6	65	L8	R10
43	K6	66	K8	N11
-	-	-	L12	F7
-	-	-	H13	-
44	G7	67	J9	P11
45	H7	68	N9	R11

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
46	J7	69	L9	R12
47	K7	70	M9	R13
48	F8	71	N10	M10
49	E4	-	-	K7
-	-	-	M10	-
50	-	72	M1	N10
-	-	-	-	-
-	-	-	-	M11
-	-	-	-	N12
-	-	-	-	M12
-	-	-	-	F8
-	-	-	L13	-

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	-	-	M13
-	-	-	K9	L13
-	-	-	L10	L12
-	-	-	K10	K12
-	-	-	-	H12
-	-	-	N11	J12
51	K8	73	N12	P12
52	J8	74	L11	P13

Table 9. Pin/ball definition (continued)

LQFP100	TFBGA100	LQFP144	UFBGA169	Pin/ball name UFBGA176+25	LQFP176	LQFP208	TFBGA240 +25	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
53	H10	75	N13	R14	94	106	U15	PB14	I/O	FT_u	-	TIM1_CH2N, TIM12_CH1, TIM8_CH2N, USART1_TX, SPI2_MISO/I2S2_SDI, DFSDM1_DATIN2, USART3_RTS/ USART3_DE, UART4_RTS/UART4_DE , SDMMC2_D0, OTG_HS_DM, EVENTOUT	-
54	G10	76	M13	R15	95	107	T15	PB15	I/O	FT_u	-	RTC_REFIN, TIM1_CH3N, TIM12_CH2, TIM8_CH3N, USART1_RX, SPI2_MOSI/I2S2_SDO, DFSDM1_CKIN2, UART4_CTS, SDMMC2_D1, OTG_HS_DP, EVENTOUT	-
55	K9	77	M12	P15	96	108	U16	PD8	I/O	FT_h	-	DFSDM1_CKIN3, SAI3_SCK_B, USART3_TX, SPDIFRX1_IN2, FMC_D13/FMC_DA13, EVENTOUT	-
56	J9	78	K11	P14	97	109	T17	PD9	I/O	FT_h	-	DFSDM1_DATIN3, SAI3_SD_B, USART3_RX, FMC_D14/FMC_DA14, EVENTOUT	-
57	H9	79	K12	N15	98	110	T16	PD10	I/O	FT_h	-	DFSDM1_CKOUT, SAI3_FS_B, USART3_CK, FMC_D15/FMC_DA15, LCD_B3, EVENTOUT	-
-	-	-	N7	-	-	-	N12	VDD	S	-	-	-	-
-	-	-	-	F9	-	-	U17	VSS	S	-	-	-	-

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
58	G9	80	J10	N14
59	K10	81	K13	N13
60	J10	82	J11	M15
-	-	83	-	K8
-	-	84	-	J13
61	H8	85	J13	M14
62	G8	86	J12	L14
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	-	-	F10
-	-	-	-	-
-	-	-	-	-

Table 9. Pin/ball definition (continued)

• EVENTOUT
• TIM1_CH1, TIM8_CH3N,
  -
  -
  -
  -
  -
  -
  127
  J15
  PK1
  I/O
  FT
  -
  SPI5_NSS, LCD_G6,
  EVENTOUT
• TIM1_BKIN, TIM8_BKIN,
  TIM8_BKIN_COMP12,
  -
  -
  -
  -
  -
  -
  128
  H17
  PK2
  I/O
  FT
  -
  TIM1_BKIN_COMP12,
  LCD_G7, EVENTOUT
• TIM8_BKIN,
  -
  -
  87
  H9
  L15
  106
  129
  H16
  PG2
  I/O
  FT_h
  -
  TIM8_BKIN_COMP12,
  FMC_A12, EVENTOUT
• TIM8_BKIN2,
  -
  -
  88
  H10
  K15
  107
  130
  H15
  PG3
  I/O
  FT_h
  -
  TIM8_BKIN2_COMP12,
  FMC_A13, EVENTOUT
• -
  -
  -
  -
  G7
  -
  -
  -
  VSS
  S
  -
  -
  -

Table 9. Pin/ball definition (continued)

								Table 9. Pin/ball definition (continued)
				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25	LQFP176	LQFP208	TFBGA240 +25	Pin name (function after reset)
-	-	-	-	-	-	-	N7	VDD
-	-	89	F8	K14	108	131	H14	PG4
-	-	90	H11	K13	109	132	G14	PG5
-	-	91	G9	J15	110	133	G15	PG6
-	-	92	G10	J14	111	134	F16	PG7
-	-	93	G11	H14	112	135	F15	PG8
-	-	94	-	G12	113	136	G16	VSS
-	-	-	G12	-	-	-	G17	VDD50 USB(10)
-	F6	95	G13	H13	114	137	F17	VDD33 USB
-	-	-	-	-	-	-	M5	VDD
63	F10	96	F9	H15	115	138	F14	PC6

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
64	E10	97	F10	G15
65	F9	98	F12	G14
66	E9	99	F11	F14
-	-	-	-	G8
-	-	-	-	-
67	D9	100	E12	F15
68	C9	101	E11	E15

Table 9. Pin/ball definition (continued)

				Pin/ball name				Table 9. Pin/ball definition (continued)
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25	LQFP176	LQFP208	TFBGA240 +25	Pin name (function after reset)
69	D10	102	E10	D15	121	144	D14	PA10
70	C10	103	F13	C15	122	145	E17	PA11
71	B10	104	E13	B15	123	146	E16	PA12
72	A10	105	D11	A15	124	147	C15	PA13 (JTMS/SW DIO)
73	E7	106	D13	F13	125	148	D17	VCAP
74	E5	107	-	F12	126	149	-	VSS VDDLDO
-	-	-	D12	-	-	-	C17	(8)
75	-	108	-	G13	127	150	K5	VDD
-	-	-	-	E12	128	151	D16	PH13
-	-	-	-	E13	129	152	B17	PH14

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	-	-	D13
-	-	-	A13	E14
-	-	-	-	G9
-	-	-	B13	D14
-	-	-	A6	C14
-	-	-	B7	C13
-	-	-	-	D9
-	-	-	-	C9
76	A9	109	B12	A14
77	A8	110	C11	A13
78	B9	111	A12	B14

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
79	B8	112	B11	B13
80	C8	113	A11	A12
-	-	-	-	G10
81	D8	114	D10	B12
82	E8	115	C10	C12
83	B7	116	E9	D12
84	C7	117	D9	D11
85	D7	118	C9	D10
86	B6	119	A9	C11

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	120	-	D8
-	-	121	-	C8
87	C6	122	B9	B11
88	D6	123	D8	A11
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	-	-	H6
-	-	-	A7	-
-	-	124	C8	C10
-	-	125	A8	B10

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	126	B8	B9
-	-	127	E8	B8
-	-	128	D7	A8
-	-	129	C7	A7
-	-	130	-	D7
-	-	131	-	C7
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	-	-	-
-	-	-	-	H7

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
-	-	132	E7	B7
89	A7	133	F7	A10
90	A6	134	B6	A9
91	C5	135	C6	A6
-	-	-	-	H8
92	B5	136	A5	B6

Table 9. Pin/ball definition (continued)

				Pin/ball name
LQFP100	TFBGA100	LQFP144	UFBGA169	UFBGA176+25
93	A5	137	D6	B5
94	D5	138	E6	D6
95	B4	139	B5	A5
96	A4	140	C5	B4
97	D4	141	D5	A4
98	C4	142	D4	A3
-	-	-	-	-
99	-	-	-	D5

• TIM8_BKIN,
  SAI2_MCLK_A,
  -
  -
  -
  -
  D4
  173
  205
  A4
  PI4
  I/O
  FT_h
  -
  TIM8_BKIN_COMP12,
  -
  FMC_NBL2, DCMI_D5,
  LCD_B4, EVENTOUT
• TIM8_CH1,
  SAI2_SCK_A,
  -
  -
  -
  -
  C4
  174
  206
  A3
  PI5
  I/O
  FT_h
  -
  FMC_NBL3,
  -
  DCMI_VSYNC, LCD_B5,
  EVENTOUT
• TIM8_CH2, SAI2_SD_A,
  -
  -
  -
  A4
  C3
  175
  207
  A2
  PI6
  I/O
  FT_h
  -
  FMC_D28, DCMI_D6,
  -
  LCD_B6, EVENTOUT
• TIM8_CH3, SAI2_FS_A,
  -
  -
  -
  E2
  C2
  176
  208
  B3
  PI7
  I/O
  FT_h
  -
  FMC_D29, DCMI_D7,
  -
  LCD_B7, EVENTOUT
• -
  -
  -
  -
  H9
  -
  -
  -
  VSS
  S
  -
  -
  -
  -
• -
  -
  -
  -
  K9
  -
  -
  -
  VSS
  S
  -
  -
  -
  -
• -
  -
  -
  -
  K10
  -
  -
  M15
  VSS
  S
  -
  -
  -
  -

Table 9. Pin/ball definition (continued)

• 1. When this pin/ball was previously configured as an oscillator, the oscillator function is kept during and after a reset. This is valid for all resets except for power-on reset.
• 2. This ball should remain floating.
• 1. This ball should not remain floating. It can be connected to VSS or VDD. It is reserved for future use.
• 4. This ball should be connected to VSS.
• 5. Pxy_C and Pxy pins/balls are two separate pads (analog switch open). The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits.
• 6. There is a direct path between Pxy_C and Pxy pins/balls, through an analog switch. Pxy alternate functions are available on Pxy_C when the analog switch is closed. The analog switch is configured through a SYSCFG register. Refer to the product reference manual for a detailed description of the switch configuration bits.
• 1. VREF+ pin, and consequently the internal voltage reference, are not available on the TFBGA100 package. On this package, this pin is double-bonded to VDDA which can be connected to an external reference. The internal voltage reference buffer is not available and must be kept disabled
• 8. When it is not available on a package, the VDDLDO pin is internally tied to VDD.
• 9. When the pin is used in USB configuration (OTG_HS_ID/OTG_HS_VBUS), the I/O is supplied by VDD33USB, otherwise it is supplied by VDD.
• 1. When it is not available on a package, the VDD50USB pin is internally tied to VDD33USB.

Pin descriptions

Г				1	1							1			l		1
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
	Port	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4/ 5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1/ 3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1	SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD	I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM1/ SDMMC2/ MDIOS/ ETH	TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD	TIM1/DCMI /LCD/ COMP	UART5/ LCD	SYS
	PA0	1	TIM2_CH1/ TIM2_ETR	TIM5_CH1	TIM8_ETR	TIM15_BKIN	-	1	USART2_ CTS/ USART2_ NSS	UART4_TX	SDMMC2_ CMD	SAI2_SD_B	ETH_MII_ CRS	-	-	,	EVENT- OUT
	PA1	ı	TIM2_CH2	TIM5_CH2	LPTIM3_ OUT	TIM15_ CH1N	1	ı	USART2_ RTS/ USART2_ DE	UART4_RX	QUADSPI_ BK1_IO3	SAI2_MCLK _B	ETH_MII_ RX_CLK/ ETH_RMII_ REF_CLK	-	-	LCD_R2	EVENT- OUT
	PA2	-	TIM2_CH3	TIM5_CH3	LPTIM4_ OUT	TIM15_CH1	-	-	USART2_ TX	SAI2_SCK_ B	-	-	ETH_MDIO	MDIOS_ MDIO	-	LCD_R1	EVENT- OUT
	PA3	-	TIM2_CH4	TIM5_CH4	LPTIM5_ OUT	TIM15_CH2	-	-	USART2_ RX	-	LCD_B2	OTG_HS_ ULPI_D0	ETH_MII_ COL	-	-	LCD_B5	EVENT- OUT
	PA4	D1 PWREN	-	TIM5_ETR	-	-	SPI1_NSS/ I2S1_WS	SPI3_NSS/ I2S3_WS	USART2_ CK	SPI6_NSS	-	-	-	OTG_HS_ SOF	DCMI_ HSYNC	LCD_ VSYNC	EVENT- OUT
	PA5	D2 PWREN	TIM2_CH1/ TIM2_ETR	-	TIM8_ CH1N	-	SPI1_SCK /I2S1_CK	-	-	SPI6_SCK	-	OTG_HS_ ULPI_CK	-	-	-	LCD_R4	EVENT- OUT
Port A	PA6	-	TIM1_BKIN	TIM3_CH1	TIM8_BKIN	-	SPI1_MISO /I2S1_SDI	-	-	SPI6_MISO	TIM13_ CH1	TIM8_BKIN _COMP12	MDIOS_ MDC	TIM1_BKIN _COMP12	DCMI_PIX CLK	LCD_G2	EVENT- OUT
Ğ	PA7	-	TIM1_CH1N	TIM3_CH2	TIM8_CH1 N	-	SPI1_MOSI /I2S1_SDO	-	-	SPI6_MOSI	TIM14_ CH1	-	ETH_MII_ RX_DV/ ETH_RMII_ CRS_DV	FMC_SDN WE	-	-	EVENT- OUT
	PA8	MCO1	TIM1_CH1	HRTIM_CH B2	TIM8_BKIN 2	I2C3_SCL	-	=	USART1_ CK	-	-	OTG_FS_ SOF	UART7_RX	TIM8_BKIN 2_COMP12	LCD_B3	LCD_R6	EVENT- OUT
	PA9	-	TIM1_CH2	HRTIM_CH C1	LPUART1_ TX	I2C3_SMBA	SPI2_SCK/ I2S2_CK	-	USART1_ TX	-	-	-	-	-	DCMI_D0	LCD_R5	EVENT- OUT
	PA10	-	TIM1_CH3	HRTIM_CH C2	LPUART1_ RX	-	-	-	USART1_ RX	-	-	OTG_FS_ID	MDIOS_ MDIO	LCD_B4	DCMI_D1	LCD_B1	EVENT- OUT
	PA11	-	TIM1_CH4	HRTIM_CH D1	LPUART1_ CTS	-	SPI2_NSS /I2S2_WS	UART4_RX	USART1_ CTS/ USART1_ NSS	-	FDCAN1_ RX	OTG_FS_ DM	-	-	-	LCD_R4	EVENT- OUT
	PA12	-	TIM1_ETR	HRTIM_CH D2	LPUART1_ RTS/ LPUART1_ DE	-	SPI2_SCK/ I2S2_CK	UART4_TX	USART1_ RTS/ USART1_ DE	SAI2_FS_B	FDCAN1_ TX	OTG_FS_ DP	-	-	-	LCD_R5	EVENT- OUT

Table 10. Port A alternate functions (continued)

	Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
		SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4/ 5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1/ 3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1	SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD	I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM1/ SDMMC2/ MDIOS/ ETH	TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD	TIM1/DCMI/ LCD/ COMP	UART5/ LCD	SYS
	PA0	-	TIM2_CH1/ TIM2_ETR	TIM5_CH1	TIM8_ETR	TIM15_BKIN	-	-	USART2_CTS/ USART2_NSS	UART4_TX	SDMMC2_CMD	SAI2_SD_B	ETH_MII_CRS	-	-	-	EVENT- OUT
	PA1	-	TIM2_CH2	TIM5_CH2	LPTIM3_OUT	TIM15_CH1N	-	-	USART2_RTS/ USART2_DE	UART4_RX	QUADSPI_BK1_IO3	SAI2_MCLK_B	ETH_MII_RX_CLK/ ETH_RMII_REF_CLK	-	-	LCD_R2	EVENT- OUT
	PA2	-	TIM2_CH3	TIM5_CH3	LPTIM4_OUT	TIM15_CH1	-	-	USART2_TX	SAI2_SCK_B	-	-	ETH_MDIO	MDIOS_MDIO	-	LCD_R1	EVENT- OUT
	PA3

Table 11. Port B alternate functions

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
	Port	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/5/ 6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/3 /6/UART7/S DMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1	SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD	I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM1/ SDMMC2/ MDIOS/ ETH	TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD	TIM1/ DCMI/LCD /COMP	UART5/ LCD	SYS
	PB0	-	TIM1_CH2N	TIM3_CH3	TIM8_ CH2N	-	-	DFSDM1_ CKOUT	-	UART4_ CTS	LCD_R3	OTG_HS_ ULPI_D1	ETH_MII_ RXD2	-	-	LCD_G1	EVENT- OUT
	PB1	-	TIM1_CH3N	TIM3_CH4	TIM8_ CH3N	1	1	DFSDM1_ DATIN1	1	1	LCD_R6	OTG_HS_ ULPI_D2	ETH_MII_ RXD3	-	-	LCD_G0	EVENT- OUT
	PB2	RTC_OUT	-	SAI1_D1	-	DFSDM1_ CKIN1	-	SAI1_SD_A	SPI3_ MOSI/I2S3_ SDO	SAI4_SD_ A	QUADSPI_ CLK	SAI4_D1	-	-	ı	-	EVENT- OUT
1	PB3	JTDO/TRA CESWO	TIM2_CH2	HRTIM_ FLT4	-	-	SPI1_SCK/ I2S1_CK	SPI3_SCK/ I2S3_CK	-	SPI6_SCK	SDMMC2_ D2	CRS_SYNC	UART7_RX	-	-	-	EVENT- OUT
Ċ	PB4	NJTRST	TIM16_ BKIN	TIM3_CH1	HRTIM_ EEV6	-	SPI1_MISO/ I2S1_SDI	SPI3_MISO/ I2S3_SDI	SPI2_NSS/I 2S2_WS	SPI6_ MISO	SDMMC2_ D3	-	UART7_TX	-	-	1	EVENT- OUT
	PB5	-	TIM17_ BKIN	TIM3_CH2	HRTIM_ EEV7	I2C1_SMBA	SPI1_MOSI/ I2S1_SDO	I2C4_SMBA	SPI3_MOSI/ I2S3_SDO	SPI6_ MOSI	FDCAN2_ RX	OTG_HS_ ULPI_D7	ETH_PPS_ OUT	FMC_ SDCKE1	DCMI_ D10	UART5_ RX	EVENT- OUT
	PB6	-	TIM16_ CH1N	TIM4_CH1	HRTIM_ EEV8	I2C1_SCL	CEC	I2C4_SCL	USART1_ TX	LPUART1_ TX	FDCAN2_ TX	QUADSPI_ BK1_NCS	DFSDM1_ DATIN5	FMC_ SDNE1	DCMI_D5	UART5_ TX	EVENT- OUT
	PB7	-	TIM17_ CH1N	TIM4_CH2	HRTIM_ EEV9	I2C1_SDA	-	I2C4_SDA	USART1_ RX	LPUART1_ RX	-	-	DFSDM1_ CKIN5	FMC_NL	DCMI_ VSYNC	-	EVENT- OUT

Pin descriptions

Tabl	e 11. Por	t B alteri	nate fund	ctions (c	ontinue	d)
AF4	AF5	AF6	AF7	AF8	AF9 SAI4/	AF10 CAIDIAI
		AF0	AF1	AF2	AF3	AF4
---	------	---------------	------------------------------------	---------------------------------	--------------------------------------------------------	---------------------------------------------------------------
	Port	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC
	PB8	-	TIM16_CH1	TIM4_CH3	DFSDM1_ CKIN7	I2C1_SCL
	PB9	-	TIM17_CH1	TIM4_CH4	DFSDM1_ DATIN7	I2C1_SDA
	PB10	-	TIM2_CH3	HRTIM_ SCOUT	LPTIM2_IN 1	I2C2_SCL
	PB11	-	TIM2_CH4	HRTIM_ SCIN	LPTIM2_ ETR	I2C2_SDA
a	PB12	-	TIM1_BKIN	-	-	I2C2_SMBA
	PB13	-	TIM1_CH1N	-	LPTIM2_ OUT	-
	PB14	-	TIM1_CH2N	TIM12_ CH1	TIM8_ CH2N	USART1_TX
	PB15	RTC_ REFIN	TIM1_CH3N	TIM12_ CH2	TIM8_ CH3N	USART1_RX

Table 12. Port C alternate functions

	-
	AF0
Port	SYS
PC	0 -
PC	1 TRACED0
PC	2 CDSLEEP
PC	3 CSLEEP
PC	4 -
PC	5 -
Port C	6 -
PC	7 TRGIO
PC	8 TRACED1
PC	9 MCO2
PC	-
PC	11 -
PC	12 TRACED3
PC	13 -

Table 12. Port C alt	ernate functions	(continued)
----------------------	------------------	-------------

| | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | AF8 | AF9 | AF10 | AF11 | AF12 | AF13 | AF14 | AF15 | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | | Port | SYS | TIM1/2/16/
17/LPTIM1/
HRTIM1 | SAI1/TIM3/
4/5/12/
HRTIM1 | LPUART/
TIM8/
L

Table 13. Port D alternate functions

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
	Port	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1	SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD	I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM1/ SDMMC2/ MDIOS/ ETH	TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD	TIM1/DCMI /LCD/ COMP	UART5/ LCD	SYS
	PD0	-	-	-	DFSDM1_ CKIN6	-	-	SAI3_SCK_ A	-	UART4_RX	FDCAN1_ RX	-	-	FMC_D2/ FMC_DA2	-	-	EVENT- OUT
	PD1	-	-	-	DFSDM1_ DATIN6	-	-	SAI3_SD_A	-	UART4_TX	FDCAN1_ TX	-	-	FMC_D3/ FMC_DA3	-	-	EVENT- OUT
	PD2	TRACED2	-	TIM3_ETR	-	-	-	-	-	UART5_RX	-	-	-	SDMMC1_ CMD	DCMI_D11	-	EVENT- OUT
	PD3	-	-	-	DFSDM1_ CKOUT	-	SPI2_SCK/ I2S2_CK	-	USART2_ CTS/ USART2_ NSS	-	-	-	-	FMC_CLK	DCMI_D5	LCD_G7	EVENT- OUT
1	PD4	-	-	HRTIM_ FLT3	-	-	-	SAI3_FS_A	USART2_ RTS/ USART2_ DE	-	-	-	-	FMC_NOE	-	-	EVENT- OUT
	PD5	-	-	HRTIM_ EEV3	-	-	-	-	USART2_ TX	-	-	-	-	FMC_NWE	-	-	EVENT- OUT
	PD6	-	-	SAI1_D1	DFSDM1_ CKIN4	DFSDM1_ DATIN1	SPI3_ MOSI/I2S3 _SDO	SAI1_SD_A	USART2_ RX	SAI4_SD_ A	-	SAI4_D1	SDMMC2_ CK	FMC_ NWAIT	DCMI_D10	LCD_B2	EVENT- OUT
	PD7	-	-	-	DFSDM1_ DATIN4	-	SPI1_ MOSI/I2S1 _SDO	DFSDM1_ CKIN1	USART2_ CK	-	SPDIFRX1_ IN1	-	SDMMC2_ CMD	FMC_NE1	-	-	EVENT- OUT

Table 13. Port D alternate functions (continued)

						iabi	e 13. 1 U	rt D aiter	mate rui	ictions (	Continue	·u)
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10
	Port	sys	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1	SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD
	PD8	-	-	1	DFSDM1_ CKIN3	-	-	SAI3_SCK_ B	USART3_ TX	-	SPDIFRX1_ IN2	-
	PD9	-	-	-	DFSDM1_ DATIN3	-	-	SAI3_SD_B	USART3_ RX	-	-	-
	PD10	-	-	-	DFSDM1_ CKOUT	-	-	SAI3_FS_B	USART3_ CK	-	-	-
	PD11	-	-	-	LPTIM2_ IN2	I2C4_SMBA	-	-	USART3_ CTS/ USART3_N SS	-	QUADSPI_ BK1_IO0	SAI2_SD_A
Port	PD12	-	LPTIM1_IN1	TIM4_CH1	LPTIM2_ IN1	I2C4_SCL	-	-	USART3_ RTS/ USART3_ DE	-	QUADSPI_ BK1_IO1	SAI2_FS_A
	PD13	-	LPTIM1_ OUT	TIM4_CH2	-	I2C4_SDA	-	-		-	QUADSPI_ BK1_IO3	SAI2_SCK_ A
	PD14	-	-	TIM4_CH3	-	-	-	SAI3_MCLK _B	-	UART8_ CTS	-	-
	PD15	-	-	TIM4_CH4	-	-	-	SAI3_MCLK _A	-	UART8_ RTS/ UART8_ DE	-	-

							Table 1	4. Port E	alterna	te functi	ions
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9
	Port	SYS	TIM1/2/16/1 7/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	SAI4/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1
	PE0	-	LPTIM1_ ETR	TIM4_ETR	HRTIM_ SCIN	LPTIM2_ ETR	-	-	-	UART8_RX	-
	PE1	-	LPTIM1_IN2	-	HRTIM_ SCOUT	-	-	-	-	UART8_TX	-
	PE2	TRACE CLK	-	SAI1_CK1	-	-	SPI4_SCK	SAI1_MCLK _A	-	SAI4_ MCLK_A	QUADSPI_ BK1_IO2
	PE3	TRACED0	-	-	-	TIM15_BKIN	-	SAI1_SD_B	-	SAI4_SD_ B	-
	PE4	TRACED1	-	SAI1_D2	DFSDM1_ DATIN3	TIM15_CH1 N	SPI4_NSS	SAI1_FS_A	-	SAI4_FS_A	-
	PE5	TRACED2	-	SAI1_CK2	DFSDM1_ CKIN3	TIM15_CH1	SPI4_ MISO	SAI1_SCK_ A	-	SAI4_SCK _A	-
	PE6	TRACED3	TIM1_ BKIN2	SAI1_D1	-	TIM15_CH2	SPI4_ MOSI	SAI1_SD_A	-	SAI4_SD_ A	SAI4_D1
	PE7	-	TIM1_ETR	-	DFSDM1_ DATIN2	-	-	-	UART7_RX	-	-
Port E	PE8	-	TIM1_CH1N	-	DFSDM1_ CKIN2	-	-	-	UART7_TX	-	-
	PE9	-	TIM1_CH1	-	DFSDM1_ CKOUT	-	-	-	UART7_ RTS/ UART7_ DE	-	-
	PE10	-	TIM1_CH2N	-	DFSDM1_ DATIN4	-	-	-	UART7_ CTS	-	-
	PE11	-	TIM1_CH2	-	DFSDM1_ CKIN4	-	SPI4_NSS	-	-	-	-
	PE12	-	TIM1_CH3N	-	DFSDM1_ DATIN5	-	SPI4_SCK	-	-	-	-
	PE13	-	TIM1_CH3	-	DFSDM1_ CKIN5	-	SPI4_ MISO	-	-	-	-
	PE14	-	TIM1_CH4	-	-	-	SPI4_ MOSI	-	-	-	-
	PE15	-	TIM1_BKIN	-	-	-	-	-	-	-	-

Table 15. Port F alternate functions

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
Port	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	SAI4/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1	SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD	I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM1/ SDMMC2/ MDIOS/ ETH	TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD	TIM1/DCMI /LCD/ COMP	UART5/ LCD	SYS
PF0	-	-	-	-	I2C2_SDA	-	-	-	-	-	-	-	FMC_A0	-	-	EVENT- OUT
PF1	-	-	-	-	I2C2_SCL	-	-	-	-	-	-	-	FMC_A1	-	-	EVENT- OUT
PF2	-	-	-	-	I2C2_SMBA	-	-	-	-	-	-	-	FMC_A2	-	-	EVENT- OUT
PF3	-	-	-	-	-	-	-	-	-	-	-	-	FMC_A3	-	-	EVENT- OUT
PF4	-	-	-	-	-	-	-	-	-	-	-	-	FMC_A4	-	-	EVENT- OUT
PF5	-	-	-	-	-	-	-	-	-	-	-	-	FMC_A5	-	-	EVENT- OUT
PF6	-	TIM16_CH1	-	-	-	SPI5_NSS	SAI1_SD_B	UART7_RX	SAI4_SD_ B	QUADSPI_ BK1_IO3	-	-	-	-	-	EVENT- OUT
PF7	-	TIM17_CH1	-	-	-	SPI5_SCK	SAI1_MCLK _B	UART7_TX	SAI4_ MCLK_B	QUADSPI_ BK1_IO2	-	-	-	-	-	EVENT- OUT
PF8	-

LCD_ B1

LCD_ R0

EVENT -OUT

EVENT -OUT

Pin descriptions

									ate func
	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8
ort	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1
PG0	-	-	-	-	-	-	-	-	-
PG1	-	1	-	-	-	-	-	-	-
PG2	-	-	-	TIM8_BKIN	-	-	-	-	-
PG3	-	-	-	TIM8_ BKIN2	-	-	-	-	-
PG4	-	TIM1_ BKIN2	-	-	-	-	-	-	-
PG5	-	TIM1_ETR	-	-	-	-	-	-	-
PG6	-	TIM17_ BKIN	HRTIM_ CHE1	-	-	-	-	-	-
PG7	-	-	HRTIM_ CHE2	-	-	-	SAI1_ MCLK_A	USART6_ CK	-
PG8	-	-	-	TIM8_ETR	-	SPI6_NSS	-	USART6_ RTS/ USART6_ DE	SPDIFRX1 _IN3
PG9	-	ī	ī	-	-	SPI1_ MISO/I2S1 _SDI	=	USART6_ RX	SPDIFRX1 _IN4
G10	-	-	HRTIM_ FLT5	-	-	SPI1_NSS/ I2S1_WS	-	-	-
PG11	-	LPTIM1_IN2	HRTIM_ EEV4	-	-	SPI1_SCK/ I2S1_CK	-	-	SPDIFRX1 _IN1
	PG0 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10	SYS PG0 - PG0 - PG1 - PG2 - PG3 - PG3 - PG6 - PG6 - PG7 - PG8 - PG9 - G10 -	SYS 17/LPTIM1/ HRTIM1 PG0	SYS 17/LPTIM1/ 4/5/12/ HRTIM1 4/5/12/ HRTIM1 4/5/12/ HRTIM1 PG0	SYS	SYS	SYS	SYS	SYS

USART6_ RTS/ USART6_

DE

USART6_ CTS/ USART6_ NSS

SPDIFRX1 _IN2

LCD_B4

ETH_MII_ TXD1/ETH_ RMII_TXD1

ETH_MII_ TXD0/ETH_ RMII_TXD0

FMC_NE4

FMC_A24

SPI6_ MISO

SPI6_SCK

HRTIM_ EEV5

HRTIM_ EEV10

LPTIM1_IN1

LPTIM1_ OUT

PG12

PG13 TRACED0

Table 16. Port G alternate functions (continued)

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
Port	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ L
Port	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM

Pin descriptions

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
	Port	sys	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	SAI4/ FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1	SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD	I2C4/ UART7/ SWPMI1/ TIM1/8/ DFSDM1/ SDMMC2/ MDIOS/ ETH	TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD	TIM1/DCMI /LCD/ COMP	UART5/ LCD	SYS
	PH0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	EVENT- OUT
	PH1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	EVENT- OUT
	PH2	-	LPTIM1_IN2	-	-	-	-	-	-	-	QUADSPI_ BK2_IO0	SAI2_SCK_ B	ETH_MII_ CRS	FMC_ SDCKE0	-	LCD_R0	EVENT- OUT
	PH3	-	-	-	-	-	-	-	-	-	QUADSPI_ BK2_IO1	SAI2_ MCLK_B	ETH_MII_ COL	FMC_ SDNE0	-	LCD_R1	EVENT- OUT
	PH4	-	-	-	-	I2C2_SCL	-	-	-	-	LCD_G5	OTG_HS_ ULPI_NXT	-	-	-	LCD_G4	EVENT- OUT
	PH5	-	-	-	-	I2C2_SDA	SPI5_NSS	-	-	-	-	-	-	FMC_ SDNWE	-	-	EVENT- OUT
	PH6	-	-	TIM12_ CH1	-	I2C2_SMBA	SPI5_SCK	-	-	-	-	-	ETH_MII_ RXD2	FMC_ SDNE1	DCMI_D8	-	EVENT- OUT
Port H	PH7	-	-	-	-	I2C3_SCL	SPI5_ MISO	-	-	-	-	-	ETH_MII_ RXD3	FMC_ SDCKE1	DCMI_D9	-	EVENT- OUT
Por	PH8	-	-	TIM5_ETR	-	I2C3_SDA	-	-	-	-	-	-	1	FMC_D16	DCMI_ HSYNC	LCD_R2	EVENT- OUT
	PH9	-	-	TIM12_ CH2	-	I2C3_SMBA	-	-	-	-	-	-	1	FMC_D17	DCMI_D0	LCD_R3	EVENT- OUT
	PH10	-	-	TIM5_CH1	-	I2C4_SMBA	-	-	-	-	-	-	1	FMC_D18	DCMI_D1	LCD_R4	EVENT- OUT
	PH11	-	-	TIM5_CH2	-	I2C4_SCL	-	-	-	-	-	-	1	FMC_D19	DCMI_D2	LCD_R5	EVENT- OUT
	PH12	-	-	TIM5_CH3	-	I2C4_SDA	-	-	-	-	-	-	-	FMC_D20	DCMI_D3	LCD_R6	EVENT- OUT
	PH13	-	-	-	TIM8_ CH1N	-	-	-	-	UART4_TX	FDCAN1_ TX	-	-	FMC_D21	-	LCD_G2	EVENT- OUT
	PH14	-	-	-	TIM8_ CH2N	-	-	-	-	UART4_RX	FDCAN1_ RX	-	-	FMC_D22	DCMI_D4	LCD_G3	EVENT- OUT
	PH15	-	-	-	TIM8_ CH3N	-	-	-	-	-	-	-	-	FMC_D23	DCMI_D11	LCD_G4	EVENT- OUT

Table 18. Port I alternate functions

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
		AFU	AFI	AF2	AF3	AF4	AFS	AFO	AF7	AFO	SAI4/	-	I2C4/	AF 12	AFIS	AF 14	AFIS
	Port	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	12C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	FDCAN1/2/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1	SAI2/4/ TIM8/ QUADSPI/ SDMMC2/ OTG1_HS/ OTG2_FS/ LCD	UART7/ SWPMI1/ TIM1/8/ DFSDM1/ SDMMC2/ MDIOS/ ETH	TIM1/8/FMC /SDMMC1/ MDIOS/ OTG1_FS/ LCD	TIM1/DCMI /LCD/ COMP	UART5/ LCD	SYS
	PI0	·	-	TIM5_CH4	-	-	SPI2_NSS/ I2S2_WS	-	-	-	-	-	-	FMC_D24	DCMI_D13	LCD_G5	EVENT- OUT
	PI1	1	1	-	TIM8_ BKIN2	1	SPI2_SCK/ I2S2_CK	-	-	-	-	-	TIM8_BKIN 2_COMP12	FMC_D25	DCMI_D8	LCD_G6	EVENT- OUT
	PI2	-	-	-	TIM8_CH4	-	SPI2_ MISO/I2S2 _SDI	-	-	-	-	-	-	FMC_D26	DCMI_D9	LCD_G7	EVENT- OUT
	PI3	1	1	-	TIM8_ETR	1	SPI2_ MOSI/I2S2 _SDO	-	-	-	-	-	1	FMC_D27	DCMI_D10	1	EVENT- OUT
	PI4	-	-	-	TIM8_BKIN	1	-	-	-	-	-	SAI2_ MCLK_A	TIM8_BKIN _COMP12	FMC_NBL2	DCMI_D5	LCD_B4	EVENT- OUT
	PI5	1	1	-	TIM8_CH1	1	-	-	-	-	-	SAI2_SCK_ A	1	FMC_NBL3	DCMI_ VSYNC	LCD_B5	EVENT- OUT
	PI6	-	-	-	TIM8_CH2	1	-	-	-	-	-	SAI2_SD_A	1	FMC_D28	DCMI_D6	LCD_B6	EVENT- OUT
Port	PI7	-	-	-	TIM8_CH3	-	-	-	-	-	-	SAI2_FS_A	-	FMC_D29	DCMI_D7	LCD_B7	EVENT- OUT
	PI8	-	-	-	-	1	-	-	-	-	-	-	1	-	-	1	EVENT- OUT
	PI9	1	1	-	-	1	-	-	-	UART4_RX	FDCAN1_ RX	-	1	FMC_D30	-	LCD_ VSYNC	EVENT- OUT
	PI10	-	-	-	-	-	-	-	-	-	-	-	ETH_MII_ RX_ER	FMC_D31	-	LCD_ HSYNC	EVENT- OUT
	PI11	-	-	-	-	-	-	-	-	-	LCD_G6	OTG_HS_ ULPI_DIR	-	-	-	-	EVENT- OUT
	PI12	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LCD_ HSYNC	EVENT- OUT
	PI13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LCD_ VSYNC	EVENT- OUT
	PI14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	LCD_CLK	EVENT- OUT
	PI15	-	-	-	-	-	-	-	-	-	LCD_G2	-	-	-	-	LCD_R0	EVENT- OUT

EVENT-OUT

LCD_B3

							Table '	19. Port 、	J alterna	te funct	ions
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9
	Port	SYS	TIM1/2/16/ 17/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1	SAI4/ TIM13/14/ QUADSPI/ FMC/ SDMMC2/ LCD/ SPDIFRX1
	PJ0	-	-	-	-	-	-	-	-	-	LCD_R7
	PJ1	-	-	-	-	-	-	-	-	-	-
	PJ2	-	-	-	-	-	-	-	-	-	-
	PJ3	-	-	-	-	-	-	-	-	-	-
	PJ4	-	-	-	-	-	-	-	-	-	-
	PJ5	-	-	-	-	-	-	-	-	-	-
	PJ6	-	-	-	TIM8_CH2	-	-	-	-	-	-
- t	PJ7	TRGIN	-	-	TIM8_ CH2N	-	-	-	-	-	-
٩	PJ8	-	TIM1_CH3N	-	TIM8_CH1	-	-	-	-	UART8_TX	-
	PJ9	1	TIM1_CH3	-	TIM8_ CH1N	1	-	-	-	UART8_RX	-
	PJ10	1	TIM1_CH2N	-	TIM8_CH2	1	SPI5_ MOSI	-	-	-	-
	PJ11	-	TIM1_CH2	-	TIM8_ CH2N	-	SPI5_ MISO	-	-	-	-
	PJ12	TRGOUT	-	-	-	-	-	-	-	-	LCD_G3
	PJ13	-	-	-	-	-	-	-	-	-	LCD_B4
	PJ14	-	-	-	-	-	-	-	-	-	-

PJ15

Table 20. Port K alternate functions

_									· anconne	ito iaiiot
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8
	Port	SYS	TIM1/2/16/1 7/LPTIM1/ HRTIM1	SAI1/TIM3/ 4/5/12/ HRTIM1	LPUART/ TIM8/ LPTIM2/3/4 /5/HRTIM1/ DFSDM1	I2C1/2/3/4/ USART1/ TIM15/ LPTIM2/ DFSDM1/ CEC	SPI1/2/3/4/ 5/6/CEC	SPI2/3/SAI1 /3/I2C4/ UART4/ DFSDM1	SPI2/3/6/ USART1/2/ 3/6/UART7/ SDMMC1	SPI6/SAI2/ 4/UART4/5/ 8/LPUART/ SDMMC1/ SPDIFRX1
	PK0	-	TIM1_CH1N	-	TIM8_CH3	-	SPI5_SCK	-	-	-
	PK1	-	TIM1_CH1	-	TIM8_ CH3N	-	SPI5_NSS	-	-	-
	PK2	-	TIM1_BKIN	-	TIM8_BKIN	-	-	-	-	-
	PK3	-	-	-	-	-	-	-	-	-
	PK4	-	-	-	-	-	-	-	-	-
	PK5	-	-	-	-	-	-	-	-	-
	PK6	-	-	-	-	-	-	-	-	-
	PK7	-	-	-	-	-	-	-	-	-

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to V_SS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of junction temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction temperature at T_J = 25 °C and T_J = T_Jmax (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 sigma ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on T_J = 25 °C, V_DD = 3.3 V (for the 1.7 V ≤ V_DD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2sigma ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 13.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 14.

6.1.6 Power supply scheme

100 nF USB V_SS IOs USB V_DDLDO regulator Core domain (V_CORE) Voltage regulator switch D3 domain (System shifter D1 domain logic, D2 domain (CPU, peripherals, Ю EXTI. IOs (peripherals, RAM) Peripherals, Level logic RAM) RAM) Flash VDD domain HSI, LSI, CSI, HSI48, HSE, PLLs VBAT Backup domain charging Backup regulator LSE, RTC, Wakeup logic, Backup backup BKUP Ю RAM registers, IOs logic Reset V_SS Analog domain REF BUF ADC, DAC nF + 1 x 1 μF OPAMP, Comparator V_REF MSv46116V5

Figure 15. Power supply scheme

• 1. N corresponds to the number of VDD pins available on the package.
• 1. A tolerance of +/- 20% is acceptable on decoupling capacitors.

Caution:

Each power supply pair (V_DD/V_SS, V_DDA/V_SSA...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the

4

DS12110 Rev 10 103/357

ai14126

device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.

6.1.7 Current consumption measurement

VBAT VDD VDDA I DD_VBAT I DD

Figure 16. Current consumption measurement scheme

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics, Table 22: Current characteristics, and Table 23: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Symbols	Ratings	Min	Max	Unit
VDDX - VSS	External main supply voltage (including VDD, VDDLDO, VDDA, VDD33USB, VBAT)	-0.3	4.0	V
VIN(2)	Input voltage on FT_xxx pins	VSS-0.3	Min(VDD, VDDA, VDD33USB, VBAT) +4.0(3)(4)	V
	Input voltage on TT_xx pins	VSS-0.3	4.0	V
	Input voltage on BOOT0 pin	VSS	9.0	V
	Input voltage on any other pins	VSS-0.3	4.0	V
|ΔVDDX|	Variations between different VDDX power pins of the same domain	-	50	mV
|VSSx-VSS|	Variations between all the different ground pins	-	50	mV

Table 21. Voltage characteristics (1)

^1. All main power (VDD, VDDA, VDD33USB, VBAT) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

^2. VIN maximum must always be respected. Refer to Table 59 for the maximum allowed injected current values.

• 1. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
• 1. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.

Table 22. Current characteristics

Symbols	Ratings	Max	Unit
ΣIVDD	Total current into sum of all VDD power lines (source)(1)	620
ΣIVSS	Total current out of sum of all VSS ground lines (sink)(1)	620
IVDD	Maximum current into each VDD power pin (source)(1)	100
IVSS	Maximum current out of each VSS ground pin (sink)(1)	100
IIO	Output current sunk by any I/O and control pin, except Px_C	20	mA
	Output current sunk by Px_C pins	1
ΣI(PIN)	Total output current sunk by sum of all I/Os and control pins(2)	140
	Total output current sourced by sum of all I/Os and control pins(2)	140
IINJ(PIN)(3)(4)	Injected current on FT_xxx, TT_xx, RST and B pins except PA4, PA5	-5/+0
	Injected current on PA4, PA5	-0/0
ΣIINJ(PIN)	Total injected current (sum of all I/Os and control pins)(5)	±25

Table 23. Thermal characteristics

Symbol	Ratings	Value	Unit
TSTG	Storage temperature range	- 65 to +150	°C
TJ	Maximum junction temperature	125	°C

6.3 Operating conditions

6.3.1 General operating conditions

Table 24. General operating conditions

Symbol	Parameter	Operating conditions	Min	Max	Unit
VDD	Standard operating voltage	-	1.62(1)	3.6
VDDLDO	Supply voltage for the internal regulator	VDDLDO ≤ VDD	1.62(1)	3.6
VDD33USB	Standard operating voltage, USB domain	USB used	3.0	3.6
		USB not used	0	3.6
Symbol	Parameter	Operating conditions	Min	Max	Unit
VDDA	Analog operating voltage	ADC or COMP used	1.62	3.6	V

^1. When RESET is released functionality is guaranteed down to VBOR0 min

^2. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.

^3. For operation with voltage higher than Min (VDD, VDDA, VDD33USB) +0.3V, the internal Pull-up and Pull-Down resistors must be disabled.

^4. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 8.10: Thermal characteristics).

6.3.2 VCAP external capacitor

Stabilization for the main regulator is achieved by connecting an external capacitor C_EXT to the VCAP pin. C_EXT is specified in Table 25. Two external capacitors can be connected to VCAP pins.

Figure 17. External capacitor C_EXT

1. Legend: ESR is the equivalent series resistance.

Table 25. VCAP operating conditions⁽¹⁾

Symbol	Parameter	Conditions
CEXT	Capacitance of external capacitor	2.2 μF (2)
ESR	ESR of external capacitor	< 100 mΩ

• 1. When bypassing the voltage regulator, the two 2.2 μ F V_CAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors.
• 1. This value corresponds to CEXT typical value. A variation of +/-20% is tolerated.

6.3.3 Operating conditions at power-up / power-down

Subject to general operating conditions for T_A.

Table 26. Operating conditions at power-up / power-down (regulator ON)

Symbol	Parameter	Conditions
CEXT	Capacitance of external capacitor	2.2 µF⁽²⁾
ESR	ESR of external capacitor	< 100 mΩ

6.3.4 Embedded reset and power control block characteristics

The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

Table 27. Reset and power control block characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tRSTTEMPO(1)	Reset temporization after BOR0 released	-	-	377	-	μs
	Brown-out reset threshold 0	Rising edge(1)	1.62	1.67	1.71
VBOR0/POR/PDR	(VPOR/VPDR thresholds)	Falling edge	1.58	1.62	1.68
		Rising edge	2.04	2.10	2.15
VBOR1	Brown-out reset threshold 1	Falling edge	1.95	2.00	2.06
		Rising edge	2.34	2.41	2.47
VBOR2	Brown-out reset threshold 2	Falling edge	2.25	2.31	2.37
		Rising edge	2.63	2.70	2.78
VBOR3	Brown-out reset threshold 3	Falling edge	2.54	2.61	2.68
	Programmable Voltage	Rising edge	1.90	1.96	2.01
VPVD0	Detector threshold 0	Falling edge	1.81	1.86	1.91
	Programmable Voltage	Rising edge	2.05	2.10	2.16
VPVD1	Detector threshold 1	Falling edge	1.96	2.01	2.06	V
	Programmable Voltage	Rising edge	2.19	2.26	2.32
VPVD2	Detector threshold 2	Falling edge	2.10	2.15	2.21
	Programmable Voltage	Rising edge	2.35	2.41	2.47
VPVD3	Detector threshold 3	Falling edge	2.25	2.31	2.37
	Programmable Voltage	Rising edge	2.49	2.56	2.62
VPVD4	Detector threshold 4	Falling edge	2.39	2.45	2.51
	Programmable Voltage	Rising edge	2.64	2.71	2.78
VPVD5	Detector threshold 5	Falling edge	2.55	2.61	2.68
	Programmable Voltage	Rising edge	2.78	2.86	2.94
VPVD6	Detector threshold 6	Falling edge in Run mode	2.69	2.76	2.83
Vhyst_BOR_PVD	Hysteresis voltage of BOR (unless BOR0) and PVD	Hysteresis in Run mode	-	100	-	mV
IDD_BOR_PVD(1)	BOR(2) (unless BOR0) and PVD consumption from VDD	-	-	-	0.630	μA

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tRSTTEMPO(1)	Reset temporization after BOR0 released	-	-	377	-	µs
VBOR0/POR/PDR	Brown-out reset threshold 0 (VPOR/VPDR thresholds)	Rising edge(1)	1.62	1.67	1.71	V
		Falling edge	1.58	1.62	1.68
VBOR1	Brown-out reset threshold 1	Rising edge	2.04	2.10	2.15	V
		Falling edge	1.95	2.00	2.06
VBOR2	Brown-out reset threshold 2	Rising edge	2.34	2.41	2.47	V
		Falling edge	2.25	2.31	2.37
VBOR3	Brown-out reset threshold 3	Rising edge	2.63	2.70	2.78	V
		Falling edge	2.54	2.61	2.68
VPVD0	Programmable Voltage Detector threshold 0	Rising edge	1.90	1.96	2.01	V
		Falling edge	1.81	1.86	1.91
VPVD1	Programmable Voltage Detector threshold 1	Rising edge	2.05	2.10	2.16	V
		Falling edge	1.96	2.01	2.06
VPVD2	Programmable Voltage Detector threshold 2	Rising edge	2.19	2.26	2.32	V
		Falling edge	2.10	2.15	2.21
VPVD3	Programmable Voltage Detector threshold 3	Rising edge	2.35	2.41	2.47	V
		Falling edge	2.25	2.31	2.37
VPVD4	Programmable Voltage Detector threshold 4	Rising edge	2.49	2.56	2.62	V
		Falling edge	2.39	2.45	2.51
VPVD5	Programmable Voltage Detector threshold 5	Rising edge	2.64	2.71	2.78	V
		Falling edge	2.55	2.61	2.68
VPVD6	Programmable Voltage Detector threshold 6	Rising edge	2.78	2.86

Table 27. Reset and power control block characteristics (continued)

6.3.5 Embedded reference voltage

The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

Table 28. Embedded reference voltage

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VAVM_0	Analog voltage detector for VDDA threshold 0	Rising edge	1.66	1.71	1.76	V
		Falling edge	1.56	1.61	1.66
VAVM_1	Analog voltage detector for VDDA threshold 1	Rising edge	2.06	2.12	2.19
		Falling edge	1.96	2.02	2.08
VAVM_2	Analog voltage detector for VDDA threshold 2	Rising edge	2.42	2.50	2.58
		Falling edge	2.35	2.42	2.49
VAVM_3	Analog voltage detector for VDDA threshold 3	Rising edge	2.74	2.83	2.91
		Falling edge	2.64	2.72	2.80
Vhyst_VDDA	Hysteresis of VDDA voltage detector	-	-	100	-	mV
IDD_PVM	PVM consumption from VDD(1)	-	-	-	0.25	µA
IDD_VDDA	Voltage detector consumption on VDDA(1)	Resistor bridge	-	-	2.5	µA

^1. Guaranteed by design.

^2. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables (refer to Section 6.3.6: Supply current characteristics).

| Table 28. Embedded reference voltage | |---|---|---|---|---|---|---| | Symbol | Parameter | Conditions | Min | Typ | Max | Unit | | VREFINT | Internal reference voltages | -40°C < TJ < 105°C, VDD = 3.3 V | 1.180 | 1.216 | 1.255 | V | | tS_vrefint^(1)(2) | ADC sampling time when reading the internal reference voltage | - | 4.3 | - | - | µs | | tS_vbat^(1)(2) | VBAT sampling time when reading the internal VBAT reference voltage | - | 9 | - | - | µs | | Irefbuf^(2) | Reference Buffer consumption for ADC | VDDA=3.3 V | 9 | 13.5 | 23 | µA | | ΔVREFINT^(2) | Internal reference voltage spread over the temperature range | -40°C < TJ < 105°C | - | 5 | 15 | mV | | Tcoeff^(2) | Average temperature coefficient | Average temperature coefficient | - | 20 | 70 | ppm/°C | | VDDcoeff^(2) | Average Voltage coefficient | 3.0V < VDD < 3.6V | - | 10 | 1370 | ppm/V |

Table 29. Internal reference voltage calibration values

Symbol	Parameter	Memory address
VREFIN_CAL	Raw data acquired at temperature of 30 °C, VDDA = 3.3 V	1FF1E860 - 1FF1E861

6.3.6 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in Figure 16: Current consumption measurement scheme.

All the run-mode current consumption measurements given in this section are performed with a CoreMark code.

Typical and maximum current consumption

The MCU is placed under the following conditions:

• All I/O pins are in analog input mode.
• All peripherals are disabled except when explicitly mentioned.
• The flash memory access time is adjusted with the minimum wait states number, depending on the fACLK frequency (refer to the table "Number of wait states according to CPU clock (frcc_c_ck) frequency and VCORE range" available in the reference manual).
• When the peripherals are enabled, the AHB clock frequency is the CPU frequency divided by 2 and the APB clock frequency is AHB clock frequency divided by 2.

The parameters given in Table 30 to Table 38 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions.

Table 30. Typical and maximum current consumption in Run mode, code with data processing running from ITCM, regulator mathsf{ON}⁽¹⁾

				£			Ma	x (2)
Symbol	Parameter	Condition	ons	f rcc_c_ck (MHz)	Typ	T J = 25°C	T J = 85°C	T J = 105°C
			VOS1	400	71	110	210	290
			VO31	300	56	-	-	-
				300	50	72	170	230
			VOS2	216	37	58	150	210
		All peripherals		200	35.5	-	-	-
		peripherals		200	33	50	130	190
		disabled			180	30	47	130
	Supply current in Run		VOS3	168	28	45	130	180
I DD	mode		VU33	144	25	41	120	180
				25	10	24	99	160
			VOS1	400	165	220 (3)	400	500 (3)
		All peripherals	VUST	300	130	-	-	-
			VOSS	300	120	170	300	390
			VOS2	200	83	-	-	-
			VOS3	200	78	110	220	300

^2. Guaranteed by characterization results unless otherwise specified.

^3. Guaranteed by test in production.

Table 31. Typical and maximum current consumption in Run mode, code with data processing running from flash memory, cache ON, regulator ON

								x (1)
Symbol	Parameter	Condition	ons	f rcc_c_ck (MHz)	Typ	T J = 25°C	T J = 85°C	T J = 105°C
			VOS1	400	105	160	310	420
			VO31	300	55	-	-	-
				300	50	72	160	230
		All	VOS2	216	38	-	-	-
		All peripherals		200	36	-	-	-
		All peripherals disabled		200	33	50	130	190
		disabled		180	30	-	-	-
	Supply current in Run		VOS3	168	29	-	-	-
I DD	mode		VU33	144	26	-	-	-
				25	14	-	-	-
			VOS1	400	160	220	400	500
		All	VU31	300	130	-	-	-
			VOS2	300	120	160	300	390
			VU32	200	81	-	-	-
			VOS3	200	77	110	220	300

Table 32. Typical and maximum current consumption in Run mode, code with data processing running from flash memory, cache OFF, regulator ON

Symbol	Parameter	Conditions		f_rcc_c_ck (MHz)	Typ	Max(1)				unit
						T_J = 25°C	T_J = 85°C	T_J = 105°C	T_J = 125°C
IDD	Supply current in Run mode	All peripherals disabled	VOS1	400	73	110	220	290	540	mA
			VOS2

Table 33. Typical consumption in Run mode and corresponding performance versus code position

Symbol	Parameter	Peripheral	Code	f_rcc_c_ck (MHz)	CoreMark	Typ	Unit	IDD/CoreMark	Unit
IDD	Supply current in Run mode	All peripherals disabled, cache ON	ITCM	400	2012	71	mA	35	μA/CoreMark
			FLASH A	400	2012	105		52
			AXI SRAM	400	2012	105		5
Table 34. Typical current consumption batch acquisition mode

Symbol	Parameter	Condition	ıs	f rcc_ahb_ck(AHB4) (MHz)	Typ	unit
I DD	Supply current in batch acquisition	D1Standby, D2Standby, D3Run	VOS3	64	6.5	mA
	mode	D1Stop, D2Stop, D3Run	VOS3	64	12

				fron a ak
Symbol	Parameter	Condition	ons	f rcc_c_ck (MHz)
			VOS1	400
	Supply	All	VO31	300
I DD(Sleep)	sleep) current in perip		VOS2	300
	Sleep mode		V032	200
			VOS3	200

Table 36. Typical and maximum current consumption in Stop mode, regulator ON

					-		x (1)
Symbol	Parameter	Conditi	ons	Typ	T J = 25°C	T J = 85°C	T J = 105°C
		Flash	SVOS5	1.4	7.2 (2)	49	75 (2)
		memory in low-power	SVOS4	1.95	11	66	110
	D1Stop, D2Stop,	mode, no IWDG	SVOS3	2.85	16 (2)	91	150 (2)
	D3Stop	Flash	SVOS5	1.65	7.2	49	75
		memory ON,	SVOS4	2.2	11	66	110
		no IWDG	SVOS3	3.15	16	91	150
		Flash	SVOS5	0.99	5.1	35	60
		memory OFF, no	SVOS4	1.4	7.5	47	79
I DD(Stop)	D1Stop, D2Standby,	IWDG	SVOS3	2.05	12	64	110
(******)	D3Stop	Flash	SVOS5	1.25	5.5	35	61
		memory ON,	SVOS4	1.65	7.8	47	80
		no IWDG	no IWDG	no IWDG	no IWDG	no IWDG	SVOS3
	D1Standby,		SVOS5	0.57	3	21	36
	D2Stop,		SVOS4	0.805	4.5	27	47
	D3Stop	Flash OFF,	SVOS3	1.2	6.7	37	63
		no IWDG	SVOS5	0.17	1.1 (2)	8	13 (2)
	D2Standby,		SVOS4	0.245	1.5	11	17
	D3Stop			SVOS3	0.405	2.4 (2)	15

Table 37. Typical and maximum current consumption in Standby mode

		Condit	ions	Typ (3)				Max (3 V) (1)
Symbol	Parameter	Backup SRAM	RTC & LSE	1.62 V	2.4 V	3 V	3.3 V	T J = 25°C
	Cunnly	OFF	OFF	1.8	1.9	1.95	2.05	4 (2)
I DD	Supply current in	ON	OFF	3.4	3.4	3.5	3.7	8.2 (3)
(Standby)	Standby mode	OFF	ON	2.4	3.5	3.86	4.12	-
	mode	ON	ON	3.95	5.1	5.46	5.97	-

^2. Guaranteed by test in production.

^2. Guaranteed by test in production.

^3. Guaranteed by characterization results.

| Symbol | Parameter | Backup SRAM | RTC & LSE | 1.2 V | 2 V | 3 V | 3.4 V | TJ = 25°C | TJ = 85°C | TJ = 105°C | TJ = 125°C | Unit |

Symbol	Parameter	Backup SRAM	RTC & LSE	1.2 V	2 V	3 V	3.4 V	TJ = 25°C	TJ = 85°C	TJ = 105°C	TJ = 125°C	Unit
IDD (VBAT)	Supply current in standby mode	OFF	OFF	0.024	0.035	0.062	0.096	0.5^(1)	4.1^(1)	10^(1)
Table 38. Typical and maximum current consumption in VBAT mode

I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.

I/O static current consumption

All the I/Os used as inputs with pull-up or pull-down generate a current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 60: I/O static characteristics.

For the output pins, any internal or external pull-up or pull-down, and any external load must also be considered to estimate the current consumption.

An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs.

Caution:

Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.

I/O dynamic current consumption

In addition to the internal peripheral current consumption (see Table 39: Peripheral current consumption in Run mode), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the internal or external capacitive load connected to the pin:

$I_SW = V_DDx × f_SW × C_L$

where

$I_{\mathrm{SW}}$ is the current sunk by a switching I/O to charge/discharge the capacitive load

$V_{\text{DDx}}$ is the MCU supply voltage

f_SW is the I/O switching frequency

$C_L$ is the total capacitance seen by the I/O pin: $C = C_{INT} + C_{EXT}

DS12110 Rev 10 115/357

^1. Guaranteed by characterization results.

The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency.

On-chip peripheral current consumption

The MCU is placed under the following conditions:

• At startup, all I/O pins are in analog input configuration.
• All peripherals are disabled unless otherwise mentioned.
• The I/O compensation cell is enabled.
• frcc_cck is the CPU clock. fPCLK = frcc_cck/4, and fHCLK = frcc_cck/2. The given value is calculated by measuring the difference of current consumption
  • with all peripherals clocked off
  • with only one peripheral clocked on
  • frcc_cck = 400 MHz (Scale 1), frcc_cck = 300 MHz (Scale 2), frcc_cck = 200 MHz (Scale 3)
• The ambient operating temperature is 25 °C and VDD=3.3 V.

Table 39. Peripheral current consumption in Run mode

			IDD(Typ)
	Peripheral	VOS1	VOS2
	MDMA	8.3	7.6
	DMA2D	21	20
	JPEG	24	23
	FLASH	9.9	9
	FMC registers	0.9	0.9
	FMC kernel	6.1	5.5
	QUADSPI registers	1.5	1.4
AHB3	QUADSPI kernel	0.9	0.8
	SDMMC1 registers	8	7.2
	SDMMC1 kernel	2.4	2
	DTCM1	5.7	5
	DTCM2	5.5	4.8
	ITCM	3.2	2.9
	D1SRAM1	7.6	6.8
	AHB3 bridge	7.5	6.8
	DMA1	1.1	1
	DMA2	1.7	1.4
	ADC1/2 registers	3.9	3.2
	ADC1/2 kernel	0.9	0.8
	ART accelerator ETH1MAC	5.5	4.5
	ETH1TX ETH1RX	16	14
AHB1	USB1 OTG registers	15	14
	USB1 OTG kernel	-	8.5
	USB1 ULPI	0.3	0.3
	USB2 OTG registers	15	13
	USB2 OTG kernel	-	8.6
	USB2 ULPI	16	16
	AHB1 Bridge	10	9.6

	Peripheral	VOS1	VOS2	VOS3	Unit
	MDMA	8.3	7.6	7	µA/MHz
	DMA2D	21	20	18	µA/MHz
	JPEG	24	23	21	µA/MHz
	FLASH	9.9	9	8.3	µA/MHz
	FMC registers	0.9	0.9	0.8	µA/MHz
	FMC kernel	6.1	5.5	5.3	µA/MHz
	QUADSPI registers	1.5	1.4	1.3	µA/MHz
AHB3	QUADSPI kernel	0.9	0.8	0.7	µA/MHz
	SDMMC1 registers	8	7.2	6.8	µA/MHz
	SDMMC1 kernel	2.4	2	1.8	µA/MHz
	DTCM1	5.7	5	4.5	µA/MHz
	DTCM2	5.5	4.8	4.3	µA/MHz
	ITCM	3.2	2.9	2.6	µA/MHz
	D1SRAM1	7.6	6.8	6.1	µA/MHz
	AHB3 bridge	7.5	6.8	6.3	µA/MHz
	DMA1	1.1	1	1	µA/MHz
	DMA2	1.7	1.4	1.1	µA/MHz
	ADC1/2 registers	3.9	3.2	3.1	µA/MHz
	ADC1/2 kernel	0.9	0.8	0.7	µA/MHz
	ART accelerator	5.5	4.5	4.2	µA/MHz
	ETH1MAC	-	-	-	µA/MHz
	ETH1TX	16	14	13	µA/MHz
	ETH1RX	-	-	-	µA/MHz
AHB1	USB1 OTG registers	15	14	13	µA/MHz
	USB1 OTG kernel	-	8.5	8.5	µA/MHz
	USB1 ULPI	0.3	0.3	0.1	µA/MHz
	USB2 OTG registers	15	13	12	µA/MHz
	USB2 OTG kernel	-	8.6	8.6	µA/MHz
	USB2 ULPI	16	16	16	µA/MHz
	AHB1 Bridge	10	9.6	8.6	µA/MHz

	Peripheral	VOS1	VOS2	VOS3	Unit
AHB3	MDMA	8.3	7.6	7	µA/MHz
	DMA2D	21	20	18
	JPEG	24	23	21
	FLASH	9.9	9	8.3
	QUADSPI	1.9	1.8	1.7
	OCTOSPI	1.9	1.8	1.7
	SDMMC1 registers	1.8	1.4	1.2
	SDMMC1 kernel	2.7	2.5	2.4
	AHB3 bridge	0.1	0.1	0.1
APB3	LCD-TFT	12	11	10	µA/MHz
	WWDG1	0.5	0.4	0.3
	APB3 bridge	0.5	0.2	0.1
	FMC registers	0.9	0.9	0.8
	FMC kernel	6.1	5.5	5.3
	QU
Table 39. Peripheral current consumption in Run mode (continued)

	Peripheral	VOS1	VOS2	VOS3	Unit
AHB3	MDMA	8.3	7.6	7	μA/MHz
	DMA2D	21	20	18
	JPEG	24	23	21
	FLASH	9.9	9	8.3
	FMC registers	0.9	0.9	0.8
	FMC kernel	6.1	5.5	5.3
	QUADSPI registers	1.5	1.4	1.3
	QUADSPI kernel	0.9	0.8	0.7
	SDMMC1 registers	8	7.2	6.8
	SDMMC1 kernel	2.4	2	1.8
	DTCM1	5.7	5	4.5
	DTCM2	5.5	4.8	4.3
	ITCM	3.2	2.9	2.6
	D1SRAM1	7.6	6.8	6.1
	AHB3 bridge	7.5	6.8	6.3
	DMA1	1.1	1	1
	DMA2	1.7	1.4	1.1
	ADC1/2 registers	3.9	3.2	3.1
	ADC1/2 kernel	0.9	0.8	0.7
	ART accelerator	5.5	4.5	4.2
	ETH1MAC
	ETH1TX	16	14	13
	ETH1RX
AHB1	USB1 OTG registers	15	14	13
	USB1 OTG kernel	-	8.5	8.5
	USB1 ULPI	0.3	0.3	0.1
	USB2 OTG registers	15	13	12
	USB2 OTG kernel	-	8.6	8.6
	USB2 ULPI	16	16	16
	AHB1 Bridge	10	9.6	8.6

			IDD(Typ)
	Peripheral	VOS1	VOS2
	TIM1	5.1	4.8
	TIM8	5.4	4.9
	USART1 registers	2.7	2.6
	USART1 kernel	0.1	0.1
	USART6 registers	2.6	2.5
	USART6 kernel	0.1	0.1
	SPI1 registers	1.8	1.6
	SPI1 kernel	1	0.8
	SPI4 registers	1.6	1.5
	SPI4 kernel	0.5	0.4
	TIM15	3.1	2.8
	TIM16	2.4	2.1
APB2	TIM17	2.2	2
	SPI5 registers	1.8	1.7
	SPI5 kernel	0.6	0.5
	SAI1 registers	1.5	1.4
	SAI1 kernel	2	1.7
	SAI2 registers	1.5	1.5
	SAI2 kernel	2.2	1.9
	SAI3 registers	1.8	1.6
	SAI3 kernel	2.5	2.3
	DFSDM1 registers	6	5.4
	DFSDM1 kernel	0.9	0.8
	HRTIM	40	37
AHB2	DCMI	1.7	1.7
AHB2	RNG registers	1.8	1.4
AHB2	RNG kernel	-	9.6
AHB2	SDMMC2 registers	13	12
AHB2	SDMMC2 kernel	2.7	2.5
AHB2	D2SRAM1	3.3	3.1
AHB2	D2SRAM2	2.9	2.7
AHB2	D2SRAM3	1.9	1.8
AHB2	AHB2 bridge	0.1	0.1
AHB4	GPIOA	1.1	1
AHB4	GPIOB	1	0.9
AHB4	GPIOC	1.4	1.3
AHB4	GPIOD	1.1	1
AHB4	GPIOE	1	0.9
AHB4	GPIOF	0.9	0.8
AHB4	GPIOG	0.9	0.7
AHB4	GPIOH	1	0.9
AHB4	GPIOI	0.9	0.9
AHB4	GPIOJ	0.9	0.8
AHB4	GPIOK	0.9	0.8
AHB4	CRC	0.5	0.4
AHB4	BDMA	6.2	5.8
AHB4	ADC3 registers	1.8	1.7
AHB4	ADC3 kernel	0.1	0.1
AHB4	Backup SRAM	1.9	1.8
AHB4	Bridge AHB4	0.1	0.1
APB3	LCD-TFT	12	11
APB3	WWDG1	0.5	0.4
APB3	APB3 bridge	0.5	0.2
	Bridge APB2	0.1	0.1

AHB Bus	Peripheral	VOS1	VOS2	VOS3	Unit
	MDMA	8.3	7.6	7	µA/MHz
	DMA2D	21	20	18	µA/MHz
	JPEG	24	23	21	µA/MHz
	FLASH	9.9	9	8.3	µA/MHz
	FMC registers	0.9	0.9	0.8	µA/MHz
	FMC kernel	6.
Table 40. Peripheral current consumption in Stop, Standby and VBAT mode

Peripheral	VOS1	VOS2	VOS3	Unit
SYSCFG	1	0.7	0.7
LPUART1 registers	1.1	1.1	1.1
LPUART1 kernel	2.6	2.4	2.1
SPI6 registers	1.6	1.5	1.4
SPI6 kernel	0.2	0.2	0.2
I2C4 registers	0.1	0.1	0.1

6.3.7 Wakeup time from low-power modes

The wakeup times given in Table 41 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU:

• For Stop or Sleep modes: the wakeup event is WFE.
• WKUP (PC1) pin is used to wakeup from Standby, Stop and Sleep modes.

All timings are derived from tests performed under ambient temperature and VDD=3.3 V.

Table 41. Low-power mode wakeup timings

Symbol	Parameter	Conditions	Typ(1)	Max(1)	Unit
tWUSLEEP$^{(2)}$	Wakeup from Sleep	-	9	10	CPU clock cycles
		VOS3, HSI, flash memory in normal mode	4.4	5.6
		VOS3, HSI, flash memory in low-power mode	12	15
		VOS4, HSI, flash memory in normal mode	15

^2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.

6.3.8 External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.

The external clock signal has to respect the Table 60: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 18.

Table 42. High-speed external user clock characteristics⁽¹⁾

Symbol	Parameter	Min	Typ	Max	Unit
fHSE_ext	User external clock source frequency	4	25	50	MHz
VHSEH	Digital OSC_IN input high-level voltage	0.7 VDD	-	VDD	V
VHSEL	Digital OSC_IN input low-level voltage	VSS	-	0.3 VDD
tW(HSE)	OSC_IN high or low time	7	-	-	ns

^1. Guaranteed by design. | | F | Oscillator frequency | - | - | 32.768 | - | kHz | | | | LSEDRV[1:0] = 00, Low drive capability | - | 290 | - | | | | | LSEDRV[1:0] = 01, Medium Low drive capability | - | 390 | - | | | I_DD | LSE current consumption | LSEDRV[1:0] = 10, Medium high drive capability | - | 550 | -

Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 60: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 19.

Table 43. Low-speed external user clock characteristics⁽¹⁾

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fLSE_ext	User external clock source frequency	-	-	32.768	1000	kHz
VLSEH	OSC32_IN input pin high level voltage	-	0.7 VDDIOx	-	VDDIOx	V
VLSEL	OSC32_IN input pin low level voltage	-	VSS	-	0.3 VDDIOx	V
$\begin{array}{c} t_{w(\text{LSEH})} \ t_{w(\text{LSEL})} \end{array}$	OSC32_IN high or low time	-	250	-	-	ns

^1. Guaranteed by design.

Note:

For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs" available from the ST website www.st.com.

Figure 19. Low-speed external clock source AC timing diagram VLSEH 90% 10% V_I SFI tW(LSE) tr(LSE) t_f(LSE) tW(LSE)\mathsf{T}_{\mathsf{LSE}}$ fLSE ext External OSC32 IN clock source STM32 ai17529b

High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 44. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol	Parameter	Operating conditions (2)	Min	Typ	Max	Unit
F	Oscillator frequency	-	4	-	48	MHz
RF	Feedback resistor	-	-	200	-	kΩ
IDD(HSE)	HSE current consumption	During startup (3)	-	-	4	mA
		VDD=3 V, Rm=30 Ω CL=10pF@4MHz	-	0.35	-
		VDD=3 V, Rm=3

Table 44. 4-48 MHz HSE oscillator characteristics⁽¹⁾

• 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
• 1. This consumption level occurs during the first 2/3 of the $t_{\mbox{\scriptsize SU(HSE)}}$ startup time.
• 1. t_SU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For $C_{L1}$ and $C_{L2}$ , it is recommended to use high-quality external ceramic capacitors, designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 20). $C_{L1}$ and $C_{L2}$ are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of $C_{L1}$ and $C_{L2}$ . The PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing $C_{L1}$ and $C_{L2}.

Note:

For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs" available from the ST website www.st.com.

^1. Guaranteed by design.

ai17530b OSC_OUT OSC_IN f HSE CL1 RF STM32 8 MHz resonator Resonator with integrated capacitors Bias controlled gain REXT(1) CL2

Figure 20. Typical application with an 8 MHz crystal

1. REXT value depends on the crystal characteristics.

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 45. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Table 45. Low-speed external user clock characteristics(1)

Symbol	Parameter	Operating conditions(2)	Min	Typ	Max	Unit
F	Oscillator frequency	-	-	32.768	-	kHz
		LSEDRV[1:0] = 00, Low drive capability	-	290	-
	LSE current	LSEDRV[1:0] = 01, Medium Low drive capability	-	390	-
IDD	consumption	LSEDRV[1:0] = 10, Medium high drive capability	-	550	-	nA
		LSEDRV[1:0] = 11, High drive capability	-	900	-
		LSEDRV[1:0] = 00, Low drive capability	-	-	0.5
	Maximum critical crystal	LSEDRV[1:0] = 01, Medium Low drive capability	-	-	0.75
Gmcritmax	gm	LSEDRV[1:0] = 10, Medium high drive capability	-	-	1.7	μA/V
		LSEDRV[1:0] = 11, High drive capability	-	-	2.7
tSU(3)	Startup time	VDD is stabilized	-	2	-	s

^1. Guaranteed by design.

• 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for STM8AL/AF/S, STM32 MCUs and MPUs".
• 1. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768k Hz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for STM8AL/AF/S, STM32 MCUs and MPUs" available from the ST website www.st.com.

Figure 21. Typical application with a 32.768 kHz crystal

1. An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

6.3.9 Internal clock source characteristics

The parameters given in Table 46 and Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

48 MHz high-speed internal RC oscillator (HSI48)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI48	HSI48 frequency	VDD=3.3 V, TJ=30 °C	47.5(1)	48	48.5(1)	MHz
TRIM(2)	USER trimming step	-	-	0.17	-	%
USER TRIM COVERAGE(3)	USER TRIMMING Coverage	± 32 steps	-	±5.45	-	%
DuCy(HSI48)(2)	Duty Cycle	-	45	-	55	%
ACCHSI48REL(3)	Accuracy of the HSI48 oscillator over temperature (factory calibrated)	VDD=1.62 to 3.6 V, TJ=-40 to 125 °C	–4.5	-	3.5	%
∆VDD(HSI48)(3)	HSI48 oscillator frequency drift with	VDD=3 to 3.6 V	-	0.025	0.05
	VDD(4)	VDD=1.62 V to 3.6 V	-	0.05	0.1	%
tsu(HSI48)(2)	HSI48 oscillator start-up time	-	-	2.1	3.5	μs
IDD(HSI48)(2)	HSI48 oscillator power consumption	-	-	350	400	μA
NT jitter	Next transition jitter Accumulated jitter on 28 cycles(5)	-	-	± 0.15	-	ns
PT jitter	Paired transition jitter Accumulated jitter on 56 cycles(5)	-	-	± 0.25	-	ns

Table 46. HSI48 oscillator characteristics

• 1. Guaranteed by test in production.
• 2. Guaranteed by design.
• 3. Guaranteed by characterization.
• 1. These values are obtained by using the formula: (Freq(3.6V) - Freq(3.0V)) / Freq(3.0V) or (Freq(3.6V) - Freq(1.62V)) / Freq(1.62V).
• 5. Jitter measurements are performed without clock source activated in parallel.

64 MHz high-speed internal RC oscillator (HSI)

Table 47. HSI oscillator characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI	HSI frequency	VDD=3.3 V, TJ=30 °C	63.7(2)	64	64.3(2)	MHz
	HSI user trimming step	Trimming is not a multiple of 32	-	0.24	0.32
		Trimming is 128, 256 and 384	-5.2	-1.8	-
TRIM		Trimming is 64, 192, 320 and 448	-1.4	-0.8	-	%
		Other trimming are a multiple of 32 (not including multiple of 64 and 128)	-0.6	-0.25	-
DuCy(HSI)	Duty Cycle	-	45	-	55	%
ΔVDD (HSI)	HSI oscillator frequency drift over VDD (reference is 3.3 V)	VDD=1.62 to 3.6 V	-0.12	-	0.03	%
	HSI oscillator frequency drift over	TJ=-20 to 105 °C	-1(3)	-	1(3)	%
ΔTEMP (HSI)	temperature (reference is 64 MHz)	TJ=-40 to TJmax °C	-2(3)	-	1(3)
tsu(HSI)	HSI oscillator start-up time	-	-	1.4	2	μs
tstab(HSI)	HSI oscillator stabilization time	at 1% of target frequency	-	4	8	μs
IDD(HSI)	HSI oscillator power consumption	-	-	300	400	μA

• 1. Guaranteed by design unless otherwise specified.
• 2. Guaranteed by test in production.
• 3. Guaranteed by characterization.

4 MHz low-power internal RC oscillator (CSI)

Table 48. CSI oscillator characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fCSI	CSI frequency	VDD=3.3 V, TJ=30 °C	3.96(2)	4	4.04(2)	MHz
TRIM	Trimming step	-	-	0.35	-	%
DuCy(CSI)	Duty Cycle	-	45	-	55	%
Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	CSI oscillator frequency drift over ∆TEMP (CSI) temperature	TJ = 0 to 85 °C	-	-3.7(3)	4.5(3)
		TJ = -40 to 125 °C	-	-11(3)	7.5(3)	%
DVDD (CSI)	CSI oscillator frequency drift over VDD	VDD = 1.62 to 3.6 V	-	-0.06	0.06	%
tsu(CSI)	CSI oscillator startup time	-	-	1	2	μs
tstab(CSI)	CSI oscillator stabilization time (to reach ±3% of fCSI)	-	-	4	8	cycle
IDD(CSI)	CSI oscillator power consumption	-	-	23	30	μA

Table 48. CSI oscillator characteristics(1) (continued)

• 1. Guaranteed by design.
• 2. Guaranteed by test in production.
• 3. Guaranteed by characterization.

Low-speed internal (LSI) RC oscillator

Table 49. LSI oscillator characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fLSI(1) LSI frequency		VDD = 3.3 V, TJ = 25 °C	31.4	32	32.6
		TJ = –40 to 105 °C, VDD = 1.62 to 3.6 V	29.76	-	33.60	kHz
tsu(LSI)(2)	LSI oscillator startup time	-	-	80	130
tstab(LSI)(2)	LSI oscillator stabilization time (5% of final value)	-	-	120	170	μs
IDD(LSI)(2)	LSI oscillator power consumption	-	-	130	280	nA

• 1. Guaranteed by characterization results.
• 2. Guaranteed by design.

6.3.10 PLL characteristics

The parameters given in Table 50 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

Table 50. PLL characteristics (wide VCO frequency range)(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	PLL input clock	-	2	-	16	MHz
fPLLIN	PLL input clock duty cycle	-	10	-	90	%

Table 50. PLL characteristics (wide VCO frequency range)(1) (continued)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
		VOS1		1.5	-	400(2)
fPLLPOUT	PLL multiplier output clock P	VOS2		1.5	-	300
		VOS3		1.5	-	200
		VOS1		1.5	-	400(2)	MHz
fPLLQOUT	PLL multiplier output clock Q/R	VOS2		1.5	-	300
		VOS3		1.5	-	200
fVCOOUT	PLL VCO output	- 192		-	836
	PLL lock time	Normal mode		-	50(3)	150(3)
tLOCK		Sigma-delta mode (CKIN ≥ 8 MHz)		-	58(3)	166(3)	μs
		VCO = 192 MHz		-	134	-
	Cycle-to-cycle jitter(4)	VCO = 200 MHz		-	134	-	±ps
		VCO = 400 MHz		-	76	-
Jitter		VCO = 800 MHz		-	39	-
		Normal mode		-	±0.7	-
	Long term jitter	Sigma-delta mode (CKIN = 16 MHz)		-	±0.8	-	%
		VCO freq =	VDDA	-	440	1150
	420 MHz		VCORE	-	530	-
IDD(PLL)(3)	PLL power consumption on VDD	VCO freq =	VDDA	-	180	500	μA
		150 MHz	VCORE	-	200	-

Table 51. PLL characteristics (medium VCO frequency range)(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
	PLL input clock	-	1	-	2	MHz
fPLLIN	PLL input clock duty cycle	-	10	-	90	%
	PLL multiplier output clock P, Q, R	VOS1	1.17	-	210
fPLLOUT		VOS2	1.17	-	210	MHz
		VOS3	1.17	-	200
fVCOOUT	PLL VCO output	-	150	-	420	MHz
	PLL lock time	Normal mode	-	60(2)	100(2)	μs
tLOCK		Sigma-delta mode	forbidden	-	-	μs

^2. This value must be limited to the maximum frequency due to the product limitation (400 MHz for VOS1, 300 MHz for VOS2, 200 MHz for VOS3).

^3. Guaranteed by characterization results.

^4. Integer mode only.

Table 51. PLL characteristics (medium VCO frequency range)(1) (continued)

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
			VCO = 150 MHz	-	145	-
	Cycle-to-cycle jitter(3)	-	VCO = 300 MHz	-	91	-	+/-
			VCO = 400 MHz	-	64	-	ps
			VCO = 420 MHz	-	63	-
Jitter	Period jitter	fPLLOUT = 50 MHz	VCO = 150 MHz	-	55	-	+/- ps
			VCO = 400 MHz	-	30	-
	Long term jitter	Normal mode	VCO = 150 MHz	-	-	-
			VCO = 300 MHz	-	-	-	%
			VCO = 400 MHz	-	+/-0.3	-
		VCO freq =	VDD	-	440	1150	μA
I(PLL)(2)		420MHz	VCORE	-	530	-
	PLL power consumption on VDD	VCO freq =	VDD	-	180	500
		150MHz	VCORE	-	200	-

6.3.11 Memory characteristics

Flash memory

The characteristics are given at TJ = –40 to 125 °C unless otherwise specified.

The devices are shipped to customers with the flash memory erased.

Table 52. Flash memory characteristics

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
IDD		Write / Erase 8-bit mode	-	6.5	-
	Supply current	Write / Erase 16-bit mode		11.5	-	mA
		Write / Erase 32-bit mode	-	20	-
		Write / Erase 64-bit mode	-	35	-

^2. Guaranteed by characterization results.

^3. Integer mode only.

Table 53. Flash memory programming

Symbol	Parameter	Conditions	Min(1)	Typ	Max(1)	Unit
		Program/erase parallelism x 8	-	290	580(2)
	Word (266 bits) programming	Program/erase parallelism x 16	-	180	360	μs
tprog	time	Program/erase parallelism x 32	-	130	260
		Program/erase parallelism x 64	-	100	200
tERASE128KB		Program/erase parallelism x 8	-	2	4
	Sector (128 KB) erase time	Program/erase parallelism x 16	-	1.8	3.6
		Program/erase parallelism x 32	-	1.1	2.2
		Program/erase parallelism x 64	-	1	2
		Program/erase parallelism x 8	-	13	26	s
		Program/erase parallelism x 16	-	8	16
tME	Mass erase time	Program/erase parallelism x 32	-	6	12
		Program/erase parallelism x 64 Program parallelism x 8	-	5	10
Vprog	Programming voltage	Program parallelism x 16 Program parallelism x 32	1.62	-	3.6	V
		Program parallelism x 64	1.8	-	3.6

Table 54. Flash memory endurance and data retention

	Parameter Conditions		Value	Unit
Symbol
NEND	Endurance	TJ = –40 to +125 °C (6 suffix versions) 1 kcycle at TA = 85 °C	10 30	kcycles
tRET	Data retention	10 kcycles at TA = 55 °C	20	Years

^2. The maximum programming time is measured after 10K erase operations.

6.3.12 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A burst of fast transient voltage (positive and negative) is applied to V_DD and V_SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.

A device reset allows normal operations to be resumed.

The test results are given in Table 55. They are based on the EMS levels and classes defined in application note AN1709.

Symbol	Parameter	Conditions	Level/ Class
V FESD	Voltage limits to be applied on any I/O pin to induce a functional disturbance	V DD = 3.3 V, T A = +25 °C,	3B
V FTB	Fast transient voltage burst limits to be applied through 100 pF on V DD and V SS pins to induce a functional disturbance	UFBGA240, f rcccck = 400 MHz, conforms to IEC 61000-4-2	4B

Table 55. EMS characteristics

As a consequence, it is recommended to add a serial resistor (1k\Omega$ ) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB).

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading.

Table 56. EMI characteristics for fHSE = 8 MHz and fCPU = 400 MHz

Symbol	Parameter	Conditions	Monitored	Max vs. [fHSE/fCPU]	Unit
			frequency band	8/400 MHz
		VDD = 3.6 V, TA = 25 °C, UFBGA240 package, compliant with IEC61967-2	0.1 MHz to 30 MHz	6
SEMI	Peak (1)		30 MHz to 130 MHz 130 MHz to 1 GHz 1 GHz to 2 GHz	5 13 7	dBμV
	Level (2)		0.1 MHz to 2 GHz	2.5	-

^1. Refer to AN1709 "EMI radiated test" chapter.

^2. Refer to AN1709 "EMI level classification" chapter.

6.3.13 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002 standards.

Maximum Symbol Ratings Conditions Packages Class Unit value⁽¹⁾ Electrostatic discharge $T_A = +25$ °C conforming to voltage (human body ANSI/ESDA/JEDEC JS-ΑII 1C 1000 V_ESD(HBM) model) Electrostatic discharge $T_{\Lambda}$ = +25 °C conforming to ANSI/ESDA/JEDEC JSvoltage (charge device 250 V_ESD(CDM) ΑII C₁ 002 model)

Table 57. ESD absolute maximum ratings

Static latchup

Two complementary static tests are required on six parts to assess the latchup performance:

• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with JESD78 IC latchup standard.

Table 58. Electrical sensitivities

Symbol	Parameter	Conditions	Class
LU	Static latchup class	T A = +25 °C conforming to JESD78	II level A

6.3.14 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below $V_{SS}$ or above $V_{DD}(for standard, 3.3 V-capable I/O pins) should be avoided during the normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when an abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out

^1. Guaranteed by characterization results.

of-5~\mu\text{A}/+0~\mu\text{A}range), or other functional failure (for example reset, oscillator frequency deviation).

The following tables are the compilation of the SIC1/SIC2 and functional ESD results.

Negative induced A negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection.

Table 59. I/O current injection susceptibility⁽¹⁾

		Functional susceptibility
Symbol	Description	Negative injection
	PA7, PC5, PG1, PB14, PJ7, PA11, PA12, PA13, PA14, PA15, PJ12, PB4	5
	PA2, PH2, PH3, PE8, PA6, PA7, PC4, PE7, PE10, PE11	0
I INJ	PA0, PAC, PA1, PA1C, PC2, PC2C, PC3, PC3C, PA4, PA5, PH4, PH5, BOOT0	, PA4, 0
	All other I/Os	5

6.3.15 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 60: I/O static characteristics are derived from tests performed under the conditions summarized in Table 24: General operating conditions. All I/Os are CMOS and TTL compliant (except for BOOT0).

For information on GPIO configuration, refer to the application note AN4899 "STM32 GPIO configuration for hardware settings and low-power consumption" available from the ST website www.st.com.

Table 60. I/O static characteristics

Symbol	Parameter	Condition	Min	Typ	Max	Unit
V IL	I/O input low level voltage except BOOT0		-	-	0.3V DD (1)
	I/O input low level voltage except BOOT0	1.62 V <vDDIOx<3.6 V</v	-	-	0.4V DD - 0.1 (2)	٧
	BOOT0 I/O input low level voltage		-	-	0.19V DD + 0.1 (2)
V IH	I/O input high level voltage except BOOT0		0.7V DD (1)	-	-
	I/O input high level voltage except BOOT0 (3)	1.62 V <vDDIOx<3.6 V</v	0.47V DD + 0.25 (2)	-	-	٧
	BOOT0 I/O input high level voltage (3)		0.17V DD + 0.6 (2)	-	-
Symbol	Parameter	Condition	Min	Typ	Max	Unit
---------	------------------------------------------------	----------------------------------------	-----	-----	---------	------
VHYS(2)	TTxx, FTxxx and NRST I/O input hysteresis	1.62 V< VDDIOx <3.6 V	-	250	-	mV
	BOOT0 I/O input hysteresis		-	200	-
Ilkg(4)	FTxx Input leakage current(2)	(9) 0< VIN ≤ Max(VDDXXX)	-	-	+/-250
		Max(VDDXXX) < VIN ≤ 5.5 V (5)(6)(9)	-	-	1500
	FTu IO	(9) 0< VIN ≤ Max(VDDXXX)	-	-	+/- 350
		Max(VDDXXX) < VIN ≤ 5.5 V (5)(6)(9)	-	-	5000(7)	nA
	TTxx Input leakage current	(9) 0< VIN ≤ Max(VDDXXX)	-	-	+/-250
		0< VIN ≤ VDDIOX	-	-	15
	VPP (BOOT0 alternate function)	VDDIOX < VIN ≤ 9 V	-	-	35
RPU	Weak pull-up equivalent resistor(8)	VIN=VSS	30	40	50
RPD	Weak pull-down equivalent resistor(8)	VIN=VDD(9)	30	40	50	kΩ
CIO	I/O pin capacitance	-	-	5	-	pF

Table 60. I/O static characteristics (continued)

• 1. Compliant with CMOS requirement.
• 2. Guaranteed by design.
• 3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.
• 1. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following formula: ITotal_Ikg_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
• 5. All FT_xx IO except FT_lu, FT_u and PC3.
• 6. VIN must be less than Max(VDDXXX) + 3.6 V.
• 1. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be disabled.
• 8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order).
• 9. Max(VDDXXX) is the maximum value of all the I/O supplies.

All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 22.

Figure 22. V_IL/V_IH for all I/Os except BOOT0

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to\pm 8$ mA, and sink or source up to $\pm 20$ mA (with a relaxed $V_{OL}/V_{OH}$ ).

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular:

• The sum of the currents sourced by all the I/Os on $V_{DD}$ , plus the maximum Run consumption of the MCU sourced on $V_{DD}$ , cannot exceed the absolute maximum rating $\Sigma I_{VDD}(see Table 22).
• The sum of the currents sunk by all the I/Os on V_SS plus the maximum Run consumption of the MCU sunk on V_SS cannot exceed the absolute maximum rating ΣI_VSS (see Table 22).

Output voltage levels

Unless otherwise specified, the parameters given in Table 61 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions. All I/Os are CMOS and TTL compliant.

Table 61. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8(1)

Symbol	Parameter	Conditions(3)	Min	Max	Unit
VOL	Output low level voltage	CMOS port(2) IIO=8 mA 2.7 V≤ VDD ≤3.6 V	-	0.4
VOH	Output high level voltage	CMOS port(2) IIO=-8 mA 2.7 V≤ VDD ≤3.6 V	VDD-0.4	-
VOL(3)	Output low level voltage	TTL port(2) IIO=8 mA 2.7 V≤ VDD ≤3.6 V	-	0.4
VOH(3)	Output high level voltage	TTL port(2) IIO=-8 mA 2.7 V≤ VDD ≤3.6 V	2.4	-
VOL(3)	Output low level voltage	IIO=20 mA 2.7 V≤ VDD ≤3.6 V	-	1.3	V
VOH(3)	Output high level voltage	IIO=-20 mA 2.7 V≤ VDD ≤3.6 V	VDD-1.3	-
VOL(3)	Output low level voltage	IIO=4 mA 1.62 V≤ VDD ≤3.6 V	-	0.4
(3) VOH	Output high level voltage	IIO=-4 mA 1.62 V≤VDD<3.6 V	VDD--0.4	-
	Output low level voltage for an FTf I/O pin in FM+ mode	IIO= 20 mA 2.3 V≤ VDD≤3.6 V	-	0.4
VOLFM+(3)		IIO= 10 mA 1.62 V≤ VDD ≤3.6 V	-	0.4

^2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

^3. Guaranteed by design.

Table 62. Output voltage characteristics for PC13, PC14, PC15 and PI8(1)

Symbol	Parameter	Conditions(3)	Min	Max	Unit
VOL	Output low level voltage	CMOS port(2) IIO=3 mA 2.7 V≤ VDD ≤3.6 V	-	0.4
VOH	Output high level voltage	CMOS port(2) IIO=-3 mA 2.7 V≤ VDD ≤3.6 V	VDD-0.4	-
VOL(3)	Output low level voltage	TTL port(2) IIO=3 mA 2.7 V≤ VDD ≤3.6 V	-	0.4	V
VOH(3)	Output high level voltage	TTL port(2) IIO=-3 mA 2.7 V≤ VDD ≤3.6 V	2.4	-
VOL(3)	Output low level voltage	IIO=1.5 mA 1.62 V≤ VDD ≤3.6 V	-	0.4
VOH(3)	Output high level voltage	IIO=-1.5 mA 1.62 V≤ VDD ≤3.6 V	VDD-0.4	-

^2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

^3. Guaranteed by design.

Output buffer timing characteristics (HSLV option disabled)

The HSLV bit of SYSCFG_CCCSR register can be used to optimize the I/O speed when the product voltage is below 2.5 V.

Table 63. Output timing characteristics (HSLV OFF)(1)(2)

• Speed Symbol Parameter conditions Min Max Unit
• C=50 pF, 2.7 V≤ VDD≤3.6 V - 12
• C=50 pF, 1.62 V≤VDD≤2.7 V - 3
• C=30 pF, 2.7 V≤VDD≤3.6 V - 12
• Fmax(3) Maximum frequency C=30 pF, 1.62 V≤VDD≤2.7 V - 3 MHz
• C=10 pF, 2.7 V≤VDD≤3.6 V
  C=10 pF, 1.62 V≤VDD≤2.7 V - 16
• 00 - 4
• C=50 pF, 2.7 V≤ VDD≤3.6 V - 16.6
• C=50 pF, 1.62 V≤VDD≤2.7 V - 33.3
• Output high to low level
  (4)
  tr/tf
  fall time and output low
  to high level rise time C=30 pF, 2.7 V≤VDD≤3.6 V - 13.3
• C=30 pF, 1.62 V≤VDD≤2.7 V - 25 ns
• C=10 pF, 2.7 V≤VDD≤3.6 V - 10
• C=10 pF, 1.62 V≤VDD≤2.7 V - 20
• C=50 pF, 2.7 V≤ VDD≤3.6 V - 60
• C=50 pF, 1.62 V≤VDD≤2.7 V - 15
• C=30 pF, 2.7 V≤VDD≤3.6 V - 80
• Fmax(3) Maximum frequency C=30 pF, 1.62 V≤VDD≤2.7 V - 15 MHz
• C=10 pF, 2.7 V≤VDD≤3.6 V - 110
• C=10 pF, 1.62 V≤VDD≤2.7 V - 20
• 01 C=50 pF, 2.7 V≤ VDD≤3.6 V - 5.2
• C=50 pF, 1.62 V≤VDD≤2.7 V - 10
• (4) Output high to low level C=30 pF, 2.7 V≤VDD≤3.6 V - 4.2
• tr/tf fall time and output low
  to high level rise time C=30 pF, 1.62 V≤VDD≤2.7 V - 7.5 ns
• C=10 pF, 2.7 V≤VDD≤3.6 V - 2.8
• C=10 pF, 1.62 V≤VDD≤2.7 V - 5.2

Table 63. Output timing characteristics (HSLV OFF)⁽¹⁾⁽²⁾ (continued)

Speed	Symbol	Parameter	conditions	Min	Max	Unit
			C=50 pF, 2.7 V≤V DD ≤3.6 V (5) C=50 pF, 1.62 V≤V DD ≤2.7 V (5)	- -	85 35
	F (3)	Maximum fra accorde	C=30 pF, 2.7 V≤V DD ≤3.6 V (5)	-	110	T
	F max (3)	Maximum frequency	C=30 pF, 1.62 V≤V DD ≤2.7 V (5)	-	40	MHz
10		C=10 pF, 2.7 V≤V DD ≤3.6 V (5)	- C=10 pF, 1.62 V≤V DD ≤2.7 V (5)	166 -	85
10		C=50 pF, 1.62 V≤V DD ≤2.7 V (5)	C=50 pF, 2.7 V≤V DD ≤3.6 V (5) -	- 6.9	3.8
	. ,, (4)	t_r/t_f^{(4)}$ Output high to low level fall time and output low	C=30 pF, 2.7 V≤V DD ≤3.6 V (5)	-	2.8	no
	l r /lf` ′	to high level rise time C=50 pF, 2.7 V≤V DD ≤3.6 V (5)	C=30 pF, 1.62 V≤V DD ≤2.7 V (5) C=10 pF, 2.7 V≤V DD ≤3.6 V (5) C=10 pF, 1.62 V≤V DD ≤2.7 V (5) - C=50 pF, 1.62 V≤V DD ≤2.7 V (5)	- - - 100 -	5.2 1.8 3.3 50	- ns
	F (3)	Maximum fraguancy	C=30 pF, 2.7 V≤V DD ≤3.6 V (5)	-	133	MHz
	F max (3)	Maximum frequency	C=30 pF, 1.62 V≤V DD ≤2.7 V (5) C=10 pF, 2.7 V≤V DD ≤3.6 V (5)	- -	66 220	IVITZ
11			C=10 pF, 1.62 V≤V DD ≤2.7 V (5)	-	100
11			C=50 pF, 2.7 V≤V DD ≤3.6 V (5) C=50 pF, 1.62 V≤V DD ≤2.7 V (5)	- -	3.3 6.6
	t r /t f (4)	Output high to low level fall time and output low	C=30 pF, 2.7 V≤V DD ≤3.6 V (5)	-	2.4	no
	լ Կ / Կ՝ ′	to high level rise time	C=30 pF, 1.62 V≤V DD ≤2.7 V (5) C=10 pF, 2.7 V≤V DD ≤3.6 V (5) C=10 pF, 1.62 V≤V DD ≤2.7 V (5)	- - -	4.5 1.5 2.7	ns

5. Compensation system enabled.

^2. The frequency of the GPIOs that can be supplied in $V_{BAT}$ mode (PC13, PC14, PC15 and PI8) is limited to 2 MHz

^3. The maximum frequency is defined with the following conditions: $(t_r+t_f) \le 2/3$ T Skew $\le 1/20$ T 45%<Duty cycle<55%

^4. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.

Output buffer timing characteristics (HSLV option enabled)

Table 64. Output timing characteristics (HSLV ON)⁽¹⁾

• Speed Symbol Parameter conditions Min Max Unit
• C=50 pF, 1.62 V≤V _DD ≤2.7 V - 10
• F _max ⁽²⁾ Maximum frequency C=30 pF, 1.62 V≤V _DD ≤2.7 V - 10 MHz
• 00 C=10 pF, 1.62 V≤V _DD ≤2.7 V - 10
• 00 Output high to low level C=50 pF, 1.62 V≤V _DD ≤2.7 V - 11
• $t_r/t_f^{(3)}$ fall time and output low C=30 pF, 1.62 V≤V _DD ≤2.7 V - 9 ns
• to high level rise time C=10 pF, 1.62 V≤V _DD ≤2.7 V - 6.6
• C=50 pF, 1.62 V≤V _DD ≤2.7 V - 50
• F _max ⁽²⁾ Maximum frequency C=30 pF, 1.62 V≤V _DD ≤2.7 V - 58 MHz
• 01 C=10 pF, 1.62 V≤V _DD ≤2.7 V - 66
• 01 $t_r/t_f^{(3)}$ Output high to low level C=50 pF, 1.62 V≤V _DD ≤2.7 V - 6.6
• t _r /t _f ⁽³⁾ fall time and output low to high level rise time C=30 pF, 1.62 V≤V _DD ≤2.7 V - 4.8 ns
• C=10 pF, 1.62 V≤V _DD ≤2.7 V - 3
• C=50 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 55
• F _max ⁽²⁾ Maximum frequency C=30 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 80 MHz
• 10 C=10 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 133 1
• 10 Output high to low level C=50 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 5.8
• $t_r/t_f^{(3)}$ fall time and output low C=30 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 4 ns
• to high level rise time C=10 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 2.4
• C=50 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 60
• F _max ⁽²⁾ Maximum frequency C=30 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 90 MHz
• 11 C=10 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 175
• '' Output high to low level C=50 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 5.3
• $t_r/t_f^{(3)}$ fall time and output low C=30 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 3.6 ns
• to high level rise time C=10 pF, 1.62 V≤V _DD ≤2.7 V ⁽⁴⁾ - 1.9

^1. Guaranteed by design.

• 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively.
• 4. Compensation system enabled.

^2. The maximum frequency is defined with the following conditions: $(t_r + t_f) \le 2/3 \text{ T}$ Skew $\le 1/20 \text{ T}45%<Puty cycle<55%

6.3.16 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 60: I/O static characteristics).

Unless otherwise specified, the parameters given in Table 65 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 24: General operating conditions.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
RPU(2)	Weak pull-up equivalent resistor(1)	VIN = VSS	30	40	50	㏀
VF(NRST)(2)	NRST Input filtered pulse	1.71 V < VDD < 3.6 V	-	-	50
VNF(NRST)(2)	NRST Input not filtered pulse	1.71 V < VDD < 3.6 V	300	-	-	ns
		1.62 V < VDD < 3.6 V	1000	-	-

2. Guaranteed by design.

Figure 23. Recommended NRST pin protection

• 1. The reset network protects the device against parasitic resets.
• 1. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 60. Otherwise the reset is not taken into account by the device.

^1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order).

6.3.17 FMC characteristics

Unless otherwise specified, the parameters given in Table 66 to Table 79 for the FMC interface are derived from tests performed under the ambient temperature,f_{rcc_c_ck}$ frequency and $V_{DD}$ supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5V_DD

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

Asynchronous waveforms and timings

Figure 24 through Figure 27 represent asynchronous waveforms and Table 66 through Table 73 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• BusTurnAroundDuration = 0x0
• Capcitive load C_I = 30 pF

In all timing tables, the $T_{\mbox{\scriptsize KERCK}}$ is the $f_{\mbox{\scriptsize mc}}$ ker $_{\mbox{\scriptsize ck}}clock period.

Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	2Tfmckerck - 1	2 Tfmckerck +1
tv(NOENE)	FMCNEx low to FMCNOE low	0	0.5
tw(NOE)	FMCNOE low time	2Tfmckerck - 1	2Tfmckerck + 1
th(NENOE)	FMCNOE high to FMCNE high hold time	0	-
tv(ANE)	FMCNEx low to FMCA valid	-	0.5
th(ANOE)	Address hold time after FMCNOE high	0	-
tv(BLNE)	FMCNEx low to FMCBL valid	-	0.5
th(BLNOE)	FMCBL hold time after FMCNOE high	0	-	ns
tsu(DataNE)	Data to FMCNEx high setup time	11	-
tsu(DataNOE)	Data to FMCNOEx high setup time	11	-
th(DataNOE)	Data hold time after FMCNOE high	0	-
th(DataNE)	Data hold time after FMCNEx high	0	-
tv(NADVNE)	FMCNEx low to FMCNADV low	-	0
tw(NADV)	FMCNADV low time	-	Tfmckerck + 1

Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1)(2)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	7Tfmckerck +1	7Tfmckerck +1
tw(NOE)	FMCNWE low time	5Tfmckerck -1	5Tfmckerck +1	ns
tw(NWAIT)	FMCNWAIT low time	Tfmckerck -0.5
tsu(NWAITNE)	FMCNWAIT valid before FMCNEx high	4Tfmckerck +11	-
th(NENWAIT)	FMCNEx hold time after FMCNWAIT invalid	3Tfmckerck+11.5	-

^2. NWAIT pulse width is equal to 1 AHB cycle.

Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms

1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.

Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	3Tfmckerck - 1	3Tfmckerck
tv(NWENE)	FMCNEx low to FMCNWE low	Tfmckerck	Tfmckerck + 1
tw(NWE)	FMCNWE low time	Tfmckerck - 0.5	Tfmckerck + 0.5
th(NENWE)	FMCNWE high to FMCNE high hold time	Tfmckerck	-
tv(ANE)	FMCNEx low to FMCA valid	-	2
th(ANWE)	Address hold time after FMCNWE high	Tfmckerck - 0.5	-	ns
tv(BLNE)	FMCNEx low to FMCBL valid	-	0.5
th(BLNWE)	FMCBL hold time after FMCNWE high	Tfmckerck - 0.5	-
tv(DataNE)	Data to FMCNEx low to Data valid	-	Tfmckerck + 2.5
th(DataNWE)	Data hold time after FMCNWE high	Tfmckerck+0.5	-
tv(NADVNE)	FMCNEx low to FMCNADV low	-	0
tw(NADV)	FMCNADV low time	-	Tfmckerck + 1

Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1)(2)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	8Tfmckerck - 1	8Tfmckerck + 1
tw(NWE)	FMCNWE low time	6Tfmckerck - 1.5	6Tfmckerck + 0.5	ns
tsu(NWAITNE)	FMCNWAIT valid before FMCNEx high	5Tfmckerck + 13	-
th(NENWAIT)	FMCNEx hold time after FMCNWAIT invalid	4Tfmckerck+ 13	-

Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms

Table 70. Asynchronous multiplexed PSRAM/NOR read timings(1)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	3Tfmckerck - 1	3Tfmckerck + 1
tv(NOENE)	FMCNEx low to FMCNOE low	2Tfmckerck	2Tfmckerck + 0.5
ttw(NOE)	FMCNOE low time	Tfmckerck - 1	Tfmckerck + 1
th(NENOE)	FMCNOE high to FMCNE high hold time	0	-
tv(ANE)	FMCNEx low to FMCA valid	-	0.5
tv(NADVNE)	FMCNEx low to FMCNADV low	0	0.5
tw(NADV)	FMCNADV low time	Tfmckerck - 0.5	Tfmckerck+1
th(ADNADV)	FMCAD(address) valid hold time after FMCNADV high	Tfmckerck + 0.5	-	ns
th(ANOE)	Address hold time after FMCNOE high	Tfmckerck - 0.5	-
th(BLNOE)	FMCBL time after FMCNOE high	0	-
tv(BLNE)	FMCNEx low to FMCBL valid	-	0.5
tsu(DataNE)	Data to FMCNEx high setup time	Tfmckerck - 2	-
tsu(DataNOE)	Data to FMCNOE high setup time	Tfmckerck - 2	-
th(DataNE)	Data hold time after FMCNEx high	0	-
th(DataNOE)	Data hold time after FMCNOE high	0	-

Table 71. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	8Tfmckerck - 1	8Tfmckerck
tw(NOE)	FMCNWE low time	5Tfmckerck - 1.5	5Tfmckerck + 0.5	ns
tsu(NWAITNE)	FMCNWAIT valid before FMCNEx high	5Tfmckerck + 3	-
th(NENWAIT)	FMCNEx hold time after FMCNWAIT invalid	4Tfmckerck	-

Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms

Table 72. Asynchronous multiplexed PSRAM/NOR write timings(1)

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	4Tfmckerc - 1	4Tfmckerck
tv(NWENE)	FMCNEx low to FMCNWE low	Tfmckerc - 1	Tfmckerck + 0.5
tw(NWE)	FMCNWE low time	2Tfmckerck- 0.5	2Tfmckerck+ 0.5
th(NENWE)	FMCNWE high to FMCNE high hold time	Tfmckerck - 0.5	-
tv(ANE)	FMCNEx low to FMCA valid	-	0
tv(NADVNE)	FMCNEx low to FMCNADV low	0	0.5
tw(NADV)	FMCNADV low time	Tfmckerck	Tfmckerck+ 1	ns
th(ADNADV)	FMCAD(address) valid hold time after FMCNADV high	Tfmckerck+0.5	-
th(ANWE)	Address hold time after FMCNWE high	Tfmckerck+0.5	-
th(BLNWE)	FMCBL hold time after FMCNWE high	Tfmckerck - 0.5	-
tv(BLNE)	FMCNEx low to FMCBL valid	-	0.5
tv(DataNADV)	FMCNADV high to Data valid	-	Tfmckerck + 2
th(DataNWE)	Data hold time after FMCNWE high	Tfmckerck+0.5	-

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMCNE low time	9Tfmckerck – 1	9Tfmckerck
t w(NWE)	FMCNWE low time	7Tfmckerck – 0.5	7Tfmckerck + 0.5	ns
tsu(NWAITNE)	FMCNWAIT valid before FMCNEx high	6Tfmckerck + 3	-
th(NENWAIT)	FMCNEx hold time after FMCNWAIT invalid	4Tfmckerck	-

Synchronous waveforms and timings

Figure 28 through Figure 31 represent synchronous waveforms and Table 74 through Table 77 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration:

• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM

In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK maximum values:

• For 2.7 V<VDD<3.6 V, FMC_CLK =100 MHz at 20 pF
• For 1.8 V<VDD<1.9 V, FMC_CLK =100 MHz at 20 pF
• For 1.62 V<VDD<1.8 V, FMC_CLK =100 MHz at 15 pF

^1. Guaranteed by characterization results.

Figure 28. Synchronous multiplexed NOR/PSRAM read timings

Table 74. Synchronous multiplexed NOR/PSRAM read timings(1)

Symbol	Parameter	Min	Max	Unit
tw(CLK)	FMCCLK period	2Tfmckerck - 1	-
td(CLKL-NExL)	FMCCLK low to FMCNEx low (x=02)	-	1
td(CLKHNExH)	FMCCLK high to FMCNEx high (x= 0…2)	Tfmckerck + 0.5	-
td(CLKL-NADVL)	FMCCLK low to FMCNADV low	-	1.
td(CLKL-NADVH)	FMCCLK low to FMCNADV high	0	-
td(CLKL-AV)	FMCCLK low to FMCAx valid (x=16…25)	-	2.5
td(CLKH-AIV)	FMCCLK high to FMCAx invalid (x=16…25)	Tfmckerck	-
td(CLKL-NOEL)	FMCCLK low to FMCNOE low	-	1.5	ns
td(CLKH-NOEH)	FMCCLK high to FMCNOE high	Tfmckerck - 0.5	-
td(CLKL-ADV)	FMCCLK low to FMCAD[15:0] valid	-	3
td(CLKL-ADIV)	FMCCLK low to FMCAD[15:0] invalid	0	-
tsu(ADV-CLKH)	FMCA/D[15:0] valid data before FMCCLK high	3	-
th(CLKH-ADV)	FMCA/D[15:0] valid data after FMCCLK high	0	-
tsu(NWAIT-CLKH)	FMCNWAIT valid before FMCCLK high	3	-
th(CLKH-NWAIT)	FMCNWAIT valid after FMCCLK high	1	-

Figure 29. Synchronous multiplexed PSRAM write timings

Table 75. Synchronous multiplexed PSRAM write timings(1)

Symbol	Parameter	Min	Max	Unit
tw(CLK)	FMCCLK period	2Tfmckerck - 1	-
td(CLKL-NExL)	FMCCLK low to FMCNEx low (x=02)	-	1
td(CLKH-NExH)	FMCCLK high to FMCNEx high (x= 0…2)	Tfmckerck + 0.5	-
td(CLKL-NADVL)	FMCCLK low to FMCNADV low	-	1.5
td(CLKL-NADVH)	FMCCLK low to FMCNADV high	0	-
td(CLKL-AV)	FMCCLK low to FMCAx valid (x=16…25)	-	2
td(CLKH-AIV)	FMCCLK high to FMCAx invalid (x=16…25)	Tfmckerck	-
td(CLKL-NWEL)	FMCCLK low to FMCNWE low	-	1.5
t(CLKH-NWEH)	FMCCLK high to FMCNWE high	Tfmckerck + 0.5	-	ns
td(CLKL-ADV)	FMCCLK low to FMCAD[15:0] valid	-	2.5
td(CLKL-ADIV)	FMCCLK low to FMCAD[15:0] invalid	0	-
td(CLKL-DATA)	FMCA/D[15:0] valid data after FMCCLK low	-	2.5
td(CLKL-NBLL)	FMCCLK low to FMCNBL low	-	2
td(CLKH-NBLH)	FMCCLK high to FMCNBL high	Tfmckerck + 0.5	-
tsu(NWAIT-CLKH)	FMCNWAIT valid before FMCCLK high	2	-
th(CLKH-NWAIT)	FMCNWAIT valid after FMCCLK high	2	-

Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings

Table 76. Synchronous non-multiplexed NOR/PSRAM read timings⁽¹⁾

Symbol	Parameter	Min	Max	Unit
t w(CLK)	FMCCLK period	2T fmckerck - 1	-
t (CLKL-NExL)	FMCCLK low to FMCNEx low (x=02)	-	2
t d(CLKH-NExH)	FMCCLK high to FMCNEx high (x= 02)	T fmckerck + 0.5	-
t d(CLKL-NADVL)	FMCCLK low to FMCNADV low	-	0.5
t d(CLKL-NADVH)	FMCCLK low to FMCNADV high	0	-
t d(CLKL-AV)	FMCCLK low to FMCAx valid (x=1625)	-	2
t d(CLKH-AIV)	FMCCLK high to FMCAx invalid (x=1625)	T fmckerck	-	ns
t d(CLKL-NOEL)	FMCCLK low to FMCNOE low	-	1.5
t d(CLKH-NOEH)	FMCCLK high to FMCNOE high	T fmckerck + 0.5	-
t su(DV-CLKH)	FMCD[15:0] valid data before FMCCLK high	3	-
t h(CLKH-DV)	t h(CLKH-DV) FMCD[15:0] valid data after FMCCLK high		-
t SU(NWAIT-CLKH)	FMCNWAIT valid before FMCCLK high	3	-
t h(CLKH-NWAIT)	FMCNWAIT valid after FMCCLK high	1	-

Figure 31. Synchronous non-multiplexed PSRAM write timings

Table 77. Synchronous non-multiplexed PSRAM write timings⁽¹⁾

Symbol	Parameter	Min	Max	Unit
t (CLK)	FMCCLK period	2T fmckerck - 1	-
t d(CLKL-NExL)	FMCCLK low to FMCNEx low (x=02)	-	2
t (CLKH-NExH)	FMCCLK high to FMCNEx high (x= 02)	T fmckerck + 0.5	-
t d(CLKL-NADVL)	FMCCLK low to FMCNADV low	-	0.5
t d(CLKL-NADVH)	FMCCLK low to FMCNADV high	0	-
t d(CLKL-AV)	FMCCLK low to FMCAx valid (x=1625)	-	2
t d(CLKH-AIV)	FMCCLK high to FMCAx invalid (x=1625)	T fmckerck	-	ns
t d(CLKL-NWEL)	FMCCLK low to FMCNWE low	-	1.5	115
t d(CLKH-NWEH)	FMCCLK high to FMCNWE high	T fmckerck + 1	-
t d(CLKL-Data)	FMCD[15:0] valid data after FMCCLK low	-	3.5
t d(CLKL-NBLL)	FMCCLK low to FMCNBL low	-	2
t d(CLKH-NBLH)	FMCCLK high to FMCNBL high	T fmckerck + 1	-
t su(NWAIT-CLKH)	FMCNWAIT valid before FMCCLK high	2	-
t h(CLKH-NWAIT)	FMCNWAIT valid after FMCCLK high	2	-

DS12110 Rev 10 159/357

NAND controller waveforms and timings

Figure 32 through Figure 35 represent synchronous waveforms, and Table 78 and Table 79 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration:

• COM.FMC SetupTime = 0x01
• COM.FMC_WaitSetupTime = 0x03
• COM.FMC HoldSetupTime = 0x02
• COM.FMC HiZSetupTime = 0x01
• ATT.FMC SetupTime = 0x01
• ATT.FMC_WaitSetupTime = 0x03
• ATT.FMC_HoldSetupTime = 0x02
• ATT.FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth₁6b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC ECCPageSize 512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
• C_I = 30 pF

In all timing tables, the T_{fmc ker ck} is the fmc_ker_ck clock period.

Figure 32. NAND controller waveforms for read access

FMC_NCEX

ALE (FMC_A17) CLE (FMC_A16)

FMC_NWE

Th(NWE-ALE)

FMC_NOE (NRE)

Th(NWE-B)

Th(NWE-B)

MS32768V1

Figure 33. NAND controller waveforms for write access

Figure 35. NAND controller waveforms for common memory write access

Table 78. Switching characteristics for NAND flash read cycles⁽¹⁾

Symbol	Parameter	Min	Max	Unit
t w(N0E)	FMCNOE low width	4T fmckerck -0.5	4T fmckerck + 0.5
t su(D-NOE)	FMCD[15-0] valid data before FMCNOE high	8	-
t h(NOE-D)	FMCD[15-0] valid data after FMCNOE high	0	-	ns
t d(ALE-NOE)	FMCALE valid before FMCNOE low	-	3T fmckerck + 1
t h(NOE-ALE)	FMCNWE high to FMCALE invalid	4T fmckerck - 2	-

Table 79. Switching characteristics for NAND flash write cycles⁽¹⁾

Symbol	Parameter	Min	Max	Unit
t w(NWE)	FMCNWE low width	4T fmckerck - 0.5	4T fmckerck + 0.5
t v(NWE-D)	FMCNWE low to FMCD[15-0] valid	0	-
t h(NWE-D)	FMCNWE high to FMCD[15-0] invalid	2T fmckerck - 0.5	-	ns
t d(D-NWE)	FMCD[15-0] valid before FMCNWE high	5T fmckerck - 1	-	115
t d(ALE-NWE)	FMCALE valid before FMCNWE low	-	3T fmckerck + 0.5
t h(NWE-ALE)	FMCNWE high to FMCALE invalid	2T fmckerck - 1	-

SDRAM waveforms and timings

In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_SDCLK maximum values:

• For 1.8 V < VDD < 3.6V: FMC_SDCLK = 100 MHz at 20 pF
• For 1.62 V< VDD < 1.8 V, FMC_SDCLK = 100 MHz at 15 pF

Figure 36. SDRAM read access waveforms (CL = 1)

Table 80. SDRAM read timings(1)

Symbol	Parameter	Min	Max	Unit
tw(SDCLK)	FMCSDCLK period	2Tfmckerck - 1	2Tfmckerck + 0.5
tsu(SDCLKH Data)	Data input setup time	3	-
th(SDCLKHData)	Data input hold time	0	-
td(SDCLKLAdd)	Address valid time	-	1.5
td(SDCLKL- SDNE)	Chip select valid time	-	1.5	ns
th(SDCLKLSDNE)	Chip select hold time	0.5	-
td(SDCLKLSDNRAS)	SDNRAS valid time	-	1
th(SDCLKLSDNRAS)	SDNRAS hold time	0.5	-
td(SDCLKLSDNCAS)	SDNCAS valid time	-	0.5
th(SDCLKLSDNCAS)	SDNCAS hold time	0	-

DS12110 Rev 10 163/357

Table 81. LPSDR SDRAM read timings(1)

Symbol	Parameter	Min	Max	Unit
tW(SDCLK)	FMCSDCLK period	2Tfmckerck - 1	2Tfmckerck + 0.5
tsu(SDCLKHData)	Data input setup time	3	-
th(SDCLKHData)	Data input hold time	0.5	-
td(SDCLKLAdd)	Address valid time	-	2.5
td(SDCLKLSDNE)	Chip select valid time -		2.5	ns
th(SDCLKLSDNE)	Chip select hold time	0	-
td(SDCLKLSDNRAS	SDNRAS valid time	-	0.5
th(SDCLKLSDNRAS)	SDNRAS hold time	0	-
td(SDCLKLSDNCAS)	SDNCAS valid time	-	1.5
th(SDCLKLSDNCAS)	SDNCAS hold time	0	-

Figure 37. SDRAM write access waveforms

Table 82. SDRAM write timings(1)

Symbol	Parameter	Min	Max	Unit
tw(SDCLK)	FMCSDCLK period	2Tfmckerck - 1	2Tfmckerck + 0.5
td(SDCLKL Data)	Data output valid time	-	3
th(SDCLKL Data)	Data output hold time	0	-
td(SDCLKLAdd)	Address valid time	-	1.5
td(SDCLKLSDNWE)	SDNWE valid time	-	1.5
th(SDCLKLSDNWE)	SDNWE hold time	0.5	-	ns
td(SDCLKL_ SDNE)	Chip select valid time	-	1.5
th(SDCLKLSDNE)	Chip select hold time	0.5	-
td(SDCLKLSDNRAS)	SDNRAS valid time	-	1
th(SDCLKLSDNRAS)	SDNRAS hold time	0.5	-
td(SDCLKLSDNCAS)	SDNCAS valid time	-	1
td(SDCLKLSDNCAS)	SDNCAS hold time	0.5	-

Table 83. LPSDR SDRAM write timings(1)

Symbol	Parameter	Min	Max	Unit
tw(SDCLK)	FMCSDCLK period	2Tfmckerck - 1	2Tfmckerck + 0.5
td(SDCLKL Data)	Data output valid time	-	2.5
th(SDCLKL Data)	Data output hold time	0	-
td(SDCLKLAdd)	Address valid time	-	2.5
td(SDCLKL-SDNWE)	SDNWE valid time	-	2.5
th(SDCLKL-SDNWE)	SDNWE hold time	0	-	ns
td(SDCLKL- SDNE)	Chip select valid time	-	3
th(SDCLKL- SDNE)	Chip select hold time	0	-
td(SDCLKL-SDNRAS)	SDNRAS valid time	-	1.5
th(SDCLKL-SDNRAS)	SDNRAS hold time	0	-
td(SDCLKL-SDNCAS)	SDNCAS valid time	-	1.5
td(SDCLKL-SDNCAS)	SDNCAS hold time	0	-

6.3.18 Quad-SPI interface characteristics

Unless otherwise specified, the parameters given in Table 84 and Table 85 for QUADSPI are derived from tests performed under the ambient temperature,f_{rcc_c_ck}$ frequency and $V_{DD}$ supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5V_DD
• I/O compensation cell enabled
• HSLV activated when V_DD≤2.7 V

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics.

Table 84. QUADSPI characteristics in SDR mode⁽¹⁾

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Fck1/T CK	QUADSPI clock frequency	$2.7 \text{ V} \le \text{V}{DD} < 3.6 \text{ V}$ $\text{C}{L} = 20 \text{ pF}	-	-	133	MHz
	QUADOI I Glock frequency	1.62 V <vDD<3.6 V CL=15 pF</v	-	-	100	IVIMZ
t w(CKH)	QUADSPI clock high and low	_	T CK /2-0.5	-	T CK /2
t w(CKL)	time	-	T CK /2	ı	T CK /2 + 0.5
+	Data input actum time	2.7 \text{ V} \le \text{V}_{DD} < 3.6 \text{ V}$	2	-	-
t s(IN)	Data input setup time	1.62 V ≤ V DD < 3.6 V	2.5	-	-	no
4	Data input hold time	2.7 V ≤ V DD < 3.6 V	1	-	-	ns
t h(IN)	Data input noid time	1.62 V ≤ V DD < 3.6 V	1.5	-	-
t v(OUT)	Data output valid time	-	-	1.5	2
t h(OUT)	Data output hold time	-	0.5	-	-

Table 85. QUADSPI characteristics in DDR mode⁽¹⁾

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
E	QUADSPI clock	2.7 V <vDD<3.6 V CL=20 pF</v	-	-	100	MHz
F ck1/t(CK)	frequency	1.62 V <vDD<3.6 V CL=15 pF</v	-	-	100	IVIITZ
t w(CKH)	QUADSPI clock high and		$T_{CK}/2 - 0.5$	-	T CK /2
t w(CKL)	low time	-	T CK /2	-	T CK /2+0.5
	Data input setup time	$2.7 \text{ V} \le \text{V}_{DD} < 3.6 \text{ V}$	3	-	-
$t_{sr(IN)}, t_{sf(IN)}$		1.62 V ≤ V DD < 3.6 V	1	-	-
+ +	Data in a standard fine	$2.7 \text{ V} \le \text{V}_{DD} < 3.6 \text{ V}	1	-	-
t hr(IN) , t hf(IN)	Data input hold time	1.62 V ≤ V DD < 3.6 V	1.5	-	-	ns
		DHHC=0	-	3.5	4
t vr(OUT) , t vf(OUT)	Data output valid time	DHHC=1 Pres=1, 2	-	T CK /4+3.5	T CK /4+4
1	Data output hold time	DHHC=0	3	-	-
t hr(OUT) , t hf(OUT)		DHHC=1 Pres=1, 2	T CK /4+3	-	-

Figure 38. Quad-SPI timing diagram - SDR mode

Figure 39. Quad-SPI timing diagram - DDR mode

6.3.19 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 87 for the delay block are derived from tests performed under the ambient temperature,f_{rcc_c_ck}$ frequency and $V_{DD}$ supply voltage summarized in Table 24: General operating conditions.

Table 86. Dynamics characteristics: Delay Block characteristics⁽¹⁾

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
t init	Initial delay	-	1400	2200	2400	ps
$t_\Delta$	Unit Delay	-	35	40	45	ρs

^1. Guaranteed by characterization results.

6.3.20 16-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 87 are derived from tests performed under the ambient temperature, $f_{PCLK2}$ frequency and $V_{DDA}$ supply voltage conditions summarized in Table 24: General operating conditions.

Table 87. ADC characteristics⁽¹⁾

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
$V_{DDA}$	Analog power supply	-	-		-	3.6
V REF+	Positive reference voltage	V DDA ≥	2 V	2	-	$V_{DDA}$	V
VREF+	1 ositive reference voltage	V DDA < 2 V			$V_{DDA}$		V
$V_{REF}$	Negative reference voltage	-			$V_{SSA}$
f	ADC clock frequency 2 V	2 V ≤ V DDA ≤ 3.3 V	BOOST = 1	-	-	36	MHz
f ADC	ADC Glock frequency	2 V = V DDA = 3.3 V	BOOST = 0	-	-	20	IVII IZ
		16-bit resol	ution	-	-	3.60 (2)
	Sampling rate for Fast channels, BOOST = 1, f ADC = 36 MHz (2)	14-bit resolution		-	-	4.00 (2)
		12-bit resolution		-	-	4.50 (2)
		10-bit resolution		-	-	5.00 (2)
		8-bit resolution		-	-	6.00 (2)
		16-bit resolution		-	-	2.00 (2)
	Sampling rate for Fast	14-bit resolution		-	-	2.20 (2)
$f_S	channels, BOOST = 0,	12-bit resol	ution	-	-	2.50 (2)	MSPS
	f ADC = 20 MHz	10-bit resol	ution	-	-	2.80 (2)
		8-bit resolu	ution	-	-	3.30 (2)
		16-bit resol	ution	-	-	1.00
	Sampling rate for Slow	14-bit resolution		-	-	1.00
	channels, BOOST = 0,			-	-	1.00
	f ADC = 10 MHz	10-bit resolution		-	-	1.00
		8-bit resolu	ution	-	-	1.00	ı

Table 87. ADC characteristics⁽¹⁾ (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
f	External trigger frequency	f ADC = 36 MHz	-	-	3.6	MHz
f TRIG	External trigger frequency	16-bit resolution	-	-	10	1/f ADC
V AIN (3)	Conversion voltage range	-	0	-	V REF+
V CMIV	Common mode input voltage	-	V REF /2- 10% V REF /2 V REF /2+ 10%		V REF /2+ 10%	V
R AIN	External input impedance	-	-	-	50	kΩ
C ADC	Internal sample and hold capacitor	-	-	4	-	pF
t ADCREG_ STUP	ADC LDO startup time	-	-	5	10	μs
t STAB	ADC power-up time	LDO already started		1
t CAL	Offset and linearity calibration time	-		165,010
t OFFCAL	Offset calibration time	-		1,280
	Trigger conversion latency	CKMODE = 00	1.5	2	2.5
	for regular and injected	CKMODE = 01	-	-	2
t LATR	channels without aborting the conversion	CKMODE = 10			2.25
	the conversion	CKMODE = 11			2.125	1/f ADC
	Trianger conversion leteral	CKMODE = 00	2.5	3	3.5
	Trigger conversion latency for regular and injected	CKMODE = 01	-	-	3
t LATRINJ	channels when a regular	CKMODE = 10	-	-	3.25
	conversion is aborted	CKMODE = 11	-	-	3.125	ļ
t S	Sampling time	-	1.5	-	810.5
t CONV	Total conversion time (including sampling time)	N-bit resolution	_	+ 0.5 + N 8 cycles mode)

^2. These values are obtained using the following formula:f_S = f_{ADC}/t_{CONV}$ , where $f_{ADC} = 36$ MHz and $t_{CONV} = 1,5$ cycle sampling time + $t_{SAR}$ sampling time. Refer to the product reference manual for the value of $t_{SAR}$ depending on resolution.

^3. Depending on the package, $V_{REF+}$ can be internally connected to $V_{DDA}$ and $V_{REF-}$ to $V_{SSA}.

Table 88. ADC accuracy(1)(2)(3)

Symbol	Parameter		Conditions(4)	Min	Typ	Max	Unit
		Single	BOOST = 1	-	±6	-
	Total	ended	BOOST = 0	-	±8	-
ET	unadjusted error		BOOST = 1	-	±10	-
		Differential	BOOST = 0	-	±16	-
		Single	BOOST = 1	-	2	-
	Differential	ended	BOOST = 0	-	1	-
ED	linearity error		BOOST = 1	-	8	-	±LSB
		Differential	BOOST = 0	-	2	-
		Single	BOOST = 1	-	±6	-
	Integral	ended	BOOST = 0	-	±4	-
EL	error	linearity	BOOST = 1	-	±6	-
				Differential	BOOST = 0	-	±4
	Effective number of bits (2 MSPS)		Single	BOOST = 1	-	11.6	-
ENOB(5)		ended	BOOST = 0	-	12	-
			BOOST = 1	-	13.3	-	bits
				Differential	BOOST = 0	-	13.5
	Signal-to	Single	BOOST = 1	-	71.6	-
SINAD(5)	noise and distortion	ended	BOOST = 0	-	74	-
	ratio		BOOST = 1	-	81.83	-
	(2 MSPS)	Differential	BOOST = 0	-	83	-
		Single	BOOST = 1	-	72	-
SNR(5)	Signal-to noise ratio	ended	BOOST = 0	-	74	-
	(2 MSPS)		BOOST = 1	-	82	-	dB
		Differential	BOOST = 0	-	83	-
		Single	BOOST = 1	-	-78	-
THD(5)	Total	ended	BOOST = 0	-	-80	-
	harmonic distortion		BOOST = 1	-	-90	-
		Differential	BOOST = 0	-	-95	-

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion

being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified forI_{INJ(PIN)}$ and $\Sigma I_{INJ(PIN)}in Section 6.3.14 does not affect the ADC accuracy.

Figure 40. ADC accuracy characteristics

Figure 41. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function

• 1. Refer to Section 6.3.20: 16-bit ADC characteristics for the values of RAIN and CADC.
• C_parasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 60: I/O static characteristics for the value of the pad capacitance). A high C_parasitic value downgrades conversion accuracy. To remedy this, f_ADC should be reduced.
• 1. Refer to Table 60: I/O static characteristics for the value of I_Ika.
• 1. Refer to Figure 15: Power supply scheme.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 42 or Figure 43, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip.

Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA) MSv50648V2 1 μF // 100 nF 1 μF // 100 nF STM32 VREF+(1) VSSA/VREF-(1) VDDA

1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.

1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA.

6.3.21 DAC electrical characteristics

Table 89. DAC characteristics(1)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
VDDA	Analog supply voltage		-	1.8	3.3	3.6
VREF+	Positive reference voltage		-	1.80	-	VDDA	V
VREF	Negative reference voltage	-		-	VSSA	-
		DAC output	connected to VSSA	5	-	-
RL	Resistive Load	buffer ON	connected to VDDA	25	-	-	㏀
(2) RO	Output Impedance		DAC output buffer OFF	10.3	13	16
	Output impedance sample		VDD = 2.7 V	-	-	1.6
RBON	and hold mode, output buffer ON	DAC output buffer ON	VDD = 2.0 V	-	-	2.6	㏀
	Output impedance sample	DAC output	VDD = 2.7 V	-	-	17.8
RBOFF	and hold mode, output buffer OFF	buffer OFF	VDD = 2.0 V	-	-	18.7	㏀
(2) CL			DAC output buffer OFF	-	-	50	pF
CSH(2)	Capacitive Load		Sample and Hold mode	-	0.1	1	μF
VDACOUT	Voltage on DACOUT		DAC output buffer ON	0.2	-	VREF+ -0.2	V
	output		DAC output buffer OFF	0	-	VREF+
tSETTLING	Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when DACOUT reaches the final value of ±0.5LSB, ±1LSB, ±2LSB, ±4LSB, ±8LSB)	Normal mode, DAC output buffer OFF, ±1LSB CL=10 pF		-	1.7(2)	2(2)	μs
tWAKEUP(3)	Wakeup time from off state (setting the Enx bit in the DAC Control register) until the ±1LSB final value	Normal mode, DAC output buffer ON, CL ≤ 50 pF, RL = 5 ㏀		-	5	7.5	μs
	Middle code offset for 1		VREF+ = 3.6 V	-	850	-
Voffset(2)	trim code step		VREF+ = 1.8 V	-	425	-	μV

Table 89. DAC characteristics⁽¹⁾ (continued)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
	DAG audienent	DAC output	No load, middle code (0x800)	-	360	-
I DDA(DAC)		buffer ON	No load, worst code (0xF1C)	-	490	-
	DAC quiescent consumption from V DDA	DAC output buffer OFF	No load, middle/worst code (0x800)	-	20	-
			Hold mode, 100 nF	-	360*T ON / (T ON +T OFF )	-
		DAC output	No load, middle code (0x800)	-	170	-	μΑ
		buffer ON	No load, worst code (0xF1C)	-	170	-
I DDV (DAC)	DAC consumption from V REF+	DAC output buffer OFF	No load, middle/worst code (0x800)	-	160	-
			old mode, Buffer nF (worst code)	-	170*T ON / (T ON +T OFF )	-
			old mode, Buffer nF (worst code)	-	160*T ON / (T ON +T OFF )	-

Table 90. DAC accuracy⁽¹⁾

Symbol	Parameter	Cond	itions	Min	Typ	Max	Unit
DNL	Differential non	DAC outpu	DAC output buffer ON		±2	-	LSB
DINL	linearity (2)	DAC output buffer OFF		-	±2	-	LOD
INL	Integral non linearity (3)		DAC output buffer ON,C_L \le 50$ pF, $R_L \ge 5 \text{ k}\Omega$ DAC output buffer OFF, $C_L \le 50$ pF, no $R_L$		±4	-	LSB
IINL	integral non ineanty.	· ·			±4	-	LOD
		DAC output buffer ON,	V REF+ = 3.6 V	-	-	±12
Offset	Offset error at code $C_L \le 50 \text{ pF},$ $R_L \ge 5 \text{ k}\Omega		V REF+ = 1.8 V	-	-	±25	LSB
		· ·	buffer OFF, pF, no R L	-	-	±8

Table 90. DAC accuracy(1) (continued)

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
Offset1	Offset error at code 0x001(4)	DAC output buffer OFF, CL ≤ 50 pF, no RL		-	-	±5	LSB
OffsetCal	Offset error at code 0x800 after factory	DAC output buffer ON,	VREF+ = 3.6 V	-	-	±5	LSB
	calibration	CL ≤ 50 pF, RL ≥ 5 ㏀	VREF+ = 1.8 V	-	-	±7
	Gain error(5)	DAC output buffer ON,CL	≤ 50 pF, RL ≥ 5 ㏀	-	-	±1
Gain			DAC output buffer OFF, CL ≤ 50 pF, no RL		-	±1	%
TUE	Total unadjusted error		DAC output buffer OFF, CL ≤ 50 pF, no RL	-	-	±12	LSB
SNR	Signal-to-noise ratio(6)	DAC output buffer ON,CL	≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz, BW = 500 KHz	-	67.8	-	dB
SINAD	Signal-to-noise and distortion ratio(6)	DAC output buffer ON, CL ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz		-	67.5	-	dB
ENOB	Effective number of bits	CL	DAC output buffer ON, ≤ 50 pF, RL ≥ 5 ㏀ , 1 kHz	-	10.9	-	bits

^1. Guaranteed by characterization.

^2. Difference between two consecutive codes minus 1 LSB.

^3. Difference between the value measured at Code i and the value measured at Code i on a line drawn between Code 0 and last Code 4095.

^4. Difference between the value measured at Code (0x001) and the ideal value.

^5. Difference between the ideal slope of the transfer function and the measured slope computed from code 0x000 and 0xFFF when the buffer is OFF, and from code giving 0.2 V and (VREF+ - 0.2 V) when the buffer is ON.

^6. Signal is -0.5dBFS with Fsampling=1 MHz.

R L C L Buffered/Non-buffered DAC DAC_OUTx Buffer(1) 12-bit digital to analog converter ai17157V3

Figure 44. 12-bit buffered /non-buffered DAC

1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register.

6.3.22 Voltage reference buffer characteristics

Table 91. VREFBUF characteristics(1)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
			VSCALE = 000	2.8	3.3	3.6
		Normal mode VSCALE = 010 2.1	VSCALE = 001	2.4 -	- 3.6	3.6
			VSCALE = 011	1.8	-	3.6
VDDA	Analog supply voltage		VSCALE = 000	1.62	-	2.80
			VSCALE = 001	1.62	-	2.40
		Degraded mode	VSCALE = 010	1.62	-	2.10
			VSCALE = 011	1.62	-	1.80
			VSCALE = 000	-	2.5	-
			VSCALE = 001	-	2.048	-	V
		Normal mode	VSCALE = 010	-	1.8	-
			VSCALE = 011	-	1.5	-
VREFBUF	Voltage Reference		VSCALE = 000	VDDA- 150 mV	-	VDDA
OUT	Buffer Output	Degraded mode(2)	VSCALE = 001	VDDA- 150 mV	-	VDDA
			VSCALE = 010	VDDA- 150 mV	-	VDDA
			VSCALE = 011	VDDA- 150 mV	-	VDDA
TRIM	Trim step resolution	-	-	-	±0.05	±0.2	%
CL	Load capacitor	-	-	0.5	1	1.50	uF

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
esr	Equivalent Serial Resistor of CL	-	-	-	-	2	Ω
Iload	Static load current	-	-	-	-	4	mA
	Line regulation	≤ 3.6 V	Iload = 500 μA	-	200	-	ppm/V
Ilinereg		2.8 V ≤ VDDA	Iload = 4 mA	-	100	-
Iloadreg	Load regulation	500 μA ≤ ILOAD ≤ 4 mA	Normal Mode	-	50	-	ppm/ mA
Tcoeff	Temperature coefficient	-40 °C < TJ < +125 °C	-	-	-	Tcoeff xVREFINT + 75	ppm/ °C
		DC	-	-	60	-
PSRR	Power supply rejection	100KHz	-	-	40	-	dB
		CL=0.5 μF	-	-	300	-
tSTART	Start-up time	C L=1 μF	-	-	500	-	μs
		CL=1.5 μF	-	-	650	-
IINRUSH	Control of maximum DC current drive on VREFBUFOUT during startup phase(3)	-		-	8	-	mA
	VREFBUF	ILOAD = 0 μA	-	-	15	25
IDDA(VRE FBUF)	consumption from	ILOAD = 500 μA	-	-	16	30	μA
	VDDA	ILOAD = 4 mA	-	-	32	50

6.3.23 Temperature sensor characteristics

Table 92. Temperature sensor characteristics

Symbol	Parameter	Min	Typ	Max	Unit
(1) TL	VSENSE linearity with temperature	-	-	±3	°C
AvgSlope(2)	Average slope	-	2	-	mV/°C
V30(3)	Voltage at 30°C ± 5 °C	-	0.62	-	V
tstartrun(1)	Startup time in Run mode (buffer startup)	-	-	25.2
tStemp(1)	ADC sampling time when reading the temperature	9	-	-	μs
Isens(1)	Sensor consumption	-	0.18	0.31
Isensbuf(1)	Sensor buffer consumption	-	3.8	6.5	μA

^1. Guaranteed by design.

^1. Guaranteed by design.

^2. In degraded mode, the voltage reference buffer cannot accurately maintain the output voltage (VDDA-drop voltage).

^3. To properly control VREFBUF IINRUSH current during the startup phase and the change of scaling, VDDA voltage should be in the range of 1.8 V-3.6 V, 2.1 V-3.6 V, 2.4 V-3.6 V and 2.8 V-3.6 V for VSCALE = 011, 010, 001 and 000, respectively.

• 1. Guaranteed by characterization.
• 1. Measured at VDDA = 3.3 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.

Table 93. Temperature sensor calibration values

Symbol	Parameter	Memory address
TSCAL1	Temperature sensor raw data acquired value at 30 °C, VDDA=3.3 V	0x1FF1 E820 -0x1FF1 E821
TSCAL2	Temperature sensor raw data acquired value at 110 °C, VDDA=3.3 V	0x1FF1 E840 - 0x1FF1 E841

6.3.24 Temperature and VBAT monitoring

Table 94. VBAT monitoring characteristics

Symbol	Parameter		Typ	Max	Unit
R	Resistor bridge for VBAT	-	26	-	KΩ
Q	Ratio on VBAT measurement	-	4	-	-
Er(1)	Error on Q	–10	-	+10	%
tSvbat(1)	ADC sampling time when reading VBAT input	9	-	-	μs
VBAThigh	High supply monitoring	-	3.55	-	V
VBATlow	Low supply monitoring	-	1.36	-

Table 95. VBAT charging characteristics

Symbol	Parameter	Condition	Min	Typ	Max	Unit
	Battery charging resistor	VBRS in PWRCR3= 0	-	5	-	KΩ
RBC		VBRS in PWRCR3= 1	-	1.5	-

Symbol	Parameter	Min	Typ	Max	Unit
TEMPhigh	High temperature monitoring	-	117	-	°C
TEMPlow	Low temperature monitoring	-	–25	-

6.3.25 Voltage booster for analog switch

Table 97. Voltage booster for analog switch characteristics(1)

Symbol	Parameter	Condition	Min	Typ	Max	Unit
VDD	Supply voltage	-	1.62	2-6	3.6	V
tSU(BOOST)	Booster startup time	-	-	-	50	μs
		1.62 V ≤ VDD ≤ 2.7 V	-	-	125
IDD(BOOST)	Booster consumption	2.7 V < VDD < 3.6 V	-	-	250	μA

^1. Guaranteed by characterization results.

6.3.26 Comparator characteristics

Table 98. COMP characteristics⁽¹⁾

Symbol	Parameter	Co	onditions	Min	Typ	Max	Unit
V_{DDA}	Analog supply voltage		-	1.62	3.3	3.6
V IN	Comparator input voltage range		-	0	-	V DDA	٧
V BG (2)	Scaler input voltage		-	Refe	er to V RI	EFINT
V SC	Scaler offset voltage		-	-	±5	±10	mV
1	Scaler static consumption	BRGEN=	0 (bridge disable)	-	0.2	0.3
I DDA(SCALER)	from V DDA	BRGEN=	1 (bridge enable)	-	8.0	1	μA
t STARTSCALER	Scaler startup time		-	-	140	250	μs
	Comparator startup time to	High-	speed mode	-	2	5
t START	reach propagation delay	Med	dium mode	-	5	20	μs
	specification	Ultra-lo	w-power mode	-	15	80
	Propagation delay for	High-	speed mode	-	50	80	ns
	200 mV step with 100 mV	Med	dium mode	-	0.5	1.2
4	overdrive	Ultra-lo	w-power mode	-	2.5	7	μs
t D	Propagation delay for step	High-	speed mode	-	50	120	ns
	> 200 mV with 100 mV overdrive only on positive	Medium mode		-	0.5	1.2
	inputs	Ultra-lo	w-power mode	-	2.5	7	μs
V offset	Comparator offset error	Full comr	non mode range	-	±5	±20	mV
		No	hysteresis	-	0	-
	0	Low	hysteresis	-	10	-	/
V_{hys}	Comparator hysteresis	Mediu	ım hysteresis	-	20	-	mV
		High	n hysteresis	-	30	-
			Static	-	400	600
		Ultra-low- power mode	With 50 kHz ±100 mV overdrive square signal	-	800	-	nA
			Static	-	5	7
I DDA (COMP)	Comparator consumption from V DDA	Medium mode	With 50 kHz ±100 mV overdrive square signal	-	6	-	^
			Static	-	70	100	μA
		High-speed mode	With 50 kHz ±100 mV overdrive square signal	-	75	-

^2. Refer to Table 28: Embedded reference voltage.

6.3.27 Operational amplifier characteristics

Table 99. OPAMP characteristics(1)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
VDDA	Analog supply voltage Range	-	2	3.3	3.6	V
CMIR	Common Mode Input Range	-	0	-	VDDA
		25°C, no load on output	-	-	±1.5
VIOFFSET	Input offset voltage	All voltages and temperature, no load	-	-	±2.5	mV
ΔVIOFFSET	Input offset voltage drift	-	-	±3.0	-	μV/°C
TRIMOFFSETP TRIMLPOFFSETP	Offset trim step at low common input voltage (0.1*VDDA)	-	-	1.1	1.5	mV
TRIMOFFSETN TRIMLPOFFSETN	Offset trim step at high common input voltage (0.9*VDDA)	-	-	1.1	1.5
ILOAD	Drive current	-	-	-	500	μA
ILOADPGA	Drive current in PGA mode	-	-	-	270
CLOAD	Capacitive load	-	-	-	50	pF
CMRR	Common mode rejection ratio	-	-	80	-	dB
PSRR	Power supply rejection ratio	CLOAD ≤ 50pf / ≥ 4 kΩ(2) at 1 kHz, RLOAD Vcom=VDDA/2	50	66	-	dB
GBW	Gain bandwidth for high supply range	-	4	7.3	12.3	MHz
SR	Slew rate (from 10% and	Normal mode	-	3	-	V/μs
	90% of output voltage)	High-speed mode	-	30	-
AO	Open loop gain	-	59	90	129	dB
φm	Phase margin	-	-	55	-	°
GM	Gain margin	-	-	12	-	dB

Table 99. OPAMP characteristics(1) (continued)

Symbol	Parameter		Conditions	Min	Typ	Max	Unit
VOHSAT	High saturation voltage		Iload=max or RLOAD=min(2), Input at VDDA	VDDA -100 mV	-	-	mV
VOLSAT	Low saturation voltage		Iload=max or RLOAD=min(2), Input at 0 V	-	-	100
	Wake up time from OFF	Normal mode	CLOAD ≤ 50pf, ≥ 4 kΩ(2), RLOAD follower configuration	-	0.8	3.2
tWAKEUP	state	High speed	CLOAD ≤ 50pf, ≥ 4 kΩ(2), RLOAD follower configuration	-	0.9	2.8	μs
			-	-	2	-	-
	Non inverting gain value		-	-	4	-	-
			-	-	8	-	-
PGA gain			-	-	16	-	-
			-	-	-1	-	-
	Inverting gain value		-	-	-3	-	-
			-	-	-7	-	-
			-	-	-15	-	-
			PGA Gain=2	-	10/10	-
	R2/R1 internal resistance values in non-inverting	PGA Gain=4		-	30/10	-
	PGA mode(3)	PGA Gain=8		-	70/10	-
		PGA Gain=16		-	150/10	-	kΩ/
Rnetwork			PGA Gain=-1	-	10/10	-	kΩ
	R2/R1 internal resistance		PGA Gain=-3	-	30/10	-
	values in inverting PGA mode(3)		PGA Gain=-7	-	70/10	-
			PGA Gain=-15	-	150/10	-
Delta R	Resistance variation (R1 or R2)		-	-15	-	15	%
			Gain=2	-	GBW/2	-
	PGA bandwidth for		Gain=4	-	GBW/4	-	MHz
PGA BW	different non inverting gain		Gain=8	-	GBW/8	-
			Gain=16	-	GBW/16	-

Symbol	Parameter	C	onditions	Min	Typ	Max	Unit
en Voltage r	Valtana maia alamaita	at 1 KHz	output loaded with 4 kΩ	-	140	-	nV/√
	Voltage noise density	at 10 KHz		-	55	-	Hz
, OPAMP consumption from		Normal mode	no Load,	-	570	1000
IDDA(OPAMP)	V_{DDA}$	High- speed mode	quiescent mode, follower	-	610	1200	μA

^1. Guaranteed by design, unless otherwise specified.

^2. $R_{LOAD}is the resistive load connected to VSSA or to VDDA.

^3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance between the OPAMP inverting input and ground. PGA gain = 1 + R2/R1.

6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 100 for DFSDM are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for DFSDMx).

Table 100. DFSDM measured timing - 1.62-3.6 V(1)

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
fDFSDMCLK	DFSDM clock	1.62 V < VDD < 3.6 V	SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 V < VDD < 3.6 V SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 2.7 < VDD < 3.6 V	-	- - -	250 20 (fDFSDMCLK/4) 20 (fDFSDMCLK/4)
fCKIN (1/TCKIN)	Input clock frequency		SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]≠0), 1.62 < VDD < 3.6 V		-	20 (fDFSDMCLK/4)	MHz
		SPI mode (SITP[1:0]=0,1), Internal clock mode (SPICKSEL[1:0]≠0), 2.7 < VDD < 3.6 V		-	-	20 (fDFSDMCLK/4)
fCKOUT	Output clock frequency		1.62 < VDD < 3.6 V		-	20
	Output clock		Even division, CKOUTDIV[7:0] = 1, 3, 5	45	50	55
DuCyCKOUT	frequency duty cycle	1.62 < VDD < 3.6 V	Odd division, CKOUTDIV[7:0] = 2, 4, 6	(((n/2+1)/(n+1))* 100)–5	(((n/2+1)/(n+1)) *100)	(((n/2+1)/(n+1))* 100)+5	%

Table 100. DFSDM measured timing - 1.62-3.6 V(1) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
twh(CKIN) twl(CKIN)	Input clock high and low time	SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V	TCKIN/2 - 0.5	TCKIN/2	-
tsu	Data input setup time	SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V	4	-	-
th	Data input hold time	SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.62 < VDD < 3.6 V	0.5	-	-	ns
TManchester	Manchester data period (recovered clock period)	Manchester mode (SITP[1:0]=2,3), Internal clock mode (SPICKSEL[1:0]≠0), 1.62 < VDD < 3.6 V	(CKOUTDIV+1) * TDFSDMCLK	-	(2CKOUTDIV) TDFSDMCLK

Figure 45. Channel transceiver timing diagrams

6.3.29 Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 101 for DCMI are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage summarized in Table 24: General operating conditions, with the following configuration:

• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
• Capacitive load C=30 pF
• Measurement points are done at CMOS levels: 0.5VDD

Table 101. DCMI characteristics(1)

Symbol	Parameter	Min	Max	Unit
-	Frequency ratio DCMIPIXCLK/frcccck	-	0.4	-
DCMIPIXCLK	Pixel clock input	-	80	MHz
DPixel	Pixel clock input duty cycle	30	70	%
tsu(DATA)	Data input setup time	1	-
th(DATA)	Data input hold time	1	-
tsu(HSYNC) tsu(VSYNC)	DCMIHSYNC/DCMIVSYNC input setup time	1.5	-	ns
th(HSYNC) th(VSYNC)	DCMIHSYNC/DCMIVSYNC input hold time	1	-

MS32414V2 DCMI_PIXCLK tsu(VSYNC) tsu(HSYNC) DCMI_HSYNC DCMI_VSYNC DATA[0:13] 1/DCMI_PIXCLK th(HSYNC) th(HSYNC) tsu(DATA) th(DATA)

Figure 46. DCMI timing diagram

6.3.30 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 102 for LCD-TFT are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage summarized in Table 24: General operating conditions, with the following configuration:

• LCD_CLK polarity: high
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C=30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• I/O compensation cell enabled

Table 102. LTDC characteristics (1)

Symbol	Parameter	Conditions	Min	Max	Unit
		2.7 V < VDD < 3.6 V, 20 pF	-	150
fCLK	LTDC clock output frequency	2.7 V < VDD < 3.6 V	-	133	MHz
		1.62 V < VDD < 3.6 V	-	90
DCLK	LTDC clock output duty cycle	-	45	55	%
tw(CLKH), tw(CLKL)	Clock High time, low time	-	tw(CLK)/2-0.5	tw(CLK)/2+0.5
tv(DATA)	Data output valid time	-	-	0.5
th(DATA)	Data output hold time	-	0	-
tv(HSYNC), tv(VSYNC), tv(DE)	HSYNC/VSYNC/DE output valid time	-	-	0.5	ns
th(HSYNC), th(VSYNC), th(DE)	HSYNC/VSYNC/DE output hold time	-	0.5	-

Figure 47. LCD-TFT horizontal timing diagram

6.3.31 Timer characteristics

The parameters given in Table 103 are guaranteed by design.

Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output).

Table 103. TIMx characteristics⁽¹⁾⁽²⁾

Symbol	Parameter	Conditions (3)	Min	Max	Unit
t res(TIM)	Timer resolution time	AHB/APBx prescaler=1 or 2 or 4, f TIMxCLK = 240 MHz	1	-	t TIMxCLK
		AHB/APBx prescaler>4, f TIMxCLK = 140 MHz	1	-	t TIMxCLK
f EXT	Timer external clock frequency on CH1 to CH4			f TIMxCLK /2	MHz
Res TIM	Timer resolution		-	16/32	bit
t MAXCOUNT	Maximum possible count with 32-bit counter	-	-	65536 × 65536	t TIMxCLK

^1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers.

^2. Guaranteed by design.

^3. The maximum timer frequency on APB1 or APB2 is up to 240 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx_d2.

6.3.32 Communications interfaces

I 2 C interface characteristics

The I² C interface meets the timings requirements of the I2 C-bus specification and user manual revision 03 for:

• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
• Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s.

The I² C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0433 reference manual) and when the i2c_ker_ck frequency is greater than the minimum shown in the table below:

Symbol	Parameter		Condition	Min	Unit
I2CCLK f(I2CCLK) frequency	Standard-mode	Analog filter ON DNF=0	2 8
		Fast-mode	Analog filter OFF DNF=1 Analog filter ON DNF=0	9 17	MHz
		Fast-mode Plus	Analog filter OFF DNF=1	16

The SDA and SCL I/O requirements are met with the following restrictions:

• The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but still present.
• The 20 mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas:t_r(SDA/SCL)=0.8473xR_pxC_load

Rp(min)= (VDD-VOL(max))/IOL(max)

Where Rp is the I2C lines pull-up. Refer to Section 6.3.15: I/O port characteristics for the I2C I/Os characteristics.

All I2 C SDA and SCL I/Os embed an analog filter. Refer to Table 105 for the analog filter characteristics:

Table 105. I2C analog filter characteristics(1)

Symbol	Parameter	Min	Max	Unit
tAF	Maximum pulse width of spikes that are suppressed by the analog filter	50(2)	260(3)	ns

• 1. Guaranteed by design.
• 1. Spikes with widths below tAF(min) are filtered.
• 1. Spikes with widths above tAF(max) are not filtered.

DS12110 Rev 10 191/357

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 106 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• I/O compensation cell enabled
• HSLV activated when VDD ≤ 2.7 V

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 106. SPI dynamic characteristics(1)

• Symbol Parameter Conditions Min Typ Max Unit
• Master mode
  1.62 V≤VDD≤3.6 V 90
• Master mode
  2.7 V≤VDD≤3.6 V
  SPI1,2,3 133
• Master mode
  2.7 V≤VDD≤3.6 V
  SPI4,5,6 100
• fSCK
  1/tc(SCK) SPI clock frequency Slave receiver mode
  1.62 V≤VDD≤3.6 V
  SPI1,2,3 - - 150 MHz
• Slave receiver mode
  1.62 V≤VDD≤3.6 V
  SPI4,5,6 100
• Slave mode transmitter/full
  duplex
  2.7 V≤VDD≤3.6 V 31
• Slave mode transmitter/full
  duplex
  1.62 V≤VDD≤3.6 V 25
• tsu(NSS) NSS setup time 2 - -
• th(NSS) NSS hold time Slave mode 1 - - ns
• tw(SCKH),
  tw(SCKL) SCK high and low time Master mode TPLCK - 2 TPLCK TPLCK + 2

Table 106. SPI dynamic characteristics(1) (continued)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tsu(MI)		Master mode	2	-	-
tsu(SI)	Data input setup time	Slave mode	2	-	-
th(MI)	Data input hold time	Master mode	1	-	-
th(SI)		Slave mode	1	-	-
ta(SO)	Data output access time	Slave mode	9	13	27
tdis(SO)	Data output disable time	Slave mode	0	1	5	ns
		Slave mode, 2.7 V≤VDD≤3.6 V	-	11.5	16
tv(SO)	Data output valid time	Slave mode 1.62 V≤VDD≤3.6 V	-	13	20
tv(MO)		Master mode	-	1	3
th(SO)	Data output hold time	Slave mode, 1.62 V≤VDD≤3.6 V	9	-	-
th(MO)		Master mode	0	-	-

Figure 49. SPI timing diagram - slave mode and CPHA = 0

Figure 50. SPI timing diagram - slave mode and CPHA = 1(1)

1. Measurement points are done at 0.5VDD and with external CL = 30 pF.

1. Measurement points are done at 0.5VDD and with external CL = 30 pF.

I 2S interface characteristics

Unless otherwise specified, the parameters given in Table 107 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• I/O compensation cell enabled

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS).

Table 107. I2S dynamic characteristics(1)

Symbol	Parameter	Conditions	Min	Max	Unit
fMCK	I2S Main clock output	-	256x8K	256FS	MHz
	I2S clock frequency	Master data	-	64FS	MHz
fCK		Slave data	-	64FS
tv(WS)	WS valid time	Master mode	-	3.5
th(WS)	WS hold time	Master mode	0	-
tsu(WS)	WS setup time	Slave mode	1	-
th(WS)	WS hold time	Slave mode	1	-
tsu(SDMR)		Master receiver	1	-
tsu(SDSR)	Data input setup time	Slave receiver	1	-
th(SDMR)		Master receiver	4	-	ns
th(SDSR)	Data input hold time	Slave receiver	2	-
tv(SDST)	Data output valid time	Slave transmitter (after enable edge)	-	20
tv(SDMT)		Master transmitter (after enable edge)	-	3
th(SDST)		Slave transmitter (after enable edge)	9	-
th(SDMT)	Data output hold time	Master transmitter (after enable edge)	0	-

Figure 52. I2S slave timing diagram (Philips protocol)(1)

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

SAI characteristics

Unless otherwise specified, the parameters given in Table 108 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C=30 pF
• Measurement points are performed at CMOS levels: 0.5VDD

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS).

Table 108. SAI characteristics(1)

Symbol	Parameter	Conditions	Min	Max	Unit
fMCK	SAI Main clock output	-	256 x 8K	256xFs	MHz
	SAI clock frequency(2)	Master data: 32 bits	-	128xFs(3)
FCK		Slave data: 32 bits	-	128xFs	MHz
		Master mode 2.7≤VDD≤3.6V	-	15
tv(FS)		FS valid time Master mode - 1.71≤VDD≤3.6V		20
tsu(FS)	FS setup time	Slave mode	7	-
		Master mode	1	-	ns
th(FS)	FS hold time	Slave mode	1	-
tsu(SDAMR)		Master receiver	0.5	-
tsu(SDBSR)	Data input setup time	Slave receiver	1	-
th(SDAMR)		Master receiver	3.5	-
th(SDBSR)	Data input hold time	Slave receiver	2	-
		Slave transmitter (after enable edge) 2.7≤VDD≤3.6V	-	17
tv(SDBST)	Data output valid time	Slave transmitter (after enable edge) 1.62≤VDD≤3.6V	-	20
th(SDBST)	Data output hold time	Slave transmitter (after enable edge)	7	-
		Master transmitter (after enable edge) 2.7≤VDD≤3.6V	-	17	ns
tv(SDAMT)	Data output valid time	Master transmitter (after enable edge) 1.62≤VDD≤3.6V	-	20
th(SDAMT)	Data output hold time	Master transmitter (after enable edge)	7.55	-

Figure 54. SAI master timing waveforms

MDIO characteristics

Table 109. MDIO Slave timing parameters

Symbol	Parameter	Min	Typ	Max	Unit
F sDC	Management data clock	-	-	40	MHz
t d(MDIO)	Management data input/output output valid time	7	8	20
t su(MDIO)	Management data input/output setup time	4	-	-	ns
t h(MDIO)	Management data input/output hold time	1	i	ı

Figure 56. MDIO Slave timing diagram

SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 110 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5VDD
• I/O compensation cell enabled
• HSLV activated when VDD ≤ 2.7 V

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fPP	Clock frequency in data transfer mode	-	0	-	125	MHz
tW(CKL)	Clock low time		9.5	10.5	-
tW(CKH)	Clock high time	fPP =50 MHz	8.5	9.5	-	ns
CMD, D inputs (referenced to CK) in MMC and SD HS/SDR/DDR mode
tISU	Input setup time HS		3	-	-
tIH	Input hold time HS	fPP ≥ 50 MHz	0.5	-	-	ns
tIDW(3)	Input valid window (variable window) CMD, D outputs (referenced to CK) in MMC and SD HS/SDR/DDR mode		3	-	-
tOV	Output valid time HS		-	3.5	5
tOH	Output hold time HS	fPP ≥ 50 MHz	2	-	-	ns

Table 110. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V(1)(2)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
CMD, D inputs (referenced to CK) in SD default mode
tISUD	Input setup time SD		3	-	-
tIHD	Input hold time SD CMD, D outputs (referenced to CK) in SD default mode	fPP =25 MHz	0.5	-	-	ns
tOVD	Output valid default time SD		-	1	2
tOHD	Output hold default time SD	fPP =25 MHz	0	-	-	ns

Table 111. Dynamic characteristics: eMMC characteristics, VDD = 1.71 to 1.9 V(1)(2)

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fPP	Clock frequency in data transfer mode	-	0	-	120	MHz
tW(CKL)	Clock low time	fPP =50 MHz	9.5	10.5	-
tW(CKH)	Clock high time		8.5	9.5	-	ns
CMD, D inputs (referenced to CK) in eMMC mode
tISU	Input setup time HS		2.5	-	-
t IH	Input hold time HS	fPP ≥ 50 MHz	1	-	-	ns
tIDW(3)	Input valid window (variable window) CMD, D outputs (referenced to CK) in eMMC mode		3.5	-	-
tOV	Output valid time HS		-	5	7
tOH	Output hold time HS	fPP ≥ 50 MHz	3	-	-	ns

^2. Above 100 MHz, CL = 20 pF.

^3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

^2. CL = 20 pF.

^3. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.

Figure 57. SDIO high-speed mode

Figure 58. SD default mode

MSv36879V3 Data output IO0 IO2 IO4 Clock Data input IO0 IO2 IO4 tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK) tsf(IN) thf(IN) tvf(OUT) thr(OUT) IO1 IO3 IO5 IO1 IO3 IO5 tvr(OUT) thf(OUT) tsr(IN)thr(IN)

Figure 59. DDR mode

CAN (controller area network) interface

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (FDCANx_TX and FDCANx_RX).

USB OTG_FS characteristics

The USB interface is fully compliant with the USB specification version 2.0 and is USB-IF certified (for Full-speed device operation).

Symbol	Parameter	Condition	Min	Typ	Max	Unit
VDD33USB	USB transceiver operating voltage	-	3.0(1)	-	3.6	V
RPUI	Embedded USBDP pull-up value during idle	-	900	1250	1600
RPUR	Embedded USBDP pull-up value during reception	-	1400	2300	3200	Ω
ZDRV	Output driver impedance(2)	Driver high and low	28	36	44

USB OTG_HS characteristics

Unless otherwise specified, the parameters given in Table 113 for ULPI are derived from tests performed under the ambient temperature, frcc_cck frequency and VDD supply voltage conditions summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5VDD.

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tSC	Control in (ULPIDIR, ULPINXT) setup time	-	0.5	-	-
tHC	Control in (ULPIDIR, ULPINXT) hold time	-	6.5	-	-
tSD	Data in setup time	-	2.5	-	-
tHD	Data in hold time	-	0	-	-
		2.7 V < VDD < 3.6 V, CL = 20 pF	-	6.5	8.5	ns
tDC/tDD	Data/control output delay	-	-
		1.7 V < V DD < 3.6 V, CL = 15 pF	-	6.5	13

^1. The USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7 to 3.0 V voltage range.

^2. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-); the matching impedance is already included in the embedded driver.

^1. Guaranteed by characterization results.

Figure 60. ULPI timing diagram

Ethernet characteristics

Unless otherwise specified, the parameters given in Table 114, Table 115 and Table 116 for SMI, RMII and MII are derived from tests performed under the ambient temperature,f_{rcc_c_ck}frequency summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5V_DD.

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

Table 114 gives the list of Ethernet MAC signals for the SMI and Figure 61 shows the corresponding timing diagram.

Table 114. Dynamics characteristics: Ethernet MAC signals for SMI⁽¹⁾

Symbol	Parameter	Min	Typ	Max	Unit
t MDC	MDC cycle time(2.5 MHz)	400	400	403
T d(MDIO)	Write data valid time	1	1.5	3	ns
t su(MDIO)	Read data setup time	8	-	-	115
t h(MDIO)	Read data hold time	0	-	-

MS31384V1 ETH_MDC ETH_MDIO(O) ETH_MDIO(I) tMDC td(MDIO) tsu(MDIO) th(MDIO)

Figure 61. Ethernet SMI timing diagram

Table 115 gives the list of Ethernet MAC signals for the RMII and Figure 62 shows the corresponding timing diagram.

Table 115. Dynamics characteristics: Ethernet MAC signals for RMII(1)

Symbol	Parameter	Min	Typ	Max	Unit
tsu(RXD)	Receive data setup time	2	-	-
tih(RXD)	Receive data hold time	3	-	-
tsu(CRS)	Carrier sense setup time	2.5	-	-
tih(CRS)	Carrier sense hold time	2	-	-	ns
td(TXEN)	Transmit enable valid delay time	4	4.5	7
td(TXD)	Transmit data valid delay time	7	7.5	11.5

ai15667b RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV t d(TXEN) t d(TXD) t su(RXD) t su(CRS) t ih(RXD) t ih(CRS)

Figure 62. Ethernet RMII timing diagram

Table 116 gives the list of Ethernet MAC signals for MII and Figure 63 shows the corresponding timing diagram.

Symbol	Parameter	Min	Typ	Max	Unit
t su(RXD)	Receive data setup time	2	-	-
t ih(RXD)	Receive data hold time	3	-	-
t su(DV)	Data valid setup time	1.5	-	-
t ih(DV)	Data valid hold time	1	-	-	ns
t su(ER)	Error setup time	1.5	-	-	115
t ih(ER)	Error hold time	0.5	-	-
t d(TXEN)	Transmit enable valid delay time	4.5	6.5	11
t d(TXD)	Transmit data valid delay time	7	7.5	15

^1. Guaranteed by characterization results.

Figure 63. Ethernet MII timing diagram

6.3.33 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 117 and Table 118 for JTAG/SWD are derived from tests performed under the ambient temperature,f_{rcc_c_ck}$ frequency and $V_{DD}supply voltage summarized in Table 24: General operating conditions, with the following configuration:

• Output speed is set to OSPEEDRy[1:0] = 0x10
• Capacitive load C=30 pF
• Measurement points are done at CMOS levels: 0.5V_DD

Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics.

Table 117. Dynamics JTAG characteristics(1)

</vdd<> </vdd<> </vdd<> </vdd<>

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Fpp		2.7 V <vdd< 3.6="" td="" v<="">	-	-	37		-	-	37
1/tc(TCK)	TCK clock frequency	1.62 V <vdd< 3.6="" td="" v<="">	-	-	27.5	MHz	-	-	27.5	MHz
tisu(TMS)	TMS input setup time	-	2	-	-
tih(TMS)	TMS input hold time	-	1	-	-
tisu(TDI)	TDI input setup time	-	1.5	-	-
tih(TDI)	TDI input hold time	-	1	-	-	ns
	TDO output	2.7 V <vdd< 3.6="" td="" v<="">	-	8	13.5		-	8	13.5
tov (TDO)	valid time	1.62 V <vdd< 3.6="" td="" v<="">	-	8	18		-	8	18
toh(TDO)	TDO output hold time	-	7	-	-

Table 118. Dynamics SWD characteristics(1)

</vdd<> </vdd<> </vdd<> </vdd<>

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
Fpp		2.7 V <vdd< 3.6="" td="" v<="">	-	-	71		-	-	71
1/tc(SWCLK)	SWCLK clock frequency	1.62 V <vdd< 3.6="" td="" v<="">	-	-	55.5	MHz	-	-	55.5	MHz
tisu(SWDIO)	SWDIO input setup time	-	2.5	-	-
tih(SWDIO)	SWDIO input hold time	-	1	-	-
	SWDIO	2.7 V <vdd< 3.6="" td="" v<="">	-	8.5	14	ns	-	8.5	14	ns
tov (SWDIO)	output valid time	1.62 V <vdd< 3.6="" td="" v<="">	-	8.5	18		-	8.5	18
toh(SWDIO)	SWDIO output hold time	-	8	-	-

Figure 64. JTAG timing diagram

Figure 65. SWD timing diagram