STM32H753BI

Part: STM32H753ZIT6 (STM32H753xI family) — STMicroelectronics

Type: 32-bit Arm Cortex-M7 MCU

Description: 32-bit Arm Cortex-M7 MCU with double-precision FPU at up to 480 MHz, with 2 MB flash, 1 MB RAM, a 1.62–3.6 V supply, and cryptographic acceleration.

Operating Conditions:

• Supply voltage (VDD): 1.62–3.6 V
• Operating temperature (suffix 6): -40 to +85 °C ambient at maximum power dissipation (up to 105 °C in low-power dissipation); suffix 3 version is -40 to +125 °C
• Junction temperature (suffix 6): -40 to +125 °C
• Max CPU frequency: 480 MHz

Absolute Maximum Ratings:

• Max external main supply voltage (VDDX − VSS): 4.0 V (min -0.3 V)
• Max total current into all VDD lines (ΣIVDD): 620 mA
• Max current into each VDD pin: 100 mA
• Max output current sunk by any I/O pin (except Px_C): 20 mA
• Max junction temperature: 125 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• Core: Arm Cortex-M7 at up to 480 MHz, 1027 DMIPS (2.14 DMIPS/MHz), 16 KB I-cache and 16 KB D-cache
• Memory: 2 MB flash, 1 MB RAM (192 KB TCM, 864 KB user SRAM, 4 KB backup SRAM)
• Supply: VDD and VDDLDO 1.62–3.6 V; VDD33USB 3.0–3.6 V when USB is used
• Analog supply VDDA: 1.62–3.6 V with ADC or COMP in use; 1.8 V min with DAC or VREFBUF; 2.0 V min with OPAMP
• Standby current: 2.95 μA (Backup SRAM off, RTC/LSE on)
• ADCs: 3× 16-bit, up to 3.6 MSPS, up to 36 channels
• DACs: 2× 12-bit (1 MHz); 2× op-amps (7.3 MHz bandwidth); 2× ultra-low-power comparators
• Total injected current on I/Os: ±25 mA; total I/O sink or source current: 140 mA each

Features:

• Dual-mode Quad-SPI up to 133 MHz and a flexible memory controller (FMC) with up to 32-bit bus
• Up to 35 communication peripherals: 4× I2C, 4× USART/4× UART/1× LPUART, 6× SPI, 4× SAI, 2× FDCAN, 2× USB OTG, Ethernet MAC, 2× SDMMC
• Up to 22 timers, including a high-resolution timer (2.1 ns)
• LCD-TFT controller, Chrom-ART accelerator, hardware JPEG codec
• Crypto: AES, TDES, HASH (MD5, SHA-1, SHA-2), HMAC, true RNG
• Security: ROP, PC-ROP, active tamper, secure firmware upgrade, secure access mode
• Low-power modes (Sleep, Stop, Standby) and VBAT mode with battery charging
• 3 power domains; 6 voltage scaling ranges; LDO regulator
• SWD and JTAG debug, 4 KB embedded trace buffer
• Up to 168 I/Os; 96-bit unique ID

Applications:

Package:

• LQFP100 (14 × 14 mm)
• LQFP144 (20 × 20 mm)
• LQFP176 (24 × 24 mm)
• LQFP208 (28 × 28 mm)
• UFBGA169 (7 × 7 mm)
• UFBGA176+25 (10 × 10 mm)
• TFBGA100 (8 × 8 mm)
• TFBGA240+25 (14 × 14 mm)

Figure 4. LQFP100 pinout

1. The above figure shows the package top view.

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Figure 5. TFBGA100 pinout

1. The above figure shows the package top view.

Figure 6. LQFP144 pinout

1. The above figure shows the package top view.

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Figure 7. UFBGA169 ballout

Figure 8. LQFP176 pinout

1. The above figure shows the package top view.

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Figure 9. UFBGA176+25 ballout

1. The above figure shows the package top view.

Figure 10. LQFP208 pinout

1. The above figure shows the package top view.

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Unless otherwise specified, the parameters given in Table 86 are derived from tests performed under the ambient temperature, f PCLK2 frequency and V DDA supply voltage conditions summarized in Table 23: General operating conditions .

Table 86. ADC characteristics (1)

Table 86. ADC characteristics (1)

Table 86. ADC characteristics (1) (continued)

1. Depending on the package, V REF+ can be internally connected to V DDA and V REF- to V SSA .

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Table 87. ADC accuracy (1)(2)(3)

1. Guaranteed by characterization for BGA packages, the values for LQFP packages might differ.
2. ADC DC accuracy values are measured after internal calibration.
3. The above table gives the ADC performance in 16-bit mode.
4. ADC clock frequency ≤ 36 MHz, 2 V ≤ V DDA ≤ 3.3 V, 1.6 V ≤ V REF ≤ V DDA , BOOSTEN (for I/O) = 1.
5. ENOB, SINAD, SNR and THD are specified for V DDA = V REF = 3.3 V.

Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

Any positive injection current within the limits specified for I INJ(PIN) and Σ I INJ(PIN) in Section 6.3.14 does not affect the ADC accuracy.

Figure 39. ADC accuracy characteristics

Figure 40. Typical connection diagram when using the ADC with FT/TT pins featuring analog switch function

1. Refer to Section 6.3.20: 16-bit ADC characteristics for the values of R AIN and C ADC .
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (refer to Table 59: I/O static characteristics for the value of the pad capacitance). A high Cparasitic value downgrades conversion accuracy. To remedy this, f ADC should be reduced.
3. Refer to Table 59: I/O static characteristics for the value of I lkg .
4. Refer to Figure 14: Power supply scheme .

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Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics , Table 21: Current characteristics , and Table 22: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 20. Voltage characteristics (1)

1. This formula has to be applied on power supplies related to the IO structure described by the pin definition table.
2. To sustain a voltage higher than 4V the internal pull-up/pull-down resistors must be disabled.
3. All main power (V DD , V DDA , V DD33USB ) and ground (V SS , V SSA ) pins must always be connected to the external power supplies, in the permitted range.
4. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
5. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
6. A positive injection is induced by V IN >VDD while a negative injection is induced by V IN <VSS . I INJ(PIN) must never be exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values.
7. When several inputs are submitted to a current injection, the maximum ∑ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 21. Current characteristics

Table 22. Thermal characteristics

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The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max × Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark