STM32G070CB/KB/RB
ARM Cortex-M0+ 32-bit MCUThe STM32G070CB/KB/RB is a arm cortex-m0+ 32-bit mcu from STMicroelectronics. View the full STM32G070CB/KB/RB datasheet below including key specifications, absolute maximum ratings.
STM32G070CB/KB/RB shares its datasheet with STM32G070RBT6, whose page lists every part number it covers.
Official STM32G070CB/KB/RB datasheet (PDF) — the source this page was extracted from.
Manufacturer
STMicroelectronicsCategory
Integrated CircuitsSTM32G070CB/KB/RB Key Specifications
| Parameter | Value |
|---|---|
| ADC | 12-bit, 0.4 µs, up to 16 external channels |
| DMA | 7-channel |
| I2C | 2 (Fast-mode Plus, 1 Mbit/s) |
| SPI | 2 (32 Mbit/s), one multiplexed with I2S, plus 4 extra via USARTs |
| Core | Arm Cortex-M0+ 32-bit |
| SRAM | 36 KB (32 KB with HW parity check) |
| GPIOs | Up to 59 (29 / 43 / 59 depending on package) |
| USART | 4 |
| Timers | 11 (1 advanced-control 16-bit, 5 general-purpose 16-bit, 2 basic 16-bit, 2 watchdogs, SysTick) |
| Flash Memory | 128 KB |
| Supply Voltage | 2.0V to 3.6V |
| Debug Interface | Serial Wire Debug (SWD) |
| Low-Power Modes | Sleep, Stop, Standby |
| Max CPU Frequency | 64 MHz |
| Operating Temperature (Ambient) | -40°C to 85°C |
| Operating Temperature (Junction) | -40°C to 105°C |
STM32G070CB/KB/RB Overview
Part: STM32G070RBT6 (STM32G070CB/KB/RB family) — STMicroelectronics
Type: Arm Cortex-M0+ 32-bit MCU
Description: 32-bit Arm Cortex-M0+ MCU at up to 64 MHz with 128 KB Flash and 36 KB SRAM, 2.0–3.6 V supply, four USARTs, two I²C, two SPIs, and a 12-bit ADC.
Operating Conditions:
- Supply voltage (VDD/VDDA): 2.0–3.6 V
- Backup supply (VBAT): 1.55–3.6 V
- Operating temperature: -40 to 85 °C (ambient); junction temperature -40 to 105 °C
- Max AHB/APB clock: 64 MHz
Absolute Maximum Ratings:
- Max supply voltage (VDD): 4.0 V (VBAT also 4.0 V)
- Max current into VDD/VDDA pins: 100 mA
- Max current per I/O pin: 15 mA sunk or sourced (20 mA sunk on FT_f pins)
- Max junction temperature: 150 °C
- Storage temperature: -65 to +150 °C
Key Specs:
- Core frequency: up to 64 MHz (fHCLK, fPCLK)
- Memory: 128 KB Flash, 36 KB SRAM (32 KB with HW parity check)
- ADC: 12-bit, 0.4 μs conversion time, up to 16 external channels (RB variant), 0 to 3.6 V conversion range
- I/O: up to 59 fast I/Os on the RB variant, multiple 5 V-tolerant
- I/O input voltage: up to Min(VDD + 3.6, 5.5) V on standard FT_xx pins; FT_c pins up to 5.0 V
- Total I/O current: 80 mA sunk and 80 mA sourced (sum of all pins, abs max)
- Timers: 11 (one 16-bit advanced control, five 16-bit general-purpose, two basic, two watchdogs, SysTick)
- DMA: 7 channels
Features:
- Arm Cortex-M0+ CPU with MPU
- Four USARTs with synchronous SPI mode; two support ISO7816, LIN, IrDA
- Two I²C interfaces supporting Fast-mode Plus (1 Mbit/s); one supports SMBus/PMBus and wakeup from Stop
- Two SPIs (32 Mbit/s), one multiplexed with I²S
- Power-on/power-down reset; Sleep, Stop and Standby low-power modes
- VBAT supply for RTC and backup registers
- 32 kHz and 4–48 MHz crystal oscillators, internal 16 MHz RC with PLL option, internal 32 kHz RC
- Calendar RTC with alarm and periodic wakeup from Stop/Standby
- CRC calculation unit
- Serial wire debug (SWD)
- ECOPACK 2 compliant
Applications:
- Consumer, industrial and appliance products
- Internet of Things (IoT) solutions
Package:
- LQFP64 (10 × 10 mm)
- LQFP48 (7 × 7 mm)
- LQFP32 (7 × 7 mm)
STM32G070CB/KB/RB Features
- Includes ST state-of-the-art patented technology
- Core: Arm ® 32-bit Cortex ® -M0+ CPU, frequency up to 64 MHz
- -40°C to 85°C operating temperature
- Memories
- -128 Kbytes of flash memory with protection -36 Kbytes of SRAM (32 Kbytes with HW parity check)
- CRC calculation unit
- Reset and power management
- -Power-on/Power-down reset (POR/PDR)
- -Voltage range: 2.0 V to 3.6 V
- -Low-power modes: Sleep, Stop, Standby
- -VBAT supply for RTC and backup registers
- Clock management
- -32 kHz crystal oscillator with calibration
- -4 to 48 MHz crystal oscillator
- -Internal 16 MHz RC with PLL option
- -Internal 32 kHz RC oscillator (±5 %)
- Up to 59 fast I/Os
- -Multiple 5 V-tolerant I/Os
- -All mappable on external interrupt vectors
- 7-channel DMA controller with flexible mapping
- 12-bit, 0.4 μs ADC (up to 16 ext. channels)
- -Conversion range: 0 to 3.6V
- -Up to 16-bit with hardware oversampling
- 11 timers: 16-bit for advanced motor control, five 16-bit general-purpose, two basic 16-bit, two watchdogs, SysTick timer
- Calendar RTC with alarm and periodic wakeup from Stop/Standby
STM32G070CB/KB/RB Pin Configuration
Figure 3. STM32G070KxT LQFP32 pinout
Figure 4. STM32G070CxT LQFP48 pinout
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Figure 5. STM32G070RxT LQFP64 pinout
Table 10. Terms and symbols used in Pin assignment and description table
| Column | Symbol | Definition |
|---|---|---|
| Pin name | Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name. | Terminal name corresponds to its by-default function at reset, unless otherwise specified in parenthesis under the pin name. |
| S | Supply pin | |
| Pin type I/O structure Note Upon | I I/O FT TT RST _f _a _c _d | Input only pin Input / output pin 5 V tolerant I/O 3.6 V tolerant I/O Reset pin with embedded weak pull-up resistor Options for TT or FT I/Os I/O, Fm+ capable I/O, with analog switch function I/O, with specific electrical characteristics |
| reset, all I/Os are | I/O, with specific electrical characteristics set as analog inputs, unless otherwise specified. | |
| Pin functions functions | ||
| Functions selected through GPIOx_AFR registers | Functions selected through GPIOx_AFR registers | |
| Functions directly selected/enabled through peripheral registers | Functions directly selected/enabled through peripheral registers | |
| Additional functions |
Table 10. Terms and symbols used in Pin assignment and description table
Table 11. Pin assignment and description
| Pin Number - LQFP32 | Pin Number - LQFP48 | Pin Number - LQFP64 | Pin name (function upon reset) | Pin type | I/O structure | Note | Alternate functions | Additional functions |
|---|---|---|---|---|---|---|---|---|
| - | - | 1 | PC11 | I/O | FT | - | USART3_RX, USART4_RX, TIM1_CH4 | - |
| - | - | 2 | PC12 | I/O | FT | - | TIM14_CH1 | - |
| - | 1 | 3 | PC13 | I/O | FT | (1)(2) | TIM1_BKIN | TAMP_IN1,RTC_TS, RTC_OUT1,WKUP2 |
| - | 2 | 4 | PC14- OSC32_IN (PC14) | I/O | FT | (1)(2) | TIM1_BKIN2 | OSC32_IN |
| 2 | - | - | PC14- OSC32_IN (PC14) | I/O | FT | (1)(2) | TIM1_BKIN2 | OSC32_IN,OSC_IN |
| 3 | 3 | 5 | PC15- OSC32_OUT (PC15) | I/O | FT | (1)(2) | OSC32_EN, OSC_EN, TIM15_BKIN | OSC32_OUT |
| - | 4 | 6 | VBAT | S | - | - | - | - |
| - | 5 | 7 | VREF+ | S | - | - | - | - |
| 4 | 6 | 8 | VDD/VDDA | S | - | - | - | - |
| 5 | 7 | 9 | VSS/VSSA | S | - | - | - | - |
| - | 8 | 10 | PF0-OSC_IN (PF0) | I/O | FT | - | TIM14_CH1 | OSC_IN |
| - | 9 | 11 | PF1- OSC_OUT (PF1) | I/O | FT | - | OSC_EN, TIM15_CH1N | OSC_OUT |
| 6 | 10 | 12 | NRST | I/O | RST | - | - | NRST |
| - | - | 13 | PC0 | I/O | FT | - | - | - |
| - | - | 14 | PC1 | I/O | FT | - | TIM15_CH1- | - |
| - | - | 15 | PC2 | I/O | FT | - | SPI2_MISO, TIM15_CH2 | - |
| - | - | 16 | PC3 | I/O | FT | - | SPI2_MOSI | - |
| 7 | 11 | 17 | PA0 | I/O | FT_a | - | SPI2_SCK, USART2_CTS, USART4_TX | ADC_IN0, TAMP_IN2,WKUP1 |
Table 11. Pin assignment and description
35
Table 11. Pin assignment and description (continued)
| Pin Number - LQFP32 | Pin Number - LQFP48 | Pin Number - LQFP64 | Pin name (function upon reset) | Pin type | I/O structure | Note | Alternate functions | Additional functions |
|---|---|---|---|---|---|---|---|---|
| 8 | 12 | 18 | PA1 | I/O | FT_a | - | SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT | ADC_IN1 |
| 9 | 13 | 19 | PA2 | I/O | FT_a | - | SPI1_MOSI/I2S1_SD, USART2_TX, TIM15_CH1 | ADC_IN2, WKUP4,LSCO |
| 10 | 14 | 20 | PA3 | I/O | FT_a | - | SPI2_MISO, USART2_RX, TIM15_CH2, EVENTOUT | ADC_IN3 |
| - | 15 | 21 | PA4 | I/O | TT_a | - | SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, EVENTOUT | ADC_IN4, RTC_OUT2 |
| 11 | - | - | PA4 | I/O | TT_a | - | SPI1_NSS/I2S1_WS, SPI2_MOSI, TIM14_CH1, EVENTOUT | ADC_IN4, TAMP_IN1, RTC_TS, RTC_OUT1,WKUP2 |
| 12 | 16 | 22 | PA5 | I/O | TT_a | - | SPI1_SCK/I2S1_CK, USART3_TX, EVENTOUT | ADC_IN5 |
| 13 | 17 | 23 | PA6 | I/O | FT_a | - | SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART3_CTS, TIM16_CH1 | ADC_IN6 |
| 14 | 18 | 24 | PA7 | I/O | FT_a | - | SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, TIM14_CH1, TIM17_CH1 | ADC_IN7 |
| - | - | 25 | PC4 | I/O | FT_a | - | USART3_TX, USART1_TX | ADC_IN17 |
| - | - | 26 | PC5 | I/O | FT_a | - | USART3_RX, USART1_RX | ADC_IN18, WKUP5 |
| 15 | 19 | 27 | PB0 | I/O | FT_a | (3) | SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, USART3_RX | ADC_IN8 |
| 16 | 20 | 28 | PB1 | I/O | FT_a | - | TIM14_CH1, TIM3_CH4, TIM1_CH3N, USART3_RTS_DE_CK, EVENTOUT | ADC_IN9 |
| 17 | 21 | 29 | PB2 | I/O | FT_a | - | SPI2_MISO, USART3_TX, EVENTOUT | ADC_IN10 |
| - | 22 | 30 | PB10 | I/O | FT_fa | - | USART3_TX, SPI2_SCK, I2C2_SCL | ADC_IN11 |
Table 11. Pin assignment and description (continued)
Table 11. Pin assignment and description (continued)
| Pin Number - LQFP32 | Pin Number - LQFP48 | Pin Number - LQFP64 | Pin name (function upon reset) | Pin type | I/O structure | Note | Alternate functions | Additional functions |
|---|---|---|---|---|---|---|---|---|
| - | 23 | 31 | PB11 | I/O | FT_fa | - | SPI2_MOSI, USART3_RX, I2C2_SDA | ADC_IN15 |
| - | 24 | 32 | PB12 | I/O | FT_a | - | SPI2_NSS, TIM1_BKIN, TIM15_BKIN, EVENTOUT | ADC_IN16 |
| - | 25 | 33 | PB13 | I/O | FT_f | - | SPI2_SCK, TIM1_CH1N, USART3_CTS, TIM15_CH1N, I2C2_SCL, EVENTOUT | - |
| - | 26 | 34 | PB14 | I/O | FT_f | - | SPI2_MISO, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA, EVENTOUT | - |
| - | 27 | 35 | PB15 | I/O | FT_c | (3) | SPI2_MOSI, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, EVENTOUT | RTC_REFIN |
| 18 | 28 | 36 | PA8 | I/O | FT_c | (3) | MCO, SPI2_NSS, TIM1_CH1, EVENTOUT | - |
| 19 | 29 | 37 | PA9 | I/O | FT_fd | (3) | MCO, USART1_TX, TIM1_CH2, SPI2_MISO, TIM15_BKIN, I2C1_SCL, EVENTOUT | - |
| 20 | 30 | 38 | PC6 | I/O | FT | (3) | TIM3_CH1 | - |
| - | 31 | 39 | PC7 | I/O | FT | - | TIM3_CH2 | - |
| - | - | 40 | PD8 | I/O | FT | - | USART3_TX, SPI1_SCK/I2S1_CK | - |
| - | - | 41 | PD9 | I/O | FT | - | USART3_RX, SPI1_NSS/I2S1_WS, TIM1_BKIN2 | - |
| 21 | 32 | 42 | PA10 | I/O | FT_fd | (3) | SPI2_MOSI, USART1_RX, TIM1_CH3, TIM17_BKIN, I2C1_SDA, EVENTOUT | - |
| 22 | 33 | 43 | PA11 [PA9] (4) | I/O | FT_f | (3) | SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, TIM1_BKIN2, I2C2_SCL | - |
| 23 | 34 | 44 | PA12 [PA10] (4) | I/O | FT_f | (3) | SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, I2S_CKIN, I2C2_SDA | - |
Table 11. Pin assignment and description (continued)
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Table 11. Pin assignment and description (continued)
| Pin Number - LQFP32 | Pin Number - LQFP48 | Pin Number - LQFP64 | Pin name (function upon reset) | Pin type | I/O structure | Note | Alternate functions | Additional functions |
|---|---|---|---|---|---|---|---|---|
| 24 | 35 | 45 | PA13 | I/O | FT | (5) | SWDIO, IR_OUT, EVENTOUT | - |
| 25 | 36 | 46 | PA14-BOOT0 | I/O | FT | (5) | SWCLK, USART2_TX, EVENTOUT | BOOT0 |
| 26 | 37 | 47 | PA15 | I/O | FT | - | SPI1_NSS/I2S1_WS, USART2_RX, USART4_RTS_DE_CK, USART3_RTS_DE_CK, EVENTOUT | - |
| - | - | 48 | PC8 | I/O | FT | - | TIM3_CH3, TIM1_CH1 | - |
| - | - | 49 | PC9 | I/O | FT | - | I2S_CKIN, TIM3_CH4, TIM1_CH2 | - |
| - | 38 | 50 | PD0 | I/O | FT_c | (3) | EVENTOUT, SPI2_NSS, TIM16_CH1 | - |
| - | 39 | 51 | PD1 | I/O | FT_d | (3) | EVENTOUT, SPI2_SCK, TIM17_CH1 | - |
| - | 40 | 52 | PD2 | I/O | FT_c | (3) | USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N | - |
| - | 41 | 53 | PD3 | I/O | FT_d | (3) | USART2_CTS, SPI2_MISO, TIM1_CH2N | - |
| - | - | 54 | PD4 | I/O | FT | - | USART2_RTS_DE_CK, SPI2_MOSI, TIM1_CH3N | - |
| - | - | 55 | PD5 | I/O | FT | - | USART2_TX, SPI1_MISO/I2S1_MCK, TIM1_BKIN | - |
| - | - | 56 | PD6 | I/O | FT | - | USART2_RX, SPI1_MOSI/I2S1_SD | - |
| 27 | 42 | 57 | PB3 | I/O | FT_a | - | SPI1_SCK/I2S1_CK,TIM1_CH2, USART1_RTS_DE_CK, EVENTOUT | - |
| 28 | 43 | 58 | PB4 | I/O | FT_a | - | SPI1_MISO/I2S1_MCK, TIM3_CH1, USART1_CTS, TIM17_BKIN, EVENTOUT | - |
| 29 | 44 | 59 | PB5 | I/O | FT | - | SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, I2C1_SMBA | WKUP6 |
Table 11. Pin assignment and description (continued)
Table 11. Pin assignment and description (continued)
| Pin Number - LQFP32 | Pin Number - LQFP48 | Pin Number - LQFP64 | Pin name (function upon reset) | Pin type | I/O structure | Note | Alternate functions | Additional functions |
|---|---|---|---|---|---|---|---|---|
| 30 | 45 | 60 | PB6 | I/O | FT_fa | - | USART1_TX, TIM1_CH3, TIM16_CH1N, SPI2_MISO, I2C1_SCL, EVENTOUT | - |
| 31 | 46 | 61 | PB7 | I/O | FT_fa | - | USART1_RX, SPI2_MOSI, TIM17_CH1N, USART4_CTS, I2C1_SDA, EVENTOUT | - |
| 32 | 47 | 62 | PB8 | I/O | FT_f | - | SPI2_SCK, TIM16_CH1, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT | - |
| 1 | 48 | 63 | PB9 | I/O | FT_f | - | IR_OUT, TIM17_CH1, USART3_RX, SPI2_NSS, I2C1_SDA, EVENTOUT | - |
| - | - | 64 | PC10 | I/O | FT | - | USART3_TX, USART4_TX, TIM1_CH3 | - |
- PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
-
These GPIOs must not be used as current sources (for example to drive a LED).
-
The speed should not exceed 2 MHz with a maximum load of 30 pF
- After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers as they are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.
- Upon reset, a pull-down resistor might be present on PA8, PB15, PD0, or PD2, depending on the voltage level on PA9/PC6, PA10/PB0, PD1, and PD3, respectively. In order to disable this resistor, strobe the UCPDx_STROBE bit of the SYSCFG_CFGR1 register during start-up sequence.
- Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.
- Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.
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Table 12. Port A alternate function mapping
| Port | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
|---|---|---|---|---|---|---|---|---|
| PA0 | SPI2_SCK | USART2_CTS | - | - | USART4_TX | - | - | - |
| PA1 | SPI1_SCK/ I2S1_CK | USART2_RTS _DE_CK | - | - | USART4_RX | TIM15_CH1N | I2C1_SMBA | EVENTOUT |
| PA2 | SPI1_MOSI/ I2S1_SD | USART2_TX | - | - | - | TIM15_CH1 | - | - |
| PA3 | SPI2_MISO | USART2_RX | - | - | - | TIM15_CH2 | - | EVENTOUT |
| PA4 | SPI1_NSS/ I2S1_WS | SPI2_MOSI | - | - | TIM14_CH1 | - | - | EVENTOUT |
| PA5 | SPI1_SCK/ I2S1_CK | - | - | - | USART3_TX | - | - | EVENTOUT |
| PA6 | SPI1_MISO/ I2S1_MCK | TIM3_CH1 | TIM1_BKIN | - | USART3_CTS | TIM16_CH1 | - | - |
| PA7 | SPI1_MOSI/ I2S1_SD | TIM3_CH2 | TIM1_CH1N | - | TIM14_CH1 | TIM17_CH1 | - | - |
| PA8 | MCO | SPI2_NSS | TIM1_CH1 | - | - | - | - | EVENTOUT |
| PA9 | MCO | USART1_TX | TIM1_CH2 | - | SPI2_MISO | TIM15_BKIN | I2C1_SCL | EVENTOUT |
| PA10 | SPI2_MOSI | USART1_RX | TIM1_CH3 | - | - | TIM17_BKIN | I2C1_SDA | EVENTOUT |
| PA11 | SPI1_MISO/ I2S1_MCK | USART1_CTS | TIM1_CH4 | - | - | TIM1_BKIN2 | I2C2_SCL | - |
| PA12 | SPI1_MOSI/ I2S1_SD | USART1_RTS _DE_CK | TIM1_ETR | - | - | I2S_CKIN | I2C2_SDA | - |
| PA13 | SWDIO | IR_OUT | - | - | - | - | - | EVENTOUT |
| PA14 | SWCLK | USART2_TX | - | - | - | - | - | EVENTOUT |
| PA15 | SPI1_NSS/ I2S1_WS | USART2_RX | - | - | USART4_RTS _DE_CK | USART3_RTS _DE_CK | - | EVENTOUT |
Table 12. Port A alternate function mapping
Table 13. Port B alternate function mapping
| Port | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
|---|---|---|---|---|---|---|---|---|
| PB0 | SPI1_NSS/ I2S1_WS | TIM3_CH3 | TIM1_CH2N | - | USART3_RX | - | - | - |
| PB1 | TIM14_CH1 | TIM3_CH4 | TIM1_CH3N | - | USART3_RTS _DE_CK | - | - | EVENTOUT |
| PB2 | - | SPI2_MISO | - | - | USART3_TX | - | - | EVENTOUT |
| PB3 | SPI1_SCK/ I2S1_CK | TIM1_CH2 | - | - | USART1_RTS _DE_CK | - | - | EVENTOUT |
| PB4 | SPI1_MISO/ I2S1_MCK | TIM3_CH1 | - | - | USART1_CTS | TIM17_BKIN | - | EVENTOUT |
| PB5 | SPI1_MOSI/ I2S1_SD | TIM3_CH2 | TIM16_BKIN | - | - | - | I2C1_SMBA | - |
| PB6 | USART1_TX | TIM1_CH3 | TIM16_CH1N | - | SPI2_MISO | - | I2C1_SCL | EVENTOUT |
| PB7 | USART1_RX | SPI2_MOSI | TIM17_CH1N | - | USART4_CTS | - | I2C1_SDA | EVENTOUT |
| PB8 | - | SPI2_SCK | TIM16_CH1 | - | USART3_TX | TIM15_BKIN | I2C1_SCL | EVENTOUT |
| PB9 | IR_OUT | - | TIM17_CH1 | - | USART3_RX | SPI2_NSS | I2C1_SDA | EVENTOUT |
| PB10 | - | - | - | - | USART3_TX | SPI2_SCK | I2C2_SCL | - |
| PB11 | SPI2_MOSI | - | - | - | USART3_RX | - | I2C2_SDA | - |
| PB12 | SPI2_NSS | - | TIM1_BKIN | - | - | TIM15_BKIN | - | EVENTOUT |
| PB13 | SPI2_SCK | - | TIM1_CH1N | - | USART3_CTS | TIM15_CH1N | I2C2_SCL | EVENTOUT |
| PB14 | SPI2_MISO | - | TIM1_CH2N | - | USART3_RTS _DE_CK | TIM15_CH1 | I2C2_SDA | EVENTOUT |
| PB15 | SPI2_MOSI | - | TIM1_CH3N | - | TIM15_CH1N | TIM15_CH2 | - | EVENTOUT |
Table 13. Port B alternate function mapping
Table 14. Port C alternate function mapping
| Port | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
|---|---|---|---|---|---|---|---|---|
| PC0 | - | - | - | - | - | - | - | - |
| PC1 | - | - | TIM15_CH1 | - | - | - | - | - |
| PC2 | - | SPI2_MISO | TIM15_CH2 | - | - | - | - | - |
| PC3 | - | SPI2_MOSI | - | - | - | - | - | - |
| PC4 | USART3_TX | USART1_TX | - | - | - | - | - | - |
| PC5 | USART3_RX | USART1_RX | - | - | - | - | - | - |
| PC6 | - | TIM3_CH1 | - | - | - | - | - | - |
| PC7 | - | TIM3_CH2 | - | - | - | - | - | - |
| PC8 | - | TIM3_CH3 | TIM1_CH1 | - | - | - | - | - |
| PC9 | I2S_CKIN | TIM3_CH4 | TIM1_CH2 | - | - | - | - | - |
| PC10 | USART3_TX | USART4_TX | TIM1_CH3 | - | - | - | - | - |
| PC11 | USART3_RX | USART4_RX | TIM1_CH4 | - | - | - | - | - |
| PC12 | - | - | TIM14_CH1 | - | - | - | - | - |
| PC13 | - | - | TIM1_BKIN | - | - | - | - | - |
| PC14 | - | - | TIM1_BKIN2 | - | - | - | - | - |
| PC15 | OSC32_EN | OSC_EN | TIM15_BKIN | - | - | - | - | - |
Table 14. Port C alternate function mapping
Table 15. Port D alternate function mapping
| Port | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
|---|---|---|---|---|---|---|---|---|
| PD0 | EVENTOUT | SPI2_NSS | TIM16_CH1 | - | - | - | - | - |
| PD1 | EVENTOUT | SPI2_SCK | TIM17_CH1 | - | - | - | - | - |
| PD2 | USART3_RTS _DE_CK | TIM3_ETR | TIM1_CH1N | - | - | - | - | - |
| PD3 | USART2_CTS | SPI2_MISO | TIM1_CH2N | - | - | - | - | - |
| PD4 | USART2_RTS _DE_CK | SPI2_MOSI | TIM1_CH3N | - | - | - | - | - |
| PD5 | USART2_TX | SPI1_MISO/ I2S1_MCK | TIM1_BKIN | - | - | - | - | - |
| PD6 | USART2_RX | SPI1_MOSI/ I2S1_SD | - | - | - | - | - | - |
| PD8 | USART3_TX | SPI1_SCK/ I2S1_CK | - | - | - | - | - | - |
| PD9 | USART3_RX | SPI1_NSS/ I2S1_WS | TIM1_BKIN2 | - | - | - | - | - |
STM32G070CB/KB/RB Absolute Maximum Ratings
Stresses above the absolute maximum ratings listed in Table 17 , Table 18 and Table 19 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with the JEDEC JESD47 qualification standard.
All voltages are defined with respect to V SS .
Table 17. Voltage characteristics
| Symbol | Ratings | Min | Max | Unit |
|---|---|---|---|---|
| V DD | External supply voltage | -0.3 | 4.0 | V |
| V BAT | External supply voltage on VBAT pin | -0.3 | 4.0 | V |
| V REF+ | External voltage on VREF+ pin | -0.3 | Min(V DD + 0.4, 4.0) | V |
| V IN (1) | Input voltage on FT_xx pins except FT_c | -0.3 | V DD + 4.0 (2)(3) | V |
| V IN (1) | Input voltage on FT_c pins | -0.3 | 5.5 | V |
| V IN (1) | Input voltage on any other pin | -0.3 | 4.0 | V |
- Refer to Table 18 for the maximum allowed injected current values.
- To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
- When an FT_a pin is used by an analog peripheral such as ADC, the maximum V IN is 4 V.
Table 18. Current characteristics
| Symbol | Ratings | Max | Unit |
|---|---|---|---|
| I VDD/VDDA | Current into VDD/VDDA power pin (source) (1) | 100 | mA |
| I VSS/VSSA | Current out of VSS/VSSA ground pin (sink) (2) | 100 | mA |
| I IO(PIN) | Output current sunk by any I/O and control pin except FT_f | 15 | mA |
| I IO(PIN) | Output current sunk by any FT_f pin | 20 | mA |
| I IO(PIN) | Output current sourced by any I/O and control pin | 15 | mA |
Table 18. Current characteristics
Table 18. Current characteristics (continued)
| Symbol | Ratings | Max | Unit |
|---|---|---|---|
| ∑ I IO(PIN) | Total output current sunk by sum of all I/Os and control pins | 80 | mA |
| ∑ I IO(PIN) | Total output current sourced by sum of all I/Os and control pins | 80 | mA |
| I INJ(PIN) (2) | Injected current on a FT_xx pin | -5 / NA (3) | mA |
| I INJ(PIN) (2) | Injected current on a TT_a pin (4) | -5 / 0 | mA |
| ∑ |I INJ(PIN) | | Total injected current (sum of all I/Os and control pins) (5) | 25 | mA |
- Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
- On these I/Os, any current injection disturbs the analog performances of the device.
- When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) | is the absolute sum of the negative injected currents (instantaneous values).
Table 19. Thermal characteristics
| Symbol | Ratings | Value | Unit |
|---|---|---|---|
| T STG | Storage temperature range | -65 to +150 | °C |
| T J | Maximum junction temperature | 150 | °C |
STM32G070CB/KB/RB Thermal Information
The operating junction temperature T J must never exceed the maximum given in Table 20: General operating conditions .
The maximum junction temperature in °C that the device can reach if respecting the operating conditions, is:
$$T_J(max) = T_A(max) + P_D(max) \times \Theta_{JA}$$
STM32G070CB/KB/RB Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| STM32G070 | STMicroelectronics | — |
| STM32G070CB | STMicroelectronics | — |
| STM32G070CXT | STMicroelectronics | LQFP-48 |
| STM32G070KB | STMicroelectronics | LQFP-32 7x7mm |
| STM32G070KXT | STMicroelectronics | LQFP-32 |
| STM32G070RB | STMicroelectronics | LQFP-64 10x10mm |
| STM32G070RBT6 | STMicroelectronics | 64-LQFP |
| STM32G070RXT | STMicroelectronics | LQFP-64 |
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All Integrated Circuits datasheetsAll STMicroelectronics datasheets (808)
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