STM32F103

Part: STM32F103xC/D/E

Type: ARM-based 32-bit Microcontroller

Description: High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, and 13 communication interfaces, featuring a 72 MHz Cortex-M3 CPU.

Operating Conditions:

• Supply voltage: 2.0 to 3.6 V
• Operating temperature: -40 to +105 °C
• Max CPU frequency: 72 MHz
• ADC conversion range: 0 to 3.6 V

Absolute Maximum Ratings:

• Max supply voltage (VDD-VSS): 4.0 V
• Max junction temperature: 125 °C
• Max storage temperature: 150 °C

Key Specs:

• CPU: ARM 32-bit Cortex-M3
• CPU performance: 1.25 DMIPS/MHz at 0 wait state
• Flash memory: 256 to 512 Kbytes
• SRAM: up to 64 Kbytes
• A/D converters: 3 × 12-bit, 1 μs (up to 21 channels)
• D/A converters: 2 × 12-bit
• I/O ports: Up to 112 fast I/O ports, almost all 5 V-tolerant
• SPI speed: Up to 18 Mbit/s

Features:

• Flexible static memory controller (FSMC) supporting Compact Flash, SRAM, PSRAM, NOR, NAND
• LCD parallel interface (8080/6800 modes)
• Multiple clock sources: 4-to-16 MHz crystal, internal 8 MHz RC, internal 40 kHz RC, 32 kHz RTC oscillator
• Low power modes: Sleep, Stop, Standby
• 12-channel DMA controller
• Debug interfaces: Serial wire debug (SWD) & JTAG
• Up to 11 timers, including motor control PWM timers and watchdogs
• Up to 13 communication interfaces: I2C, USART, SPI, CAN, USB 2.0 full speed, SDIO

Package:

• LQFP64 (10 × 10 mm)
• LQFP100 (14 × 14 mm)
• LQFP144 (20 × 20 mm)
• LFBGA100 (10 × 10 mm)
• LFBGA144 (10 × 10 mm)

• ■ Core: ARM 32-bit Cortex™-M3 CPU
• -72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access
• -Single-cycle multiplication and hardware division
• ■ Memories
• -256 to 512 Kbytes of Flash memory
• -up to 64 Kbytes of SRAM
• -Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories
• -LCD parallel interface, 8080/6800 modes
• ■ Clock, reset and supply management
• -2.0 to 3.6 V application supply and I/Os
• -POR, PDR, and programmable voltage detector (PVD)
• -4-to-16 MHz crystal oscillator
• -Internal 8 MHz factory-trimmed RC
• -Internal 40 kHz RC with calibration
• -32 kHz oscillator for RTC with calibration
• ■ Low power
• -Sleep, Stop and Standby modes
• -VBAT supply for RTC and backup registers
• ■ 3 × 12-bit, 1 μs A/D converters (up to 21 channels)
• -Conversion range: 0 to 3.6 V
• -Triple-sample and hold capability
• -Temperature sensor
• ■ 2 × 12-bit D/A converters
• ■ DMA: 12-channel DMA controller
• -Supported peripherals: timers, ADCs, DAC, SDIO, I 2 Ss, SPIs, I 2 Cs and USARTs
• ■ Debug mode
• -Serial wire debug (SWD) & JTAG interfaces
• -Cortex-M3 Embedded Trace Macrocell™

LQFP64 10 × 10 mm, LQFP100 14 × 14 mm, LQFP144 20 × 20 mm

LFBGA100 10 × 10 mm LFBGA144 10 × 10 mm

• ■ Up to 112 fast I/O ports
• -51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant
• ■ Up to 11 timers
• -Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• -2 × 16-bit motor control PWM timers with dead-time generation and emergency stop
• -2 × watchdog timers (Independent and Window)
• -SysTick timer: a 24-bit downcounter
• -2 × 16-bit basic timers to drive the DAC
• ■ Up to 13 communication interfaces
• -Up to 2 × I 2 C interfaces (SMBus/PMBus)
• -Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control)
• -Up to 3 SPIs (18 Mbit/s), 2 with I 2 S interface multiplexed
• -CAN interface (2.0B Active)
• -USB 2.0 full speed interface
• -SDIO interface
• ■ CRC calculation unit, 96-bit unique ID
• ■ ECOPACK ® packages

Figure 3. STM32F103xC, STM32F103xD and STM32F103xE performance line BGA144 ballout

Figure 4. STM32F103xC, STM32F103xD and STM32F103xE performance line BGA100 ballout

Figure 3. STM32F103xC, STM32F103xD and STM32F103xE performance line BGA144 ballout

Figure 5. STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP144 pinout

Figure 4. STM32F103xC, STM32F103xD and STM32F103xE performance line BGA100 ballout

Figure 5. STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP144 pinout

Figure 6. STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP100 pinout

Figure 7. STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP64 pinout

Figure 8. STM32F103xC, STM32F103xD and STM32F103xE performance line WLCSP64 ballout, ball side

Table 5. High-density STM32F103xx pin definitions

Pins	Pins	Pins	Pins	Pins	Pins		Type (1)	Main function (3) (after reset)	Alternate functions (4)	Alternate functions (4)
BGA144	BGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	I / O Level	Main function (3) (after reset)	Default	Remap
A3	A3	-	-	1	1	PE2	I/O FT	PE2	TRACECK/ FSMC_A23
A2	B3	-	-	2	2	PE3	I/O FT	PE3	TRACED0/FSMC_A19
B2	C3	-	-	3	3	PE4	I/O FT	PE4	TRACED1/FSMC_A20
B3	D3	-	-	4	4	PE5	I/O FT	PE5	TRACED2/FSMC_A21
B4	E3	-	-	5	5	PE6	I/O FT	PE6	TRACED3/FSMC_A22
C2	B2	C6	1	6	6	V BAT	S	V BAT
A1	A2	C8	2	7	7	PC13-TAMPER- RTC (5)	I/O	PC13 (6)	TAMPER-RTC
B1	A1	B8	3	8	8	PC14- OSC32_IN (5)	I/O	PC14 (6)	OSC32_IN
C1	B1	B7	4	9	9	PC15- OSC32_OUT (5)	I/O	PC15 (6)	OSC32_OUT
C3	-	-	-	-	10	PF0	I/O	FT PF0	FSMC_A0
C4	-	-	-	-	11	PF1	I/O FT	PF1	FSMC_A1
D4	-	-	-	-	12	PF2	I/O FT	PF2	FSMC_A2
E2	-	-	-	-	13	PF3	I/O FT	PF3	FSMC_A3
E3	-	-	-	-	14	PF4	I/O FT	PF4	FSMC_A4
E4	-	-	-	-	15	PF5	I/O FT	PF5	FSMC_A5
D2	C2	-	-	10	16	V SS_5	S	V SS_5
D3	D2	-	-	11	17	V DD_5	S	V DD_5
F3	-	-	-	-	18	PF6	I/O	PF6	ADC3_IN4/FSMC_NIORD
F2	-	-	-	-	19	PF7	I/O	PF7	ADC3_IN5/FSMC_NREG
G3	-	-	-	-	20	PF8	I/O	PF8	ADC3_IN6/FSMC_NIOWR
G2	-	-	-	-	21	PF9	I/O	PF9	ADC3_IN7/FSMC_CD
G1	-	-	-	-	22	PF10	I/O	PF10	ADC3_IN8/FSMC_INTR
D1	C1	D8	5	12	23	OSC_IN	I	OSC_IN
E1	D1	D7	6	13	24	OSC_OUT	O		OSC_OUT
F1	E1	C7	7	14	25	NRST	I/O	NRST
H1	F1	E8	8	15	26	PC0	I/O	PC0	ADC123_IN10
H2	F2	F8	9	16	27	PC1	I/O	PC1	ADC123_IN11
H3	E2	D6	10	17	28	PC2	I/O	PC2	ADC123_IN12
H4	F3	-	11	18	29	PC3	I/O	PC3	ADC123_IN13
J1	G1	E7	12	19	30	V SSA	S	V	SSA

Table 5. High-density STM32F103xx pin definitions (continued)

Pins	Pins	Pins	Pins	Pins	Pins	Pin name	Type (1)	/ O Level (2) Main function (after reset)	Alternate functions (4)	Alternate functions (4)
BGA144	BGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	Type (1)	/ O Level (2) Main function (after reset)	(3) Default	Remap
K1	H1	-	-	20	31	V REF-	S	V REF-
L1	J1	F7 (7)	-	21	32	V REF+	S	V REF+
M1	K1	G8	13	22	33	V DDA	S	V DDA
J2	G2	F6	14	23	34	PA0-WKUP	I/O		PA0 WKUP/USART2_CTS (8) ADC123_IN0 TIM2_CH1_ETR TIM5_CH1/TIM8_ETR
K2	H2	E6	15	24	35	PA1	I/O		PA1 USART2_RTS (8) ADC123_IN1/ TIM5_CH2/TIM2_CH2 (8)
L2	J2	H8	16	25	36	PA2	I/O		PA2 USART2_TX (8) /TIM5_CH3 ADC123_IN2/ TIM2_CH3 (8)
M2	K2	G7	17	26	37	PA3	I/O		PA3 USART2_RX (8) /TIM5_CH4 ADC123_IN3/TIM2_CH4 (8)
G4	E4	F5	18	27	38	V SS_4	S		V SS_4
F4	F4	G6	19	28	39	V DD_4	S		V DD_4
J3	G3	H7	20	29	40	PA4	I/O		PA4 SPI1_NSS (8) / USART2_CK (8) DAC_OUT1/ADC12_IN4
K3	H3	E5	21	30	41	PA5	I/O		PA5 SPI1_SCK (8) DAC_OUT2 ADC12_IN5
L3	J3	G5	22	31	42	PA6	I/O		PA6 SPI1_MISO (8) TIM8_BKIN/ADC12_IN6 TIM3_CH1 (8)	TIM1_BKIN
M3	K3	G4	23	32	43	PA7	I/O		PA7 SPI1_MOSI (8) / TIM8_CH1N/ADC12_IN7 TIM3_CH2 (8)	TIM1_CH1N
J4	G4	H6	24	33	44	PC4	I/O		PC4 ADC12_IN14
K4	H4	H5	25	34	45	PC5	I/O		PC5 ADC12_IN15
L4	J4	H4	26	35	46	PB0	I/O		PB0 ADC12_IN8/TIM3_CH3 TIM8_CH2N	TIM1_CH2N
M4	K4	F4	27	36	47	PB1	I/O		PB1 ADC12_IN9/TIM3_CH4 (8) TIM8_CH3N	TIM1_CH3N
J5	G5	H3	28	37	48	PB2	I/O	FT	PB2/BOOT1
M5	-	-	-	-	49	PF11	I/O	FT	PF11 FSMC_NIOS16
L5	-	-	-	-	50	PF12	I/O	FT	PF12 FSMC_A6
H5	-	-	-	-	51	V SS_6	S		V SS_6

Table 5. High-density STM32F103xx pin definitions (continued)

Pins	Pins	Pins	Pins	Pins	Pins		Type (1) (2)	Main function (3) (after reset)	Alternate functions (4)	Alternate functions (4)
BGA144	BGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	I / O Level	Main function (3) (after reset)	Default	Remap
G5	-	-	-	-	52	V DD_6	S	V DD_6
K5	-	-	-	-	53	PF13	I/O FT	PF13	FSMC_A7
M6	-	-	-	-	54	PF14	I/O FT	PF14	FSMC_A8
L6	-	-	-	-	55	PF15	I/O FT	PF15	FSMC_A9
K6	-	-	-	-	56	PG0	I/O FT	PG0	FSMC_A10
J6	-	-	-	-	57	PG1	I/O FT	PG1	FSMC_A11
M7	H5	-	-	38	58	PE7	I/O FT	PE7	FSMC_D4	TIM1_ETR
L7	J5	-	-	39	59	PE8	I/O FT	PE8	FSMC_D5	TIM1_CH1N
K7	K5	-	-	40	60	PE9	I/O FT	PE9	FSMC_D6	TIM1_CH1
H6	-	-	-	-	61	V SS_7	S	V SS_7
G6	-	-	-	-	62	V DD_7	S	V DD_7
J7	G6	-	-	41	63	PE10	I/O FT	PE10	FSMC_D7	TIM1_CH2N
H8	H6	-	-	42	64	PE11	I/O FT	PE11	FSMC_D8	TIM1_CH2
J8	J6	-	-	43	65	PE12	I/O FT	PE12	FSMC_D9	TIM1_CH3N
K8	K6	-	-	44	66	PE13	I/O FT	PE13	FSMC_D10	TIM1_CH3
L8	G7	-	-	45	67	PE14	I/O FT	PE14	FSMC_D11	TIM1_CH4
M8	H7	-	-	46	68	PE15	I/O FT	PE15	FSMC_D12	TIM1_BKIN
M9	J7	G3	29	47	69	PB10	I/O FT	PB10	I2C2_SCL/USART3_TX (8)	TIM2_CH3
M10	K7	F3	30	48	70	PB11	I/O FT	PB11	I2C2_SDA/USART3_RX (8)	TIM2_CH4
H7	E7	H2	31	49	71	V SS_1	S	V SS_1
G7	F7	H1	32	50	72	V DD_1	S	V DD_1
M11	K8	G2	33	51	73	PB12	I/O FT	PB12	SPI2_NSS/I2S2_WS/ I2C2_SMBA/ USART3_CK (8) / TIM1_BKIN (8)
M12	J8	G1	34	52	74	PB13	I/O FT	PB13	SPI2_SCK/I2S2_CK USART3_CTS (8) / TIM1_CH1N
L11	H8	F2	35	53	75	PB14	I/O FT	PB14	SPI2_MISO/TIM1_CH2N USART3_RTS (8)
L12	G8	F1	36	54	76	PB15	I/O FT	PB15	SPI2_MOSI/I2S2_SD TIM1_CH3N (8)
L9	K9	-	-	55	77	PD8	I/O FT	PD8	FSMC_D13	USART3_TX
K9	J9	-	-	56	78	PD9	I/O FT	PD9	FSMC_D14	USART3_RX
J9	H9	-	-	57	79	PD10	I/O FT	PD10	FSMC_D15	USART3_CK

Table 5. High-density STM32F103xx pin definitions (continued)

Table 5. High-density STM32F103xx pin definitions (continued)

Pins	Pins	Pins	Pins	Pins	Pins	Pin name	Type (1) / O Level (2)	Main function (3) (after reset)	Alternate functions (4)	Alternate functions (4)
BGA144	BGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	I	Main function (3) (after reset)	Default	Remap
H9	G9	-	-	58	80	PD11	I/O FT	PD11	FSMC_A16	USART3_CTS
L10	K10	-	-	59	81	PD12	I/O FT	PD12	FSMC_A17	TIM4_CH1 / USART3_RTS
K10	J10	-	-	60	82	PD13	I/O FT	PD13	FSMC_A18	TIM4_CH2
G8	-	-	-	-	83	V SS_8	S	V SS_8
F8	-	-	-	-	84	V DD_8	S	V DD_8
K11	H10	-	-	61	85	PD14	I/O FT	PD14	FSMC_D0	TIM4_CH3
K12	G10	-	-	62	86	PD15	I/O FT	PD15	FSMC_D1	TIM4_CH4
J12	-	-	-	-	87	PG2	I/O FT	PG2	FSMC_A12
J11	-	-	-	-	88	PG3	I/O FT	PG3	FSMC_A13
J10	-	-	-	-	89	PG4	I/O FT	PG4	FSMC_A14
H12	-	-	-	-	90	PG5	I/O FT	PG5	FSMC_A15
H11	-	-	-	-	91	PG6	I/O FT	PG6	FSMC_INT2
H10	-	-	-	-	92	PG7	I/O FT	PG7	FSMC_INT3
G11	-	-	-	-	93	PG8	I/O FT	PG8
G10	-	-	-	-	94	V SS_9	S	V SS_9
F10	-	-	-	-	95	V DD_9	S	V DD_9
G12	F10	E1	37	63	96	PC6	I/O FT	PC6	I2S2_MCK/ TIM8_CH1/SDIO_D6	TIM3_CH1
F12	E10	E2	38	64	97	PC7	I/O FT	PC7	I2S3_MCK/ TIM8_CH2/SDIO_D7	TIM3_CH2
F11	F9	E3	39	65	98	PC8	I/O FT	PC8	TIM8_CH3/SDIO_D0	TIM3_CH3
E11	E9	D1	40	66	99	PC9	I/O FT	PC9	TIM8_CH4/SDIO_D1	TIM3_CH4
E12	D9	E4	41	67	100	PA8	I/O FT	PA8	USART1_CK/ TIM1_CH1 (8) /MCO
D12	C9	D2	42	68	101	PA9	I/O FT	PA9	USART1_TX (8) / TIM1_CH2 (8)
D11	D10	D3	43	69	102	PA10	I/O FT	PA10	USART1_RX (8) / TIM1_CH3 (8)
C12	C10	C1	44	70	103	PA11	I/O FT	PA11	USART1_CTS/USBDM CAN_RX (8) /TIM1_CH4 (8)
B12	B10	C2	45	71	104	PA12	I/O FT	PA12	USART1_RTS/USBDP/ CAN_TX (8) /TIM1_ETR (8)
A12	A10	D4	46	72	105	PA13	I/O FT	JTMS- SWDIO		PA13

Table 5. High-density STM32F103xx pin definitions (continued)

Table 5. High-density STM32F103xx pin definitions (continued)

Pins	Pins	Pins	Pins	Pins	Pins	Pin name	Type (1)	Main function (3) (after reset)	Alternate functions (4)	Alternate functions (4)
BGA144	BGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	I / O Level	Main function (3) (after reset)	Default	Remap
C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected	C11 F8 - - 73 106 Not connected
G9	E6	B1	47	74	107	V SS_2	S	V SS_2
F9	F6	A1	48	75	108	V DD_2	S	V DD_2
A11	A9	B2	49	76	109	PA14	I/O FT	JTCK- SWCLK		PA14
A10	A8	C3	50	77	110	PA15	I/O FT	JTDI	SPI3_NSS/ I2S3_WS	TIM2_CH1_ETR PA15 / SPI1_NSS
B11	B9	A2	51	78	111	PC10	I/O FT	PC10	UART4_TX/SDIO_D2	USART3_TX
B10	B8	B3	52	79	112	PC11	I/O FT	PC11	UART4_RX/SDIO_D3	USART3_RX
C10	C8	C4	53	80	113	PC12	I/O FT	PC12	UART5_TX/SDIO_CK	USART3_CK
E10	D8	D8	5	81	114	PD0	I/O FT	OSC_IN (9)	FSMC_D2 (10)	CAN_RX
D10	E8	D7	6	82	115	PD1	I/O FT	OSC_OUT (9)	FSMC_D3 (10)	CAN_TX
E9	B7	A3	54	83	116	PD2	I/O FT	PD2	TIM3_ETR/UART5_RX SDIO_CMD
D9	C7	-	-	84	117	PD3	I/O FT	PD3	FSMC_CLK	USART2_CTS
C9	D7	-	-	85	118	PD4	I/O FT	PD4	FSMC_NOE	USART2_RTS
B9	B6	-	-	86	119	PD5	I/O FT	PD5	FSMC_NWE	USART2_TX
E7	-	-	-	-	120	V SS_10	S	V SS_10
F7	-	-	-	-	121	V DD_10	S	V DD_10
A8	C6	-	-	87	122	PD6	I/O FT	PD6	FSMC_NWAIT	USART2_RX
A9	D6	-	-	88	123	PD7	I/O FT	PD7	FSMC_NE1/FSMC_NCE2	USART2_CK
E8	-	-	-	-	124	PG9	I/O FT	PG9	FSMC_NE2/FSMC_NCE3
D8	-	-	-	-	125	PG10	I/O FT	PG10	FSMC_NCE4_1/ FSMC_NE3
C8	-	-	-	-	126	PG11	I/O FT	PG11	FSMC_NCE4_2
B8	-	-	-	-	127	PG12	I/O FT	PG12	FSMC_NE4
D7	-	-	-	-	128	PG13	I/O FT	PG13	FSMC_A24
C7	-	-	-	-	129	PG14	I/O FT	PG14	FSMC_A25
E6	-	-	-	-	130	V SS_11	S	V SS_11
F6	-	-	-	-	131	V DD_11	S	V DD_11
B7	-	-	-	-	132	PG15	I/O FT	PG15
A7	A7	A4	55	89	133	PB3/	I/O FT	JTDO	SPI3_SCK / I2S3_CK/	PB3/TRACESWO TIM2_CH2 / SPI1_SCK

Table 5. High-density STM32F103xx pin definitions (continued)

Table 5. High-density STM32F103xx pin definitions (continued)

Pins	Pins	Pins	Pins	Pins	Pins	Pin name	(1)	Level (2)		Alternate functions (4)	Alternate functions (4)
BGA144	BGA100	WLCSP64	LQFP64	LQFP100	LQFP144	Pin name	(1)	Level (2)	Main function (3) (after reset)	Default	Remap
A6	A6	B4	56	90	134	PB4	I/O	FT	NJTRST	SPI3_MISO	PB4 / TIM3_CH1 SPI1_MISO
B6	C5	A5	57	91	135	PB5	I/O		PB5	I2C1_SMBA/ SPI3_MOSI I2S3_SD	TIM3_CH2 / SPI1_MOSI
C6	B5	B5	58	92	136	PB6	I/O	FT	PB6	I2C1_SCL (8) / TIM4_CH1 (8)	USART1_TX
D6	A5	C5	59	93	137	PB7	I/O	FT	PB7	I2C1_SDA (8) / FSMC_NADV / TIM4_CH2 (8)	USART1_RX
D5	D5	A6	60	94	138	BOOT0	I		BOOT0
C5	B4	D5	61	95	139	PB8	I/O	FT	PB8	TIM4_CH3 (8) /SDIO_D4	I2C1_SCL/ CAN_RX
B5	A4	B6	62	96	140	PB9	I/O	FT	PB9	TIM4_CH4 (8) /SDIO_D5	I2C1_SDA / CAN_TX
A5	D4	-	-	97	141	PE0	I/O	FT	PE0	TIM4_ETR / FSMC_NBL0
A4	C4	-	-	98	142	PE1	I/O	FT	PE1	FSMC_NBL1
E5	E5	A7	63	99	143	V SS_3	S		V SS_3
F5	F5	A8	64	100	144	V DD_3	S		V DD_3

Table 6. FSMC pin definition

Pins	FSMC	FSMC	FSMC	FSMC	FSMC	LQFP100 BGA100 (1)
Pins	CF	CF/IDE	NOR/PSRAM/ SRAM	NOR/PSRAM Mux	NAND 16 bit	LQFP100 BGA100 (1)
PE2			A23	A23		Yes
PE3			A19	A19		Yes
PE4			A20	A20		Yes
PE5			A21	A21		Yes
PE6			A22	A22		Yes
PF0	A0	A0	A0			-
PF1	A1	A1	A1			-
PF2	A2	A2	A2			-
PF3	A3		A3			-
PF4	A4		A4			-
PF5	A5		A5			-
PF6	NIORD	NIORD				-
PF7	NREG	NREG				-
PF8	NIOWR	NIOWR				-
PF9	CD	CD				-
PF10	INTR	INTR				-
PF11	NIOS16	NIOS16				-
PF12	A6		A6			-
PF13	A7		A7			-
PF14	A8		A8			-
PF15	A9		A9			-
PG0	A10		A10			-
PG1			A11			-
PE7	D4	D4	D4	DA4	D4	Yes
PE8	D5	D5	D5	DA5	D5	Yes
PE9	D6	D6	D6	DA6	D6	Yes
PE10	D7	D7	D7	DA7	D7	Yes
PE11	D8	D8	D8	DA8	D8	Yes
PE12	D9	D9	D9	DA9	D9	Yes
PE13	D10	D10	D10	DA10	D10	Yes
PE14	D11	D11	D11	DA11	D11	Yes
PE15	D12	D12	D12	DA12	D12	Yes
PD8	D13	D13	D13	DA13	D13	Yes

Table 6. FSMC pin definition

Table 6. FSMC pin definition (continued)

Pins	FSMC	FSMC	FSMC	FSMC	FSMC	LQFP100 BGA100 (1)
Pins	CF	CF/IDE	NOR/PSRAM/ SRAM	NOR/PSRAM Mux	NAND 16 bit	LQFP100 BGA100 (1)
PD9	D14	D14	D14	DA14	D14	Yes
PD10	D15	D15	D15	DA15	D15	Yes
PD11			A16	A16	CLE	Yes
PD12			A17	A17	ALE	Yes
PD13			A18	A18		Yes
PD14	D0	D0	D0	DA0	D0	Yes
PD15	D1	D1	D1	DA1	D1	Yes
PG2			A12			-
PG3			A13			-
PG4			A14			-
PG5			A15			-
PG6					INT2	-
PG7					INT3	-
PD0	D2	D2	D2	DA2	D2	Yes
PD1	D3	D3	D3	DA3	D3	Yes
PD3			CLK	CLK		Yes
PD4	NOE	NOE	NOE	NOE	NOE	Yes
PD5	NWE	NWE	NWE	NWE	NWE	Yes
PD6	NWAIT	NWAIT	NWAIT	NWAIT	NWAIT	Yes
PD7			NE1	NE1	NCE2	Yes
PG9			NE2	NE2	NCE3	-
PG10	NCE4_1	NCE4_1	NE3	NE3		-
PG11	NCE4_2	NCE4_2				-
PG12			NE4	NE4		-
PG13			A24	A24		-
PG14			A25	A25		-
PB7			NADV	NADV		Yes
PE0			NBL0	NBL0		Yes
PE1			NBL1	NBL1		Yes

1. Ports F and G are not available in devices delivered in 100-pin packages.

The definition and values of input/output AC characteristics are given in Figure 41 and Table 47 , respectively.

Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 10 .

Table 47. I/O AC characteristics (1)

MODEx[1:0] bit value (1)	Symbol	Parameter	Conditions	Min	Max	Unit
10	f max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2 V to 3.6 V		2	MHz
10	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2 V to 3.6 V		125 (3)	ns
10	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2 V to 3.6 V		125 (3)	ns
01	f max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2 V to 3.6 V		10	MHz
01	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2 V to 3.6 V		25 (3)	ns
01	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2 V to 3.6 V		25 (3)	ns
11	F max(IO)out	Maximum frequency (2)	C L = 30 pF, V DD = 2.7 V to 3.6 V		50	MHz
11	F max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2.7 V to 3.6 V		30	MHz
11	F max(IO)out	Maximum frequency (2)	C L = 50 pF, V DD = 2 V to 2.7 V		20	MHz
11	t f(IO)out	Output high to low level fall time	C L = 30 pF, V DD = 2.7 V to 3.6 V		5 (3)	ns
11	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2.7 V to 3.6 V		8 (3)	ns
11	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 2 V to 2.7 V		12 (3)	ns
11	t r(IO)out	Output low to high level rise time	C L = 30 pF, V DD = 2.7 V to 3.6 V		5 (3)	ns
11	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2.7 V to 3.6 V		8 (3)	ns
11	t r(IO)out	Output low to high level rise time	C L = 50 pF, V DD = 2 V to 2.7 V		12 (3)	ns
-	t EXTIpw	Pulse width of external signals detected by the EXTI controller		10		ns

1. The maximum frequency is defined in Figure 41 .
2. Guaranteed by design, not tested in production.

Figure 41. I/O AC characteristics definition

Figure 41. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics , Table 8: Current characteristics , and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 7. Voltage characteristics

Symbol	Ratings	Min	Max	Unit
V DD -V SS	External main supply voltage (including V DDA and V DD ) (1)	-0.3	4.0	V
V IN	Input voltage on five volt tolerant pin (2)	V SS 0.3	+5.5	V
V IN	Input voltage on any other pin (2)	V SS 0.3	V DD +0.3	V
\	V DDx \		Variations between different V DD power pins
\	V SSX V SS \		Variations between all the different ground pins
V ESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 5.3.12: Absolute maximum ratings (electrical sensitivity)	see Section 5.3.12: Absolute maximum ratings (electrical sensitivity)

Symbol	Ratings	Max.	Unit
I VDD	Total current into V DD /V DDA power lines (source) (1)	150	mA
I VSS	Total current out of V SS ground lines (sink) (1)	150	mA
I IO	Output current sunk by any I/O and control pin	25	mA
I IO	Output current source by any I/Os and control pin	25	mA
I INJ(PIN) (2)(3)	Injected current on NRST pin	± 5	mA
I INJ(PIN) (2)(3)	Injected current on HSE OSC_IN and LSE OSC_IN pins	± 5	mA
I INJ(PIN) (2)(3)	Injected current on any other pin (4)	± 5	mA
I INJ(PIN) (2)	Total injected current (sum of all I/O and control pins) (4)	± 25	mA

1. Negative injection disturbs the analog performance of the device. See note in Section 5.3.18: 12-bit ADC characteristics .
2. When several inputs are submitted to a current injection, the maximum I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with I INJ(PIN) maximum current injection on four I/O port pins of the device.

Table 9. Thermal characteristics

Symbol	Ratings	Value	Unit
T STG	Storage temperature range	-65 to +150	°C
T J	Maximum junction temperature	150	°C

The maximum chip junction temperature (T J max) must never exceed the values given in Table 10: General operating conditions on page 42 .

The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.

Figure 57. Recommended PCB design rules (0.80/0.75 mm pitch BGA)

Figure 58. LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline

Figure 57. Recommended PCB design rules (0.80/0.75 mm pitch BGA)

1. Drawing is not to scale.
2. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 64. LFBGA144 - 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data

Symbol	millimeters	millimeters	millimeters	inches (1)	inches (1)	inches (1)
Symbol	Min	Typ	Max	Typ	Min	Max
A			1.70			0.0669
A1	0.21			0.0083
A2		1.07			0.0421
A3		0.27			0.0106
A4			0.85			0.0335
b	0.35	0.40	0.45	0.0138	0.0157	0.0177
D	9.85	10.00	10.15	0.3878	0.3937	0.3996
D1		8.80			0.3465
E	9.85	10.00	10.15	0.3878	0.3937	0.3996
E1		8.80			0.3465
e		0.80			0.0315
F		0.60			0.0236
ddd		0.10			0.0039
eee		0.15			0.0059
fff		0.08			0.0031

Figure 59. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline

1. Drawing is not to scale.

Table 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data

Symbol	millimeters	millimeters	millimeters	inches (1)	inches (1)	inches (1)
Symbol	Min	Typ	Max	Min	Typ	Max
A			1.700			0.0669
A1	0.270			0.0106
A2		1.085			0.0427
A3		0.30			0.0118
A4			0.80			0.0315
b	0.45	0.50	0.55	0.0177	0.0197	0.0217
D	9.85	10.00	10.15	0.3878	0.3937	0.3996
D1		7.20			0.2835
E	9.85	10.00	10.15	0.3878	0.3937	0.3996
E1		7.20			0.2835
e		0.80			0.0315
F		1.40			0.0551
ddd		0.12				0.0047
eee		0.15				0.0059
fff		0.08				0.0031

Figure 60. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline

Table 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data

1. Drawing is not to scale.
2. Primary datum Z and seating plane are defined by the spherical crowns of the ball.
3. Values in inches are converted from mm and rounded to 4 decimal digits.
4. Dimension is measured at the maximum ball diameter parallel to primary datum Z.

Table 66. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data

Symbol	millimeters	millimeters	millimeters	inches (1)	inches (1)	inches (1)
Symbol	Min	Typ	Max	Min	Typ	Max
A	0.535	0.585	0.635	0.0211	0.0230	0.0250
A1	0.205	0.230	0.255	0.0081	0.0091	0.0100
A2	0.330	0.355	0.380	0.0130	0.0140	0.0150
b (2)	0.290	0.320	0.350	0.0114	0.0126	0.0138
e		0.500			0.0197
e1		3.500			0.1378
F		0.447			0.0176
G		0.483			0.0190
D	4.446	4.466	4.486	0.1750	0.1758	0.1766
E	4.375	4.395	4.415	0.1722	0.1730	0.1738
H		0.250			0.0098
L		0.200			0.0079
eee		0.05			0.0020
aaa		0.10			0.0039
Number of balls	64	64	64	64	64	64

Table 66. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data

Figure 61. Recommended PCB design rules (0.5 mm pitch BGA)

Figure 62. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline (1) Figure 63. Recommended footprint (1)(2)

Figure 61. Recommended PCB design rules (0.5 mm pitch BGA)

1. Drawing is not to scale.
2. Dimensions are in millimeters.
3. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data

Symbol	millimeters	millimeters	millimeters	inches (1)	inches (1)	inches (1)
Symbol	Min	Typ	Max	Min	Typ	Max
A			1.60			0.063
A1	0.05		0.15	0.002		0.0059
A2	1.35	1.40	1.45	0.0531	0.0551	0.0571
b	0.17	0.22	0.27	0.0067	0.0087	0.0106
c	0.09		0.20	0.0035		0.0079
D	21.80	22.00	22.20	0.8583	0.8661	0.874
D1	19.80	20.00	20.20	0.7795	0.7874	0.7953
D3		17.50			0.689
E	21.80	22.00	22.20	0.8583	0.8661	0.874
E1	19.80	20.00	20.20	0.7795	0.7874	0.7953
E3		17.50			0.689
e		0.50			0.0197
L	0.45	0.60	0.75	0.0177	0.0236	0.0295
L1		1.00			0.0394
k	0°	3.5°	7°	0°	3.5°	7°
ccc	0.08	0.08	0.08	0.0031	0.0031	0.0031

Table 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data

Figure 64. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline (1)

Figure 65. Recommended footprint (1)(2)

1. Drawing is not to scale.
2. Dimensions are in millimeters.
3. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 68. LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data

Symbol	millimeters	millimeters	millimeters	inches (1)	inches (1)	inches (1)
Symbol	Min	Typ	Max	Min	Typ	Max
A			1.60			0.063
A1	0.05		0.15	0.002		0.0059
A2	1.35	1.40	1.45	0.0531	0.0551	0.0571
b	0.17	0.22	0.27	0.0067	0.0087	0.0106
c	0.09		0.20	0.0035		0.0079
D	15.80	16.00	16.20	0.622	0.6299	0.6378
D1	13.80	14.00	14.20	0.5433	0.5512	0.5591
D3		12.00			0.4724
E	15.80	16.00	16.20	0.622	0.6299	0.6378
E1	13.80	14.00	14.20	0.5433	0.5512	0.5591
E3		12.00			0.4724
e		0.50			0.0197
L	0.45	0.60	0.75	0.0177	0.0236	0.0295
L1		1.00			0.0394
k	0°	3.5°	7°	0°	3.5°	7°
ccc	0.08	0.08	0.08	0.0031	0.0031	0.0031

Table 68. LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data

Figure 66. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline (1)

Figure 67. Recommended footprint (1)(2)

Table 69. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data

Symbol	millimeters	millimeters	millimeters	inches (1)	inches (1)	inches (1)
Symbol	Min	Typ	Max	Min	Typ	Max
A			1.60			0.0630
A1	0.05		0.15	0.0020		0.0059
A2	1.35	1.40	1.45	0.0531	0.0551	0.0571
b	0.17	0.22	0.27	0.0067	0.0087	0.0106
c	0.09		0.20	0.0035		0.0079
D		12.00			0.4724
D1		10.00			0.3937
E		12.00			0.4724
E1		10.00			0.3937
e		0.50			0.0197
	0°	3.5°	7°	0°	3.5°	7°
L	0.45	0.60	0.75	0.0177	0.0236	0.0295
L1		1.00			0.0394
N	Number of pins	Number of pins	Number of pins	Number of pins	Number of pins	Number of pins
N	64	64	64	64	64	64

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Table 69. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package mechanical data