Part: Si5351A/B/C — Silicon Labs Type: I2C-Programmable Any-Frequency CMOS Clock Generator + VCXO

Description: The Si5351 is an I2C configurable clock generator capable of generating up to 8 non-integer-related frequencies from 8 kHz to 160 MHz with 0 ppm error, using a PLL/VCXO + high resolution MultiSynth fractional divider architecture.

Operating Conditions:

• Supply voltage (VDD): 2.25–3.6 V
• Output buffer voltage (VDDOx): 1.71–3.6 V
• Operating temperature: -40 to 85 °C
• CLKIN frequency range: 10–100 MHz
• Output frequency range: 0.008–160 MHz

Absolute Maximum Ratings:

• Max supply voltage (VDD): 3.8 V
• Max input voltage (CLKIN, SCL, SDA): 3.8 V
• Max junction temperature: 150 °C

Key Specs:

• Core supply current (3 outputs enabled): 22 mA (typ)
• Core supply current (8 outputs enabled): 27 mA (typ)
• Core supply current (Power Down): 20 μA (max)
• Output buffer supply current (per output, CL=5 pF): 2.2 mA (typ)
• Output period jitter: 100 ps pk-pk (max)
• RMS phase jitter (12 kHz-20 MHz): 11 ps rms (max)
• I2C standard mode speed: 100 kbps
• I2C fast mode speed: 400 kbps

Features:

• Generates up to 8 non-integer-related frequencies from 8 kHz to 160 MHz
• I2C user definable configuration
• Exact frequency synthesis at each output (0 ppm error)
• Highly linear VCXO (Si5351B only)
• Optional clock input (CLKIN)
• Low output period jitter: 100 ps pp
• Glitchless frequency changes
• Separate voltage supply pins: Core VDD (2.5 or 3.3 V), Output VDDO (1.8, 2.5, or 3.3 V)
• Configurable spread spectrum selectable at each output
• Operates from a low-cost, fixed frequency crystal: 25 or 27 MHz
• Supports static phase offset
• Programmable rise/fall time control

Applications:

• HDTV, DVD/Blu-ray, set-top box
• Audio/video equipment, gaming
• Printers, scanners, projectors
• Residential gateways
• Networking/communication
• Servers, storage
• XO replacement

Package:

• 10-MSOP (3 outputs)
• 24-QSOP (8 outputs)
• 20-QFN (4x4 mm) (8 outputs)

• Generates up to 8 non-integer-related frequencies from 8 kHz to 160 MHz
• I 2 C user definable configuration
• Exact frequency synthesis at each output (0 ppm error)
• Highly linear VCXO
• Optional clock input (CLKIN)
• Low output period jitter: 100 ps pp
• Glitchless frequency changes
• Separate voltage supply pins:
• Core VDD: 2.5 or 3.3 V
• Output VDDO: 1.8, 2.5, or 3.3 V
• Excellent PSRR eliminates external power supply filtering
• Very low power consumption
• Adjustable output-output delay
• Configurable spread spectrum selectable at each output
• Available in 3 packages types:
• 10-MSOP: 3 outputs
• Operates from a low-cost, fixed frequency crystal: 25 or 27 MHz
• 24-QSOP: 8 outputs
• 20-QFN (4x4 mm): 8 outputs
• Supports static phase offset
• Programmable rise/fall time control

• HDTV, DVD/Blu-ray, set-top box
• Audio/video equipment, gaming
• Printers, scanners, projectors

SI5351A 20-Pin QFN Pinout

Notes

• Part Number Clarification: The datasheet section header states "Si5351A Pin Descriptions" and covers both 20-Pin QFN and 24-Pin QSOP variants. The pinout above is for the 20-Pin QFN package as shown in the attached pin diagram labeled "Si5351A 20-QFN Top View."
• Requested Part (SI5351): The datasheet provided covers the Si5351A variant, not the base SI5351. If a pinout for the base SI5351 exists in the full datasheet, it was not included in this excerpt. The Si5351A is the variant documented here.
• GND Center Pad: The 20-QFN package includes a center thermal/ground pad in addition to the four corner GND pins (pins 5, 8, 17, 19 in the 24-QSOP variant). For the 20-QFN, the center pad is the primary GND connection point.

Table 1. Recommended Operating Conditions

Notes: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD and VDDOx can be operated at independent voltages.

Power supply sequencing for VDD and VDDOx requires that both voltage rails are powered at the same time.

1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.

Table 14. 24-QSOP Package Dimensions

Table 14. 24-QSOP Package Dimensions

1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.