SI4438-C2A-GM
High-Performance, Low-Current TransceiverThe SI4438-C2A-GM is a high-performance, low-current transceiver from Silicon Laboratories. View the full SI4438-C2A-GM datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
Silicon Laboratories
Category
High-Performance, Low-Current Transceiver
Package
QFN-20 Pb-free
Overview
Part: Si4438 — Silicon Laboratories Type: High-Performance, Low-Current Transceiver Description: The Si4438 is a high-performance, low-current sub-GHz transceiver operating in the 425-525 MHz frequency range, offering -124 dBm receive sensitivity and up to +20 dBm output power, targeted at China smart meter applications.
Operating Conditions:
- Supply voltage: 1.8–3.8 V
- Operating temperature: -40 to +85 °C
- Frequency range: 425–525 MHz
Absolute Maximum Ratings:
- Max supply voltage: 3.8 V
- Max RX input power: +10 dBm
- Max junction temperature: +105 °C
- Max storage temperature: -55 to +150 °C
Key Specs:
- Receive sensitivity: -124 dBm (BER < 0.1%, 500 bps, GFSK, BT = 0.5, f = 250Hz)
- Max output power: +20 dBm
- RX mode current: 13.7 mA
- TX mode current: 75 mA (+20 dBm output power, class-E match, 490 MHz, 3.3 V)
- Shutdown current: 30 nA
- Standby current: 40 nA
- Data rate (GFSK): 0.1 to 500 kbps
- Data rate (OOK): 0.1 to 120 kbps
- Adjacent channel selectivity: -60 dB (1-Ch Offset, 450 MHz)
Features:
- Modulation: (G)FSK, OOK
- Preamble Sense Mode
- Fast wake and hop times
- Excellent selectivity performance (58 dB adjacent channel, 75 dB blocking at 1 MHz)
- Antenna diversity and T/R switch control
- Highly configurable packet handler
- TX and RX 64 byte FIFOs
- Auto frequency control (AFC)
- Automatic gain control (AGC)
- Low BOM
- Low battery detector
- Temperature sensor
- IEEE 802.15.4g ready
- Suitable for China regulatory (State Grid)
Applications:
- China smart meters
- Electric meters
Package:
- 20-Pin QFN package
Features
- Frequency range = 425-525 MHz
- Receive sensitivity = -124 dBm
- Modulation
- (G)FSK
- OOK
- Max output power
- +20 dBm
- Low active power consumption
- 14 mA RX
- Ultra low current powerdown modes
- 30 nA shutdown, 40 nA standby
- Data rate = 100 bps to 500 kbps
- Preamble Sense Mode
- 6 mA average Rx current at 1.2 kbps
- Fast wake and hop times
- Power supply = 1.8 to 3.8 V
Pin Configuration
| Pin | Pin Name | I/0 | Description |
|---|---|---|---|
| 1 | SDN | I | Shutdown Input Pin . 0-VDD V digital input. SDNshould be = 0 in all modes except Shutdown mode. When SDN = 1, the chip will be completely shut down, and the contents of the registers will be lost. |
| 2 | RXp | I | Differential RF Input Pins of the LNA. See application schematic for example matching network. |
| 3 | RXn | I | Differential RF Input Pins of the LNA. See application schematic for example matching network. |
| 4 | TX | O | Transmit Output Pin. The PA output is an open-drain connection, so the L-C match must supply VDD (+3.3 VDC nominal) to this pin. |
| 5 | NC | It is recommended to connect this pin to GND per the reference design schematic. Not connected internally to any circuitry. | |
| 6 | VDD | VDD | +1.8 to +3.8 V Supply Voltage Input to Internal Regulators. The recommended VDD supply voltage is +3.3 V. |
| 7 | TXRAMP | O | Programmable Bias Output with Ramp Capability for External FET PA. See "5.4. Transmitter (TX)" on page 27. |
| 8 | VDD | VDD | +1.8 to +3.8 V Supply Voltage Input to Internal Regulators. The recommended VDD supply voltage is +3.3 V. |
| 9 | GPIO0 | I/O | General Purpose Digital I/O. May be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. |
| 10 | GPIO1 | I/O | General Purpose Digital I/O. May be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. |
| Pin | Pin Name | I/0 | Description |
| 11 | nIRQ | O | General Microcontroller Interrupt Status Output. When the Si4438 exhibits any one of the interrupt events, the nIRQ pin will be set low = 0. The Microcontroller can then determine the state of the interrupt by reading the interrupt status. No external resistor pull-up is required, but it may be desirable if multiple interrupt lines are connected. |
| 12 | SCLK | I | Serial Clock Input. 0-VDD V digital input. This pin provides the serial data clock function for the 4-line serial data bus. Data is clocked into the Si4438 on positive edge transi- tions. |
| 13 | SDO | O | 0-VDD V Digital Output. Provides a serial readback function of the internal control registers. |
| 14 | SDI | I | Serial Data Input. 0-VDD V digital input. This pin provides the serial data stream for the 4-line serial data bus. |
| 15 | nSEL | I | Serial Interface Select Input. 0-VDD V digital input. This pin provides the Select/Enable function for the 4-line serial data bus. |
| 16 | XOUT | O | Crystal Oscillator Output. Connect to an external 25 to 32 MHz crystal, or leave floating when driving with an external source on XIN. |
| 17 | XIN | I | Crystal Oscillator Input. Connect to an external 25 to 32 MHz crystal, or connect to an external source. |
| 18 | GND | GND | When using a XTAL, leave floating per the reference design schematic. When using a TCXO, connect to TCXO GND which should be separate from the board reference ground plane. |
| 19 | GPIO2 | I/O | General Purpose Digital I/O. May be configured through the registers to perform various functions, including Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery |
| 20 | GPIO3 | I/O | Detect, TRSW, AntDiversity control, etc. |
| PKG | PADDLE_GND | GND | The exposed metal paddle on the bottom of the Si4438 supplies the RF and circuit ground(s) for the entire chip. It is very important that a good solder con- nection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4438. |
Electrical Characteristics
Table 1. DC Characteristics *
| Parameter | Symbol | Test Condition | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| Supply Voltage Range | V DD | 1.8 | 3.3 | 3.8 | V | |
| Power Saving Modes | I Shutdown | RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF | - | 30 | - | nA |
| Power Saving Modes | I Standby | Register values maintained and RC oscillator/WUT OFF | - | 40 | - | nA |
| Power Saving Modes | I SleepRC | RC Oscillator/WUT ON and all register values maintained, and all other blocks OFF | - | 740 | - | nA |
| Power Saving Modes | I SleepXO | Sleep current using an external 32 kHz crystal. | - | 1.7 | - | μ A |
| Power Saving Modes | I Sensor -LBD | Low battery detector ON, register values main- tained, and all other blocks OFF | - | 1 | - | μ A |
| Power Saving Modes | I Ready | Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF | - | 1.8 | - | mA |
| Preamble Sense Mode Current | I psm | Duty cycling during preamble search, 1.2 kbps, 4 byte preamble | - | 6 | - | mA |
| Preamble Sense Mode Current | I psm | Fixed 1 s wakeup interval, 50 kbps, 5 byte pream- ble | - | 10 | - | μ A |
| TUNE Mode Current | I Tune_RX | RX Tune | - | 7.6 | - | mA |
| TUNE Mode Current | I Tune_TX | TX Tune | - | 7.8 | - | mA |
| RX Mode Current | I RXH | - | 13.7 | - | mA | |
| TX Mode Current (Si4438) | I TX_+20 | +20 dBm output power, class-E match, 490 MHz, 3.3 V | - | 75 | - | mA |
*Note: All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from -40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
**Table 1. DC Characteristics ***
Table 2. Synthesizer AC Electrical Characteristics 1
| Parameter | Symbol | Test Condition | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| Synthesizer Frequency Range (Si4438) | F SYN | 425 | - | 525 | MHz | |
| Synthesizer Frequency Resolution 2 | F RES-525 | 425-525 MHz | - | 14.3 | - | Hz |
| Synthesizer Settling Time | t LOCK | Measured from exiting Ready mode with XOSC running to any frequency. Including VCO Calibration. | - | 50 | - | μ s |
| Phase Noise | L (f M ) | F = 10 kHz, 460 MHz | - | -109 | - | dBc/Hz |
| Phase Noise | L (f M ) | F = 100 kHz, 460 MHz | - | -111 | - | dBc/Hz |
| Phase Noise | L (f M ) | F = 1 MHz, 460 MHz | - | -131 | - | dBc/Hz |
| Phase Noise | L (f M ) | F = 10 MHz, 460 MHz | - | -141 | - | dBc/Hz |
-
All minimum and maximum values are guaranteed across the recommended operating conditions of supply voltage and from -40 to +85 °C unless otherwise stated. All typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated.
-
Default API setting for modulation deviation resolution is double the typical value specified.
Absolute Maximum Ratings
| Parameter | Value | Unit |
|---|---|---|
| V DD to GND | -0.3, +3.8 | V |
| Instantaneous V to GND on TX Output Pin | RF-peak -0.3, +8.0 | V |
| Sustained V to GND | RF-peak on TX Output Pin -0.3, +6.5 | V |
| Voltage on Digital | Control Inputs -0.3, V DD + 0.3 | V |
| Voltage on Analog Inputs | -0.3, V DD + 0.3 | V |
| Voltage on XIN Input when | using a TCXO -0.7, V DD + 0.3 | V |
| RX Input Power | +10 | dBm |
*Note: Stresses beyond those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX matching network design will influence TX V RF-peak on TX output pin. Caution: ESD sensitive device.
Thermal Information
| Parameter | Value | Unit |
|---|---|---|
| Operating Ambient Temperature Range T A | -40 to +85 | C |
| Thermal Impedance JA | 25 | C / W |
| Junction Temperature T JMAX | +105 | C |
| Storage Temperature Range T STG | -55 to +150 | C |
Package Information
Figure 16 illustrates the package details for the Si4438. Table 16 lists the values for the dimensions shown in the illustration.
Figure 16. 20-Pin Quad Flat No-Lead (QFN)
Table 16. Package Dimensions
| Dimension | Min | Nom | Max |
|---|---|---|---|
| A | 0.80 | 0.85 | 0.90 |
| A1 | 0.00 | 0.02 | 0.05 |
| A3 | 0.20 REF | 0.20 REF | 0.20 REF |
| b | 0.18 | 0.25 | 0.30 |
| D | 4.00 BSC | 4.00 BSC | 4.00 BSC |
| D2 | 2.45 | 2.60 | 2.75 |
| e | 0.50 BSC | 0.50 BSC | 0.50 BSC |
| E | 4.00 BSC | 4.00 BSC | 4.00 BSC |
| E2 | 2.45 | 2.60 | 2.75 |
| L | 0.30 | 0.40 | 0.50 |
| aaa | 0.15 | 0.15 | 0.15 |
| bbb | 0.15 | 0.15 | 0.15 |
| ccc | 0.10 | 0.10 | 0.10 |
| ddd | 0.10 | 0.10 | 0.10 |
| eee | 0.08 | 0.08 | 0.08 |
- All dimensions are shown in millimeters (mm) unless otherwise noted.
- Dimensioning and tolerancing per ANSI Y14.5M-1994.
- This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VGGD-8.
- Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| SI4438 | Silicon Laboratories | — |
| SI4438-C | Silicon Laboratories | — |
| SI4438-C2A-GMR | Silicon Laboratories | QFN-20 |
Get structured datasheet data via API
Get started free