MM32F0141C4Q

Part: MM32F0140C7P — MindMotion

Type: Arm Cortex-M0 32-bit Microcontroller

Description: Arm Cortex-M0 based 32-bit MCU in the MM32F0140 family, running at up to 72 MHz from a 2.0–5.5 V supply.

Operating Conditions:

• Supply voltage: VDD 2.0–5.5 V; VDDA 2.5–5.5 V (performance guaranteed), 2.0–2.5 V (performance not guaranteed); VDDA must be the same as VDD
• Operating temperature: -40 to 85 °C (industrial level); -40 to 105 °C (extended industrial level)
• Max AHB/APB1/APB2 clock frequency: 72 MHz
• Junction temperature: -40 to 105 °C (industrial), -40 to 125 °C (extended industrial)

Absolute Maximum Ratings:

• Max supply voltage (VDD − VSS, including VDDA/VSSA): 5.8 V (min -0.3 V)
• Input voltage on other pins: VSS − 0.3 V to VDD + 0.3 V
• Total current through VDD/VDDA pins: +120 mA
• Total current through VSS/VSSA pins: -120 mA
• Output sink/source current on any I/O or control pin: +25 mA / -25 mA
• NRST and HSE OSC_IN pin injection current: ±5 mA
• Max junction temperature: 125 °C (stated in the footnotes to Table 5-3 as the absolute maximum)

Key Specs:

• VDD operating range: 2.0 V min, 3.3 V typ, 5.5 V max
• VDDA operating range: 2.5–5.5 V with guaranteed performance
• Max AHB/APB clock: 72 MHz
• Power dissipation (TA = 85 °C or 105 °C): LQFP48 357 mW, LQFP32 333 mW, QFN32 5x5 mm² 571 mW, TSSOP20 270 mW
• Max VDD–VDDA difference: 300 mV during power-up and normal operation

Features:

• Arm Cortex-M0 core
• Up to 72 MHz bus clocks
• Peripherals include UART, I2C, SPI, I2S, FlexCAN, ADC, comparator, DMA, hardware divider, CRC, advanced/general-purpose/basic timers and watchdogs
• SWD debug interface
• Low-power modes (Sleep, Stop, Standby)
• Power supply supervisors and an internal voltage regulator

Applications:

• General-purpose embedded control

Package:

• Package options in the MM32F0140 family: LQFP48, LQFP32, QFN32 (5x5 mm²), QFN32 (4x4 mm²), TSSOP20

• Core and system

• -32-bit Arm ® Cortex ® ­M0.

• -Frequency up to 72MHz.

• Memory

• -Up to 64KB embedded Flash storage.

• -Up to 8KB SRAM.

• -Embedded Bootloader to support In-System-Programming (ISP).

• Clock, reset and power management

• -Power supply ranges from 2.0 to 5.5V.

• -Power-on and Power-down reset (POR/PDR), Programmable voltage detector (PVD).

• -4 to 24MHz high speed crystal oscillator.

• -8MHz factory-trimmed high speed RC oscillator.

• -Integrated PLL to generate up to 72MHz system clock and support multiple prescaler rate to provide clock sources to bus matrix and peripherals.

• -40KHz low speed oscillator.

• Low power

• -Multiple low power modes including Sleep mode, Stop mode, Deep Stop mode and Standby mode.

• One DMA controller with 5 channels to support peripherals including timers, ADC, UART, I2C, SPI, and FlexCAN.

• Total 9 timers:

• -One 16-bit 4-channel advanced timer (TIM1), each channel providing two PWM output including one complementary output, supports hardware dead-time insertion and emergency break when fault detected.

• -One 16-bit general purpose timer (TIM3) and one 32-bit general purpose timer (TIM2), with up to four input capture or output compare channels and can be used for infrared decode.

• -Three 16-bit basic timers (TIM14 / TIM16 / TIM17), with one input capture or output compare channel and one complementary output, support hardware deadtime insertion, emergency break when fault detected, and integrated modulator circuit for infrared control.

• -Two watchdog timers, including one independent watchdog (IWDG) and one window watchdog (WWDG).

• -One 24-bit Systick timer.

• Up to 40 fast I/O ports:

• -All I/O ports can be mapped to 16 external interrupts.

• -All I/O ports can accept input or generate output signal voltage level is not higher than VDD.

• Up to 7 communication interfaces:

• -Three UART.

• -One I2C.

• -Two SPI (support I2S mode).

• -One FlexCAN module supports CAN 2.0B interface.

• One 12-bit Analog-to-Digital converter (ADC), support 1μs conversion duration, with up to 14 external inputs and 2 internal inputs

• -Conversion range: 0 to VDDA.

• -Configurable sampling cycles and resolution.

• -On-chip temperature sensor.

• -On-chip voltage sensor.

• One high speed analog comparator

• 32-bit hardware divider

• Embedded CRC engine

• 96bit unique chip ID (UID)

• Debug mode

• -Serial Wire Debug (SWD).

• Available in LQFP48, LQFP32, QFN32 and TSSOP20 packages

Table 4-1 Pin assignment table

1. I = input, O = output, S = power pins, HiZ = high resistance state.
2. TC: standard IO. Input signal level should not exceed VDD.

The definitions and values of the input and output AC characteristics are given in the following figure and table, respectively.

Unless otherwise stated, the parameters listed in the following table are provided under the ambient temperature and supply voltage in accordance with the condition Table 5-3.

Table 5-23 I/O AC characteristics (1)(2)(3)

1. The speed of the I/O port can be configured through MODEx[1:0]. Refer to the description of the GPIO port configuration register in this chip user manual.
2. The maximum frequency is defined in Figure 5-8.
3. Guaranteed by design, not tested in production.

Figure 5-8 I/O AC characteristics

Stresses above the absolute maximum ratings given in "Absolute Group Maximum Ratings" list (Table 5-1, Table 5-2 and Table 5-3) may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 5-1 Voltage characteristics

1. All power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply system within the permitted range.
2. The maximum value of VIN must be respected. Refer to the table below for the maximum allowed injected current values.
3. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to an external power supply in the permitted range.
4. This current consumption must be correctly distributed to all I/O and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP package.
5. The reverse injection current can interfere with the analog performance of the device.
6. When VIN > VDDA, a positive injected current is generated; when VIN < VSS, a reverse injected current is generated. Do not exceed IINJ(PIN).
7. When there is simultaneous injection current for multiple inputs, the maximum value of ΣIINJ(PIN) is equal to the sum of the absolute values of the forward injection current and the reverse injection current (instantaneous value) .

Table 5-2 Current characteristics