Part: MK66FN2M0VLQ18R — NXP Type: ARM Cortex-M4F Microcontroller Description: 180 MHz ARM Cortex-M4F microcontroller with DSP and FPU, up to 2 MB Flash, 256 KB SRAM, Dual USB, and 10/100 Mbit/s Ethernet MAC.

Operating Conditions:

• Supply voltage: 1.71 to 3.6 V
• Operating temperature: -40 to 105 °C
• Max CPU frequency: 180 MHz

Absolute Maximum Ratings:

• Max supply voltage: 3.8 V
• Max continuous current: 300 mA (Digital supply current)
• Max junction/storage temperature: 150 °C

Key Specs:

• Core: ARM Cortex-M4F with DSP and FPU
• Max CPU frequency: 180 MHz
• Program Flash Memory: Up to 2 MB
• SRAM: 256 KB
• Digital supply voltage (V DD): 1.71 to 3.6 V
• Analog supply voltage (V DDA): 1.71 to 3.6 V
• Input leakage current (I IN): 0.5 μA (Max, V SS ≤ V IN ≤ V DD)
• Internal pullup/pulldown resistors (R PU/R PD): 20 kΩ (Min), 50 kΩ (Max)

Features:

• Multiple low-power modes
• Memory protection unit
• Hardware random-number generator
• DES, AES, SHA accelerator (CAU)
• Dual USB (High Speed and Full Speed OTG)
• 10/100 Mbit/s Ethernet MAC with IEEE 1588
• Two 16-bit SAR ADCs and two 12-bit DACs
• Four analog comparators
• Secure Digital Host Controller (SDHC)
• I2S module
• Low-power hardware touch sensor interface (TSI)

Applications:

Package:

• MAPBGA 144-pin
• LQFP 144-pin

MK66FN2M0VLQ18R – LQFP-144 Pinout

Pin	Pin Name	Type	Default	ALT0	ALT1	ALT2	ALT3	ALT4	ALT5	ALT6	ALT7	EzPort
1	PTE0	I/O	ADC1_SE4a	ADC1_SE4a	PTE0	SPI1_PCS1	UART1_TX	SDHC0_D1	TRACE_CLKOUT	I2C1_SDA	RTC_CLKOUT	—
2	PTE1/LLWU_P0	I/O	ADC1_SE5a	ADC1_SE5a	PTE1/LLWU_P0	SPI1_SOUT	UART1_RX	SDHC0_D0	TRACE_D3	I2C1_SCL	SPI1_SIN	—
3	PTE2/LLWU_P1	I/O	ADC1_SE6a	ADC1_SE6a	PTE2/LLWU_P1	SPI1_SCK	UART1_CTS_b	SDHC0_DCLK	TRACE_D2	—	—	—
4	PTE3	I/O	ADC1_SE7a	ADC1_SE7a	PTE3	SPI1_SIN	UART1_RTS_b	SDHC0_CMD	TRACE_D1	—	SPI1_SOUT	—
5	VDD	P	VDD	VDD	—	—	—	—	—	—	—	—
6	VSS	P	VSS	VSS	—	—	—	—	—	—	—	—
7	PTE4/LLWU_P2	I/O	DISABLED	—	PTE4/LLWU_P2	SPI1_PCS0	UART3_TX	SDHC0_D3	TRACE_D0	—	—	—
8	PTE5	I/O	DISABLED	—	PTE5	SPI1_PCS2	UART3_RX	SDHC0_D2	—	FTM3_CH0	—	—
9	PTE6/LLWU_P16	I/O	DISABLED	—	PTE6/LLWU_P16	SPI1_PCS3	UART3_CTS_b	I2S0_MCLK	—	FTM3_CH1	USB0_SOF_OUT	—
10	PTE7	I/O	DISABLED	—	PTE7	—	UART3_RTS_b	I2S0_RXD0	—	FTM3_CH2	—	—
11	PTE8	I/O	DISABLED	—	PTE8	I2S0_RXD1	I2S0_RX_FS	LPUART0_TX	FTM3_CH3	—	—	—
12	PTE9/LLWU_P17	I/O	DISABLED	—	PTE9/LLWU_P17	I2S0_TXD1	I2S0_RX_BCLK	LPUART0_RX	FTM3_CH4	—	—	—
13	PTE10/LLWU_P18	I/O	DISABLED	—	PTE10/LLWU_P18	I2C3_SDA	I2S0_TXD0	LPUART0_CTS_b	FTM3_CH5	USB1_ID	—	—
14	PTE11	I/O	DISABLED	—	PTE11	I2C3_SCL	I2S0_TX_FS	LPUART0_RTS_b	FTM3_CH6	—	—	—
15	PTE12	I/O	DISABLED	—	PTE12	—	I2S0_TX_BCLK	—	FTM3_CH7	—	—	—
16	VDD	P	VDD	VDD	—	—	—	—	—	—	—	—
17	VSS	P	VSS	VSS	—	—	—	—	—	—	—	—
18	VSS	P	VSS	VSS	—	—	—	—	—	—	—	—
19	USB0_DP	I/O	USB0_DP	USB0_DP	—	—	—	—	—	—	—	—
20	USB0_DM	I/O	USB0_DM	USB0_DM	—	—	—	—	—	—	—	—
21	VREG_OUT	P	VREG_OUT	VREG_OUT	—	—	—	—	—	—	—	—
22	VREG_IN0	P	VREG_IN0	VREG_IN0	—	—	—	—	—	—	—	—
23	VREG_IN1	P	DISABLED	VREG_IN1	—	—	—	—	—	—	—	—
24	USB1_VSS	P	DISABLED	USB1_VSS	—	—	—	—	—	—	—	—
25	USB1_DP	I/O	DISABLED	USB1_DP	—	—	—	—	—	—	—	—
26	USB1_DM	I/O	DISABLED	USB1_DM	—	—	—	—	—	—	—	—
27	USB1_VBUS	I/O	DISABLED	USB1_VBUS	—	—	—	—	—	—	—	—
28	ADC0_DM0/ADC1_DM3	A	ADC0_DM0/ADC1_DM3	ADC0_DM0/ADC1_DM3	—	—	—	—	—	—	—	—
29	ADC1_DP0/ADC0_DP3	A	ADC1_DP0/ADC0_DP3	ADC1_DP0/ADC0_DP3	—	—	—	—	—	—	—	—
30	ADC1_DM0/ADC0_DM3	A	ADC1_DM0/ADC0_DM3	ADC1_DM0/ADC0_DM3	—	—	—	—	—	—	—	—
31	VDDA	P	VDDA	VDDA	—	—	—	—	—	—	—	—
32	VREFH	P	VREFH	VREFH	—	—	—	—	—	—	—	—
33	VREFL	P	VREFL	VREFL	—	—	—	—	—	—	—	—
34	VSSA	P	VSSA	VSSA	—	—	—	—	—	—	—	—
35	ADC1_SE16/CMP2_IN2/ADC0_SE22	A	ADC1_SE16/CMP2_IN2/ADC0_SE22	ADC1_SE16/CMP2_IN2/ADC0_SE22	—	—	—	—	—	—	—	—
36	ADC0_SE16/CMP1_IN2/ADC0_SE21	A	ADC0_SE16/CMP1_IN2/ADC0_SE21	ADC0_SE16/CMP1_IN2/ADC0_SE21	—	—	—	—	—	—	—	—
37	VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18	A	VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18	VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18	—	—	—	—	—	—	—	—
38	DAC0_OUT/CMP1_IN3/ADC0_SE23	A	DAC0_OUT/CMP1_IN3/ADC0_SE23	DAC0_OUT/CMP1_IN3/ADC0_SE23	—	—	—	—	—	—	—	—
39	DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23	A	DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23	DAC1_OUT/CMP0_IN4/CMP2_IN3/ADC1_SE23	—	—	—	—	—	—	—	—
40	XTAL32	I	XTAL32	XTAL32	—	—	—	—	—	—	—	—
41	EXTAL32	O	EXTAL32	EXTAL32	—	—	—	—	—	—	—	—
42	VBAT	P	VBAT	VBAT	—	—	—	—	—	—	—	—
43	VDD	P	VDD	VDD	—	—	—	—	—	—	—	—
44	VSS	P	VSS	VSS	—	—	—	—	—	—	—	—
45	PTE24	I/O	ADC0_SE17	ADC0_SE17	PTE24	CAN1_TX	UART4_TX	—	I2C0_SCL	EWM_OUT_b	—	—
46	PTE25/LLWU_P21	I/O	ADC0_SE18	ADC0_SE18	PTE25/LLWU_P21	CAN1_RX	UART4_RX	—	I2C0_SDA	EWM_IN	—	—
47	PTE26	I/O	DISABLED	—	PTE26	ENET_1588_CLKIN	UART4_CTS_b	—	—	RTC_CLKOUT	USB0_CLKIN	—
48	PTE27	I/O	DISABLED	—	PTE27	—	UART4_RTS_b	—	—	—	—	—
49	PTE28	I/O	DISABLED	—	PTE28	—	—	—	—	—	—	—
50	PTA0	I/O	JTAG_TCLK/SWD_CLK/EZP_CLK	TSI0_CH1	PTA0	UART0_CTS_b/UART0_COL_b	FTM0_CH5	—	LPUART0_CTS_b	—	JTAG_TCLK/SWD_CLK	EZP_CLK
51	PTA1	I/O	JTAG_TDI/EZP_DI	TSI0_CH2	PTA1	UART0_RX	FTM0_CH6	I2C3_SDA	LPUART0_RX	—	JTAG_TDI	EZP_DI
52	PTA2	I/O	JTAG_TDO/TRACE_SWO/EZP_DO	TSI0_CH3	PTA2	UART0_TX	FTM0_CH7	I2C3_SCL	LPUART0_TX	—	JTAG_TDO/TRACE_SWO	EZP_DO
53	PTA3	I/O	JTAG_TMS/SWD_DIO	TSI0_CH4	PTA3	UART0_RTS_b	FTM0_CH0	—	LPUART0_RTS_b	—	JTAG_TMS/SWD_DIO	—
54	PTA4/LLWU_P3	I/O	NMI_b/EZP_CS_b	TSI0_CH5	PTA4/LLWU_P3	—	FTM0_CH1	—	—	—	NMI_b	EZP_CS_b
55	PTA5	I/O	DISABLED	—	PTA5	USB0_CLKIN	FTM0_CH2	RMII0_RXER/MII0_RXER	CMP2_OUT	I2S0_TX_BCLK	JTAG_TRST_b	—
56	VDD	P	VDD	VDD	—	—	—	—	—	—	—	—
57	VSS	P	VSS	VSS	—	—	—	—	—	—	—	—
58	PTA6	I/O	DISABLED	—	PTA6	—	FTM0_CH3	—	CLKOUT	—	TRACE_CLKOUT	—
59	PTA7	I/O	ADC0_SE10	ADC0_SE10	PTA7	—	FTM0_CH4	—	RMII0_MDIO/MII0_MDIO	—	TRACE_D3	—
60	PTA8	I/O	ADC0_SE11	ADC0_SE11	PTA8	—	FTM1_CH0	—	RMII0_MDC/MII0_MDC	FTM1_QD_PHA/TPM1_CH0	TRACE_D2	—
61	PTA9	I/O	DISABLED	—	PTA9	—	FTM1_CH1	MII0_RXD3	—	FTM1_QD_PHB/TPM1_CH1	TRACE_D1	—
62	PTA10/LLWU_P22	I/O	DISABLED	—	PTA10/LLWU_P22	—	FTM2_CH0	MII0_RXD2	—	FTM2_QD_PHA/TPM2_CH0	TRACE_D0	—
63	PTA11/LLWU_P23	I/O	DISABLED	—	PTA11/LLWU_P23	—	FTM2_CH1	MII0_RXCLK	I2C2_SDA	FTM2_QD_PHB/TPM2_CH1	—	—
64	PTA12	I/O	CMP2_IN0	CMP2_IN0	PTA12	CAN0_TX	FTM1_CH0	RMII0_RXD1/MII0_RXD1	I2C2_SCL	I2S0_TXD0	FTM1_QD_PHA/TPM1_CH0	—
65	PTA13/LLWU_P4	I/O	CMP2_IN1	CMP2_IN1	PTA13/LLWU_P4	CAN0_RX	FTM1_CH1	RMII0_RXD0/MII0_RXD0	I2C2_SDA	I2S0_TX_FS	FTM1_QD_PHB/TPM1_CH1	—
66	PTA14	I/O	DISABLED	—	PTA14	SPI0_PCS0	UART0_TX	RMII0_CRS_DV/MII0_RXDV	I2C2_SCL	I2S0_RX_BCLK	I2S0_TXD1	—
67	PTA15	I/O	CMP3_IN1	CMP3_IN1	PTA15	SPI0_SCK	UART0_RX	RMII0_TXEN/MII0_TXEN	—	I2S0_RXD0	—	—
68	PTA16	I/O	CMP3_IN2	CMP3_IN2	PTA16	SPI0_SOUT	UART0_CTS_b/UART0_COL_b	RMII0_TXD0/MII0_TXD0	—	I2S0_RX_FS	I2S0_RXD1	—
69	PTA17	I/O	ADC1_SE17	ADC1_SE17	PTA17	SPI0_SIN	UART0_RTS_b	RMII0_TXD1/MII0_TXD1	—	I2S0_MCLK	—	—
70	VDD	P	VDD	VDD	—	—	—	—	—	—	—	—
71	VSS	P	VSS	VSS	—	—	—	—	—	—	—	—
72	PTA18	I/O	EXTAL0	EXTAL0	PTA18	—	FTM0_FLT2	FTM_CLKIN0	—	—	TPM_CLKIN0	—
73	PTA19	I/O	XTAL0	XTAL0	PTA19	—	FTM1_FLT0	FTM_CLKIN1	LPTMR0_ALT1	—	TPM_CLKIN1	—
74	RESET_b	I	RESET_b	RESET_b	—	—	—	—	—	—	—	—
75	PTA24	I/O	CMP3_IN4	CMP3_IN4	PTA24	—	—	MII0_TXD2	—	—	FB_A29	—
76	PTA25	I/O	CMP3_IN5	CMP3_IN5	PTA25	—	—	MII0_TXCLK	—	—	FB_A28	—
77	PTA26	I/O	DISABLED	—	PTA26	—	—	MII0_TXD3	—	—	FB_A27	—
78	PTA27	I/O	DISABLED	—	PTA27	—	—	MII0_CRS	—	—	FB_A26	—
79	PTA28	I/O	DISABLED	—	PTA28	—	—	MII0_TXER	—	—	FB_A25	—
80	PTA29	I/O	DISABLED	—	PTA29	—	—	MII0_COL	—	—	FB_A24	—
81	PTB0/LLWU_P5	I/O	ADC0_SE8/ADC1_SE8/TSI0_CH0	ADC0_SE8/ADC1_SE8/TSI0_CH0	PTB0/LLWU_P5	I2C0_SCL	FTM1_CH0	RMII0_MDIO/MII0_MDIO	SDRAM_CAS_b	FTM1_QD_PHA/TPM1_CH0	—	—

Pin	Pin Name	Type	Default	ALT0	ALT1	ALT2	ALT3	ALT4	ALT5	ALT6	ALT7	EzPort
82	PTB1	I/O	ADC0_SE9/ADC1_SE9/TSI0_CH6	ADC0_SE9/ADC1_SE9/TSI0_CH6	PTB1	I2C0_SDA	FTM1_CH1	RMII0_MDC/MII0_MDC	SDRAM_RAS_b	FTM1_QD_PHB/TPM1_CH1	—	—
83	PTB2	I/O	ADC0_SE12/TSI0_CH7	ADC0_SE12/TSI0_CH7	PTB2	UART0_RTS_b	FTM0_FLT3	RMII0_RXER/MII0_RXER	SDRAM_WE_b	—	—	—
84	PTB3	I/O	ADC0_SE13/TSI0_CH8	ADC0_SE13/TSI0_CH8	PTB3	UART0_CTS_b	—	RMII0_RXDV/MII0_RXDV	SDRAM_CS_b	—	—	—
85	PTB4	I/O	ADC1_SE10/TSI0_CH9	ADC1_SE10/TSI0_CH9	PTB4	—	FTM0_FLT0	RMII0_RXD1/MII0_RXD1	SDRAM_CLKOUT	—	—	—
86	PTB5	I/O	ADC1_SE11/TSI0_CH10	ADC1_SE11/TSI0_CH10	PTB5	—	FTM0_FLT1	RMII0_RXD0/MII0_RXD0	SDRAM_DQM3	—	—	—
87	PTB6	I/O	DISABLED	—	PTB6	—	FTM0_FLT2	RMII0_TXEN/MII0_TXEN	SDRAM_DQM2	—	—	—
88	PTB7	I/O	DISABLED	—	PTB7	—	FTM0_CH6	RMII0_TXD0/MII0_TXD0	SDRAM_DQM1	—	—	—
89	PTB8	I/O	DISABLED	—	PTB8	—	FTM0_CH7	RMII0_TXD1/MII0_TXD1	SDRAM_DQM0	—	—	—
90	PTB9	I/O	DISABLED	—	PTB9	—	FTM0_CH5	RMII0_MDIO/MII0_MDIO	SDRAM_A10	—	—	—
91	PTB10	I/O	DISABLED	—	PTB10	—	FTM0_CH4	RMII0_MDC/MII0_MDC	SDRAM_A9	—	—	—
92	PTB11	I/O	DISABLED	—	PTB11	—	FTM0_CH3	RMII0_RXER/MII0_RXER	SDRAM_A8	—	—	—
93	PTB16	I/O	DISABLED	—	PTB16	CAN1_TX	UART0_RX	RMII0_TXER/MII0_TXER	SDRAM_A7	—	—	—
94	PTB17	I/O	DISABLED	—	PTB17	CAN1_RX	UART0_TX	RMII0_TXEN/MII0_TXEN	SDRAM_A6	—	—	—
95	PTB18	I/O	DISABLED	—	PTB18	—	UART0_RTS_b	RMII0_TXD0/MII0_TXD0	SDRAM_A5	—	—	—
96	PTB19	I/O	DISABLED	—	PTB19	—	UART0_CTS_b	RMII0_TXD1/MII0_TXD1	SDRAM_A4	—	—	—
97	PTB20	I/O	DISABLED	—	PTB20	—	UART0_RX	RMII0_RXD1/MII0_RXD1	SDRAM_A3	—	—	—
98	PTB21	I/O	DISABLED	—	PTB21	—	UART0_TX	RMII0_RXD0/MII0_RXD0	SDRAM_A2	—	—	—
99	PTB22	I/O	DISABLED	—	PTB22	—	—	RMII0_RXDV/MII0_RXDV	SDRAM_A1	—	—	—
100	PTB23	I/O	DISABLED	—	PTB23	—	—	RMII0_RXER/MII0_RXER	SDRAM_A0	—	—	—
101	VDD	P	VDD	VDD	—	—	—	—	—	—	—	—
102	VSS	P	VSS	VSS	—	—	—	—	—	—	—	—
103	PTC0	I/O	DISABLED	—	PTC0	SPI0_PCS4	UART1_TX	RMII0_MDIO/MII0_MDIO	SDRAM_D23	—	—	—
104	PTC1	I/O	DISABLED	—	PTC1	SPI0_SOUT	UART1_RX	RMII0_MDC/MII0_MDC	SDRAM_D22	—	—	—
105	PTC2	I/O	ADC0_SE4b	ADC0_SE4b	PTC2	SPI0_SCK	UART1_CTS_b	RMII0_RXER/MII0_RXER	SDRAM_D21	—	—	—
106	PTC3	I/O	ADC0_SE5b	ADC0_SE5b	PTC3	SPI0_SIN	UART1_RTS_b	RMII0_RXDV/MII0_RXDV	SDRAM_D20	—	—	—
107	PTC4	I/O	ADC1_SE4b	ADC1_SE4b	PTC4	SPI0_PCS0	UART1_TX	RMII0_RXD1/MII0_RXD1	SDRAM_D19	—	—	—
108	PTC5	I/O	ADC1_SE5b	ADC1_SE5b	PTC5	SPI0_PCS1	UART1_RX	RMII0_RXD0/MII0_RXD0	SDRAM_D18	—	—	—
109	PTC6	I/O	DISABLED	—	PTC6	SPI0_PCS2	UART1_CTS_b	RMII0_TXEN/MII0_TXEN	SDRAM_D17	—	—	—
110	PTC7	I/O	DISABLED	—	PTC7	SPI0_PCS3	UART1_RTS_b	RMII0_TXD0/MII0_TXD0	SDRAM_D16	—	—	—
111	PTC8	I/O	ADC1_SE4a	ADC1_SE4a	PTC8	I2C0_SCL	UART4_TX	RMII0_TXD1/MII0_TXD1	SDRAM_D15	—	—	—
112	PTC9	I/O	ADC1_SE5a	ADC1_SE5a	PTC9	I2C0_SDA	UART4_RX	RMII0_MDIO/MII0_MDIO	SDRAM_D14	—	—	—
113	PTC10	I/O	ADC1_SE6a	ADC1_SE6a	PTC10	I2C1_SCL	UART4_CTS_b	RMII0_MDC/MII0_MDC

Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure.

Figure 2. Input signal measurement reference

All digital I/O switching characteristics assume:

1. output pins

• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength

Symbol	Description	Min.	Max.	Unit	Notes
T STG	Storage temperature	-55	150	°C	1
T SDR	Solder temperature, lead-free	-	260	°C	2

Package dimensions are provided in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the drawing's document number:

If you want the drawing for this package	Then use this document number
144-pin LQFP	98ASS23177W
144-pin MAPBGA	98ASA00222D

Part Number	Flash Memory	SRAM Memory	Maximum number of I/O's
MK66FN2M0VMD18	2 MB	256 KB	100
MK66FX1M0VMD18	1.25 MB	256 KB	100
MK66FN2M0VLQ18	2 MB	256 KB	100
MK66FX1M0VLQ18	1.25 MB	256 KB	100