LP384

Part: iCE40™ LP/HX Family — Lattice Semiconductor Corp.

Type: Field-Programmable Gate Array (FPGA)

Description: Ultra-low power, non-volatile FPGAs with 384 to 7,680 LUTs, up to 128 kbits sysMEM Embedded Block RAM, and advanced 40 nm low power process.

Operating Conditions:

• Standby power: As low as 21 μA

Absolute Maximum Ratings:

Key Specs:

• Logic Cells (LUT + Flip-Flop): 384 to 7,680
• sysMEM Embedded Block RAM: Up to 128 kbits
• Process technology: 40 nm low power CMOS
• Standby power: As low as 21 μA
• Maximum Programmable I/O Pins: 10 to 206
• Phase-Locked Loops (PLLs): Up to two per device
• Logic Cells per PLB: 8
• LUTs per Logic Cell: One four-input Look-Up Table (LUT4)

Features:

• Flexible Logic Architecture with 384 to 7,680 LUT4s and 10 to 206 I/Os
• Ultra Low Power Devices with advanced 40 nm low power process and as low as 21 μA standby power
• Embedded and Distributed Memory with up to 128 kbits sysMEM™ Embedded Block RAM
• Pre-Engineered Source Synchronous I/O with DDR registers in I/O cells
• High Current LED Drivers for three different LEDs or one RGB LED
• High Performance, Flexible I/O Buffer supporting LVCMOS 3.3/2.5/1.8, LVDS25E, subLVDS
• Schmitt trigger inputs, to 200 mV typical hysteresis
• Programmable pull-up mode
• Flexible On-Chip Clocking with eight low-skew global clock resources and up to two analog PLLs
• Flexible Device Configuration via Standard SPI Interface or Internal Nonvolatile Configuration Memory (NVCM)
• Broad Range of Package Options including WLCSP, QFN, VQFP, TQFP, ucBGA, caBGA, and csBGA

Applications:

• Low-cost, high-volume consumer and system applications

Package:

• 16 WLCSP (1.40 mm x 1.48 mm, 0.35 mm)
• 32 QFN (5 mmx 5 mm, 0.5 mm)
• 36 ucBGA (2.5 mmx 2.5 mm, 0.4 mm)
• 49 ucBGA (3 mmx 3 mm, 0.4 mm)
• 81 ucBGA (4 mmx 4 mm, 0.4 mm)
• 81 csBGA (5 mmx 5 mm, 0.5 mm)
• 84 QFN (7 mmx 7 mm, 0.5 mm)
• 100 VQFP (14 mmx 14 mm, 0.5 mm)
• 121 ucBGA (5 mmx 5 mm, 0.4 mm)
• 121 csBGA (6 mmx 6 mm, 0.5 mm)
• 121 caBGA (9 mmx 9 mm, 0.8 mm)
• 132 csBGA (8 mmx 8 mm, 0.5 mm)
• 144 TQFP (20 mmx 20 mm, 0.5 mm)
• 225 ucBGA (7 mmx 7 mm, 0.4 mm)
• 256-ball caBGA (14 mmx 14 mm, 0.8 mm)

•  Flexible Logic Architecture
• Five devices with 384 to 7,680 LUT4s and 10 to 206 I/Os
•  Ultra Low Power Devices
• Advanced 40 nm low power process
• As low as 21 μA standby power
• Programmable low swing differential I/Os
•  Embedded and Distributed Memory
• Up to 128 kbits sysMEM™ Embedded Block RAM
•  Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
•  High Current LED Drivers
• Three High Current Drivers used for three different LEDs or one RGB LED
•  High Performance, Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide range of interfaces:
• LVCMOS 3.3/2.5/1.8
• LVDS25E, subLVDS

Table 1-1. iCE40 Family Selection Guide

• Input/ Output V IL V IL V IH 1 V IH 1 V OL Max. (V) V OH Min. (V)
• Standard Min. (V) Max. (V) Min. (V) Max. (V) I OL Max. (mA) I OH Max. (mA)
• LVCMOS 3.3 -0.3 0.8 2.0 V CCIO + 0.2 V 0.4 V CCIO - 0.4 8, 16 2 , 24 2 -8, -16 2 , -24 2
• LVCMOS 3.3 -0.3 0.8 2.0 V CCIO + 0.2 V 0.2 V CCIO - 0.2 0.1 -0.1
• LVCMOS 2.5 -0.3 0.7 1.7 V CCIO + 0.2 V 0.4 V CCIO - 0.4 6, 12 2 , 18 2 -6, -12 2 , -18 2
• LVCMOS 2.5 -0.3 0.7 1.7 V CCIO + 0.2 V 0.2 V CCIO - 0.2 0.1 -0.1
• LVCMOS 1.8 -0.3 0.35V CCIO 0.65V CCIO V CCIO + 0.2 V 0.4 V CCIO - 0.4 4, 8 2 , 12 2 -4, -8 2 , -12 2
• LVCMOS 1.8 -0.3 0.35V CCIO 0.65V CCIO V CCIO + 0.2 V 0.2 V CCIO - 0.2 0.1 -0.1

1. No PLL available on the iCE40LP384 and iCE40LP640 device.

2. VCCPLL is tied to V CC internally in packages without PLLs pins.