LMX2571NJKT

The LMX2571NJKT is an electronic component from Texas Instruments. View the full LMX2571NJKT datasheet below including key specifications, electrical characteristics, absolute maximum ratings.

Manufacturer

Texas Instruments

Key Specifications

Parameter	Value
Differential - Input:Output	Yes/No
DigiKey Programmable	Not Verified
Divider/Multiplier	Yes/Yes
Frequency - Max	1.4GHz
Input	Clock, Crystal
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature	-40°C ~ 85°C
Output	Clock
Package / Case	36-WFQFN Exposed Pad
PLL	Yes with Bypass
Ratio - Input:Output	2:2
Supplier Device Package	36-WQFN (6x6)
Type	Frequency Synthesizer (RF)
Supply Voltage	3.15V ~ 3.45V

Overview

The LMX2571 is a low-power, high-performance, wideband PLLatinum™ RF synthesizer that integrates a delta-sigma fractional N PLL, multiple core voltage-controlled oscillator (VCO), programmable output dividers and two output buffers. The VCO cores work up to 5.376 GHz resulting in continuous output frequency range of 10 MHz to 1344 MHz.

This synthesizer can also be used with an external VCO. To that end, a dedicated 5-V charge pump and an output divider are available for this configuration.

A unique programmable multiplier is also incorporated to help improve spurs, allowing the system to use every channel even if it falls on an integer boundary.

The output has an integrated SPDT switch that can be used as a transmit/receive switch in FDD radio application. Both outputs can also be turned on to provide 2 outputs at the same time.

The LMX2571 supports direct digital FSK modulation through programming or pins. Discrete level FSK, pulse shaping FSK, and analog FM modulation are supported.

A new FastLock technique can be used allowing the user to step from one frequency to the next in less then 1.5 ms even when an external VCO is used with a narrow band loop filter.

Features

1 · Any Frequency from 10 MHz to 1344 MHz
Low Phase Noise and Spurs
--123 dBc/Hz at 12.5 kHz Offset @ 480 MHz
--145 dBc/Hz at 1 MHz Offset @ 480 MHz
-Normalized PLL Noise Floor of -231 dBc/Hz
-Spurious Better Than -75 dBc/Hz
New FastLock to Reduce Lock Time
A Novel Technique to Remove Integer Boundary Spurs
Integrated 5-V Charge Pump and Output Divider for External VCO Operation
2-, 4- and 8-level or Arbitrary Level Direct Digital FSK Modulation
One TX/RX Output or Two Fanout Outputs
Crystal, XO or Differential Reference Clock Input
Low Current Consumption
-39-mA Typical Synthesizer Mode (Int. VCO)
-9-mA Typical PLL Mode (Ext. VCO)
24-Bit Fractional-N Delta Sigma Modulator

Applications

Duplex Mode Digital Professional 2-Way Radio -dPMR, DMR, PDT, P25 Phase I
Low Power Radio Communication Systems
-Satcom Modem
-Wireless Microphone
-Propriety Wireless Connectivity
Handheld Test and Measurement Equipment

Pin Configuration

Pin Functions

Pin Functions

PIN	PIN	TYPE	DESCRIPTION
NAME	NO.
Bypass1	2	Bypass	Place a 100-nF capacitor to GND.
Bypass2	3	Bypass	Place a 100-nF capacitor to GND.
CE	19	Input	Chip Enable input. Active HIGH powers on the device.
CLK	11	Input	MICROWIRE clock input.
CPout	25	Output	Internal VCO charge pump access point to connect to a 2 nd order loop filter.
CPoutExt	30	Output	5-V charge pump output used in PLL mode (external VCO).
DAP	0	GND	The DAP should be grounded.
DATA	12	Input	MICROWIRE serial data input.
Fin	24	Input	High frequency AC coupled input pin for an external VCO. Leave it open or AC coupled to GND if not being used.
FSK_D0	7	Input	FSK data bit 0 (FSK PIN mode) / I2S FS input (FSK I2S mode).
FSK_D1	6	Input	FSK data bit 1 (FSK PIN mode) / I2S DATA input (FSK I2S mode).
FSK_D2	5	Input	FSK data bit 2 (FSK PIN mode).
FSK_DV	4	Input	FSK data valid input (FSK PIN mode) / I2S CLK input (FSK I2S mode).
FLout1	29	Output	FastLock output control 1 for external switch. Output is HIGH when F1 is selected.
FLout2	28	Output	FastLock output control 2 for external switch. Output is HIGH when F2 is selected.
GND	23	GND	VCO ground.
GND	31	GND	Charge pump ground.
GND	35	GND	OSCin ground.
LE	13	Input	MICROWIRE latch enable input.
MUXout	10	Output	Multiplexed output that can be assigned to lock detect or readback serial data output.
NC	8,14, 26	NC	Do not connect these pins.
OSCin	34	Input	Reference clock input.
OSCin*	36	Input	Complementary reference clock input.
RFoutRx	16	Output	RF output used to drive receive mixer. Selectable open drain or push-pull output.
RFoutTx	17	Output	RF output used to drive transmit signal. Selectable open drain or push-pull output.
TrCtl	18	Input	Transmit/Receive control. This pin controls the RF output port and the output frequency selection.

Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, VIO = VCC, -40 °C ≤ TA ≤ 85 °C, except as specified. Typical values are at VCC = VIO = 3.3 V, VCP = 3.3 V or 5 V in synthesizer mode, VCP = 5 V in PLL mode, TA = 25 °C.

PARAMETER	PARAMETER	TEST CONDITIONS	TEST CONDITIONS	MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION	CURRENT CONSUMPTION
I CC	Total current in synthesizer mode (internal VCO)		Configuration A (1)		39		mA
I CC	Total current in synthesizer mode (internal VCO)		Configuration B (2)		44		mA
I CC	Total current in synthesizer mode (internal VCO)	Configuration C (3)	Configuration C (3)		46		mA
I CC	Total current in synthesizer mode (internal VCO)	f OUT = 480 MHz Configuration D (4) SE OSCin	f OUT = 480 MHz Configuration D (4) SE OSCin		51		mA
I PLL	Total current in PLL mode (external VCO)		Configuration E (5)		9		mA
I PLL	Total current in PLL mode (external VCO)	Configuration F (6)	Configuration F (6)		15		mA
I PLL	Total current in PLL mode (external VCO)	Configuration G (7)	Configuration G (7)		21		mA
I CC PD	Power down current	CE = 0V or POWERDOWN bit = 1 V = 3.3 V, Push-pull output	CE = 0V or POWERDOWN bit = 1 V = 3.3 V, Push-pull output		0.9		mA
OSCIN REFERENCE INPUT	OSCIN REFERENCE INPUT	OSCIN REFERENCE INPUT	OSCIN REFERENCE INPUT	OSCIN REFERENCE INPUT	OSCIN REFERENCE INPUT	OSCIN REFERENCE INPUT	OSCIN REFERENCE INPUT
f OSCin	OSCin frequency range	Single-ended or differential input	Single-ended or differential input	10		150	MHz
V OSCin	OSCin input voltage (8)	Single-ended input	Single-ended input	1.4		3.3	V
V OSCin	OSCin input voltage (8)	Differential input	Differential input	0.15		1.5	V
CRYSTAL REFERENCE INPUT	CRYSTAL REFERENCE INPUT	CRYSTAL REFERENCE INPUT	CRYSTAL REFERENCE INPUT	CRYSTAL REFERENCE INPUT	CRYSTAL REFERENCE INPUT	CRYSTAL REFERENCE INPUT	CRYSTAL REFERENCE INPUT
f XTAL	Crystal frequency range	Fundamental model, ESR < 200 Ω	Fundamental model, ESR < 200 Ω	10		40	MHz
C IN	OSCin input capacitance				1		pF
MULT	MULT	MULT	MULT	MULT	MULT	MULT	MULT
f MULTin	MULT input frequency	MULT > Pre-divider	MULT > Pre-divider	10		30	MHz
f MULTout	MULT output frequency	Not supported with crystal reference input	Not supported with crystal reference input	60		130	MHz
PLL	PLL	PLL	PLL	PLL	PLL	PLL	PLL
f	Phase detector frequency	PD	PD			130	MHz
K PD	Charge pump current (9)	Programmable minimum value	Internal charge pump	312.5			μA
K PD	Charge pump current (9)	Programmable minimum value	5-V charge pump	625			μA
K PD	Charge pump current (9)	Per programmable step	Internal charge pump	312.5			μA
K PD	Charge pump current (9)	Per programmable step	5-V charge pump	625			μA
K PD	Charge pump current (9)	Programmable maximum value	Internal charge pump	7187.5			μA
K PD	Charge pump current (9)	Programmable maximum value	5-V charge pump	6875			μA

Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted) (1)

		MIN	MAX	UNIT
V CC	Power supply voltage	-0.3	3.6	V
V IO	IO supply voltage	-0.3	3.6	V
V IN	IO input voltage		V CC + 0.3	V
V CP	Charge pump supply voltage		5.25	V
T J	Junction temperature		150	°C
T STG	Storage temperature	-65	150	°C

Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V CC	Power supply voltage	3.15	3.45	V
V IO	IO supply voltage		V CC	V
V CP	Charge pump supply voltage		5	V
		V CC	5	V
T A	Ambient temperature	-40	85	°C
T J	Junction Temperature		125	°C

Thermal Information

THERMAL METRIC (1)		LMX2571 WQFN (NJK)	UNIT
		36 PINS
R θ JA	Junction-to-ambient thermal resistance	32.9	°C/W
R θ JC(top)	Junction-to-case (top) thermal resistance	14.5	°C/W
R θ JB	Junction-to-board thermal resistance	6.3	°C/W
ψ JT	Junction-to-top characterization parameter	0.2	°C/W
ψ JB	Junction-to-board characterization parameter	6.3	°C/W
R θ JC(bot)	Junction-to-case (bottom) thermal resistance	2.0	°C/W

Typical Application

Use Equation 4 and Equation 6 to calculate the required FSK steps. For +10 kHz frequency deviation, the FSK step value is equal to [10000 * 16777216 / (104 * 10 6 )] * (5 * 1 / 2) = 4033. For -10 kHz frequency deviation, the FSK step value is equal to 2's complement of 4033 = 61502. Similarly, the FSK step values for ±30 kHz frequency deviation are 12099 and 53436.

All the required configuration values for F2, 928 MHz can be calculated in the similar fashion and are summarized as follows:

Table 40. Frequency Plan Summary

CONFIGURATION PARAMETER	F1 (902 MHz)	F2 (928 MHz)
Pre-divider	1	1
MULT	4	4
Post-divider	1	1
PDF	104 MHz	104 MHz
VCO	4510 MHz	4640 MHz
N-divider	21.68269231	22.30769231
N integer	21	22
DEN	0	0
NUM	11453676	5162220
CHDIV1	5	5
CHDIV2	1	1
FSK_DEV0	4033
FSK_DEV1	12099
FSK_DEV2	61502
FSK_DEV3	53436

Table 41. Register Settings Summary

CONFIGURATION PARAMETERS	REGISTER BIT	COMMON SETTING	F1 SPECIFIC SETTING	F2 SPECIFIC SETTING
VCO calibration	FCAL_EN	1 = Enabled
Lock detect	SDO_LE_SEL	1 = Lock detect output
Lock detect	LD_EN	1 = Enabled
OSCin buffer type	IPBUF_SE_DIFF_SEL	0 = SE input buffer
Dithering	DITHERING	0 = Disabled
Charge pump gain	CP_GAIN	1 = 1x
Base charge pump current	CP_IUP	8 = 1250 μA
Base charge pump current	CP_IDN	8 = 1250 μA
MULT settling time	MULT_WAIT	520 = 20 μs
Output buffer type	OUTBUF_RX_TYPE	1 = Push pull
Output buffer type	OUTBUF_TX_TYPE	1 = Push pull
Output buffer auto mute	OUTBUF_AUTOMUTE	0 = Disabled
TrCtl pin polarity	RXTX_POL	0 = Active LOW = TX
TX RX switching mode	RXTX_CTRL	1 = TrCtl pin control
Enable F1 F2 initialization	F1F2_MODE	1 = Enabled
F1 F2 switching mode	F1F2_CTRL	1 = Control by TrCtl pin
Pre-divider	PLL_R_PRE_F1		1
Pre-divider	PLL_R_PRE_F2			1
MULT multiplier	MULT_F1		4
MULT multiplier	MULT_F2			4

Table 41. Register Settings Summary

Table 41. Register Settings Summary (continued)

CONFIGURATION PARAMETERS	REGISTER BIT	COMMON SETTING	F1 SPECIFIC SETTING	F2 SPECIFIC SETTING
Post-divider	PLL_R_F1 PLL_R_F2		1	1
ΔΣ modulator order	FRAC_ORDER_F1 FRAC_ORDER_F2		3 = 3 rd order	3 = 3 rd order
PFD delay	PFD_DELAY_F1 PFD_DELAY_F2		5 = 8 clock cycles	5 = 8 clock cycles
CHDIV1 divider	CHDIV1_F1 CHDIV1_F2		1 = Divide by 5	1 = Divide by 5
CHDIV2 divider	CHDIV2_F1 CHDIV2_F2		0 = Divide by 1	0 = Divide by 1
Internal 3 rd pole loop filter	LF_R3_F1 LF_R3_F2		4 = 800 Ω	4 = 800 Ω
Internal 4 th pole loop filter	LF_R4_F1 LF_R4_F2		4 = 800 Ω	4 = 800 Ω
Output port selection	OUTBUF_TX_EN_F1 OUTBUF_RX_EN_F2		1 = TX port enabled	1 = RX port enabled
Output power control	OUTBUF_TX_PWR_F1 OUTBUF_RX_PWR_F2		6	6
FSK mode	FSK_MODE_SEL1 FSK_MODE_SEL0	00 = FSK PIN mode
FSK level	FSK_LEVEL	2 = 4FSK
Enable FSK modulation	FSK_EN_F1		1 = Enabled
FSK deviation at 00	FSK_DEV0_F1		4033 = +10 kHz
FSK deviation at 01	FSK_DEV1_F1		12099 = +30 kHz
FSK deviation at 10	FSK_DEV2_F1		61502 = -10 kHz
FSK deviation at 11	FSK_DEV3_F1		53436 = -30 kHz
Fractional denominator	PLL_DEN_F1[23:16] PLL_DEN_F1[15:0] PLL_DEN_F2[23:16] PLL_DEN_F2[15:0]		0 0	0 0
Fractional numerator	PLL_NUM_F1[23:16] PLL_NUM_F1[15:0] PLL_NUM_F2[23:16] PLL_NUM_F2[15:0]		174 50412	78 50412
N integer	PLL_N_F1 PLL_N_F2		21	22
Prescaler	PLL_N_PRE_F1 PLL_N_PRE_F2		0 = Divide by 2	0 = Divide by 2

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
LMX2571	Texas Instruments	—
LMX2571NJKR	Texas Instruments	36-WFQFN Exposed Pad

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