KSZ8081RNBIC
Physical Layer TransceiverThe KSZ8081RNBIC is a physical layer transceiver from Microchip Technology. View the full KSZ8081RNBIC datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
Microchip Technology
Category
Physical Layer Transceiver
Package
32-Pin QFN
Overview
Part: KSZ8081MNX/KSZ8081RNB — Micrel Inc.
Type: 10Base-T/100Base-TX Ethernet Physical Layer Transceiver
Description: Single-supply 10Base-T/100Base-TX Ethernet physical-layer transceiver with MII/RMII interface support, integrated 1.2V core regulator, and LinkMD TDR-based cable diagnostics.
Operating Conditions:
- Supply voltage: Single 3.3V (VDD I/O options for 1.8V, 2.5V, or 3.3V)
- Operating temperature: 0°C to 70°C (Commercial), -40°C to 85°C (Industrial)
- Reference clock: 25MHz crystal input
Features:
- Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
- MII interface support (KSZ8081MNX)
- RMII v1.2 Interface support with a 50MHz reference clock output to MAC, and an option to input a 50MHz reference clock (KSZ8081RNB)
- Back-to-back mode support for a 100Mbps copper repeater
- MDC/MDIO management interface for PHY register configuration
- Programmable interrupt output
- LED outputs for link, activity, and speed status indication
- On-chip termination resistors for the differential pairs
- Baseline wander correction
- HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option
- Auto-negotiation to automatically select the highest linkup speed (10/100Mbps) and duplex (half/full)
- Power-down and power-saving modes
- LinkMD TDR-based cable diagnostics to identify faulty copper cabling
- Parametric NAND Tree support for fault detection between chip I/Os and the board
- Loopback modes for diagnostics
- Built-in 1.2V regulator for core
Applications:
- Game console
- IP phone
- IP set-top box
- IP TV
- LOM
- Printer
Package:
- 32-pin (5mm x 5mm) QFN
Features
- Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
- MII interface support (KSZ8081MNX)
- RMII v1.2 Interface support with a 50MHz reference clock output to MAC, and an option to input a 50MHz reference clock (KSZ8081RNB)
- Back-to-back mode support for a 100Mbps copper repeater
- MDC/MDIO management interface for PHY register configuration
- Programmable interrupt output
- LED outputs for link, activity, and speed status indication
- On-chip termination resistors for the differential pairs
- Baseline wander correction
- HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option
- Auto-negotiation to automatically select the highest linkup speed (10/100Mbps) and duplex (half/full)
- Power-down and power-saving modes
- LinkMD TDR-based cable diagnostics to identify faulty copper cabling
- Parametric NAND Tree support for fault detection between chip I/Os and the board
Applications
- Game console
- IP phone
- IP set-top box
- IP TV
- LOM
- Printer
Pin Configuration
32-Pin (5mm x 5mm) QFN
Electrical Characteristics
| Symbol | Parameter | Condition | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|---|
| Supply Current (V DDIO , V DDA_3.3 = 3.3V) (4) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (4) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (4) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (4) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (4) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (4) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (4) |
| I DD1_3.3V | 10Base-T | Full-duplex traffic @100% utilization | 41 | mA | ||
| I DD2_3.3V | 100Base-TX | Full-duplex traffic @100% utilization | 47 | mA | ||
| I DD3_3.3V | EDPD Mode | Ethernet cable disconnected (reg. 18h.11 = 0) | 20 | mA | ||
| I DD4_3.3V | Power-Down Mode | Software power-down (reg. 0h.11 = 1) | 4 | mA | ||
| CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs |
| V IH | Input High Voltage | V DDIO = 3.3V | 2.0 | V | ||
| V IH | Input High Voltage | V DDIO = 2.5V | 1.8 | V | ||
| V IH | Input High Voltage | V DDIO = 1.8V | 1.3 | V | ||
| V IL | Input Low Voltage | V DDIO = 3.3V | 0.8 | V | ||
| V IL | Input Low Voltage | V DDIO = 2.5V | 0.7 | V | ||
| V IL | Input Low Voltage | V DDIO = 1.8V | 0.5 | V | ||
| \ | I IN \ | Input Current | V IN = GND ~ VDDIO | |||
| CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs |
| V OH | Output High Voltage | V DDIO = 3.3V | 2.4 | V | ||
| V OH | Output High Voltage | V DDIO = 2.5V | 2.0 | V | ||
| V OH | Output High Voltage | V DDIO = 1.8V | 1.5 | V | ||
| V OL | Output Low Voltage | V DDIO = 3.3V | 0.4 | V | ||
| V OL | Output Low Voltage | V DDIO = 2.5V | 0.4 | V | ||
| V OL | Output Low Voltage | V DDIO = 1.8V | 0.3 | V | ||
| \ | I oz \ | Output Tri-State Leakage | ||||
| LED Output | LED Output | LED Output | LED Output | LED Output | LED Output | LED Output |
| I LED | Output Drive Current | Each LED pin (LED0, LED1) | 8 | mA |
Absolute Maximum Ratings
- (V DD_1.2 ) .................................................. 0.5V to +1.8V
- (V DDIO, V DDA_3.3 ) ....................................... 0.5V to +5.0V
- Input Voltage (all inputs) .............................. 0.5V to +5.0V
- Output Voltage (all outputs) ......................... 0.5V to +5.0V
- Lead Temperature (soldering, 10sec.).......................260°C
- Storage Temperature (T s ) .........................-55°C to +150°C
Package Information
Figure 27. Recommended Land Pattern, 32-Pin (5mm x 5mm) QFN
Table 26. Compatible Single-Port 10/100 Magnetics
Red circles indicate thermal vias. They should be 0.350mm in diameter and be connected to the GND plane for maximum thermal performance.
Green rectangles (with shaded area) indicate solder stencil openings on the exposed pad area. They should be 0.87 x 0.87mm in size, 1.07mm pitch.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| KSZ8081 | Microchip Technology | — |
| KSZ8081MNX | Microchip Technology | — |
| KSZ8081MNX-EVAL | Microchip Technology | 32-Pin QFN |
| KSZ8081MNX/RNB | Microchip Technology | — |
| KSZ8081MNX/RNB28 | Microchip Technology | — |
| KSZ8081MNX32 | Microchip Technology | — |
| KSZ8081MNXCA | Microchip Technology | 32-VFQFN Exposed Pad |
| KSZ8081MNXCC | Microchip Technology | 32-Pin QFN |
| KSZ8081MNXIA | Microchip Technology | 32-Pin QFN |
| KSZ8081MNXIC | Microchip Technology | 32-Pin QFN |
| KSZ8081RNB | Microchip Technology | 32-Pin QFN |
| KSZ8081RNB-EVAL | Microchip Technology | 32-Pin QFN |
| KSZ8081RNB33 | Microchip Technology | — |
| KSZ8081RNBCA | Microchip Technology | 32-Pin QFN |
| KSZ8081RNBCC | Microchip Technology | 32-Pin QFN |
| KSZ8081RNBIA | Microchip Technology | 32-Pin QFN |
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