KSZ8081MNXIA

Part: Microchip KSZ8081

Type: 10BASE-T/100BASE-TX Physical Layer Transceiver

Key Specs:

• Data Rates: 10/100 Mbps
• Supply Voltage: 3.3V (single)
• I/O Voltage Options: 1.8V, 2.5V, 3.3V
• Core Regulator: Built-in 1.2V
• ESD Rating (HBM): 6 kV

Features:

• Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
• MII interface support (KSZ8081MNX)
• RMII v1.2 Interface support with a 50 MHz reference clock output to MAC, and an option to input a 50 MHz reference clock (KSZ8081RNB)
• Back-to-back mode support for a 100 Mbps copper repeater
• MDC/MDIO management interface for PHY register configuration
• Programmable interrupt output
• LED outputs for link, activity, and speed status indication
• On-chip termination resistors for the differential pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option
• Auto-negotiation to automatically select the highest link-up speed (10/100 Mbps) and duplex (half/full)
• Power-down and power-saving modes
• LinkMD TDR-based cable diagnostics to identify faulty copper cabling
• Parametric NAND Tree support for fault detection between chip I/Os and the board
• HBM ESD rating (6 kV)
• Loopback modes for diagnostics
• Single 3.3V power supply with VDD I/O options for 1.8V, 2.5V, or 3.3V
• Built-in 1.2V regulator for core

Applications:

• Game console
• IP phone
• IP set-top box
• IP TV
• LOM
• Printer

Package:

• 32-pin QFN: 5 mm × 5 mm

• Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
• MII interface support (KSZ8081MNX)
• RMII v1.2 Interface support with a 50 MHz reference clock output to MAC, and an option to input a 50 MHz reference clock (KSZ8081RNB)
• Back-to-back mode support for a 100 Mbps copper repeater
• MDC/MDIO management interface for PHY register configuration
• Programmable interrupt output
• LED outputs for link, activity, and speed status indication
• On-chip termination resistors for the differential pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option
• Auto-negotiation to automatically select the highest link-up speed (10/100 Mbps) and duplex (half/full)
• Power-down and power-saving modes
• LinkMD TDR-based cable diagnostics to identify faulty copper cabling
• Parametric NAND Tree support for fault detection between chip I/Os and the board
• HBM ESD rating (6 kV)
• Loopback modes for diagnostics
• Single 3.3V power supply with VDD I/O options for 1.8V, 2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 32-pin (5 mm × 5 mm) QFN package

• Game console
• IP phone
• IP set-top box
• IP TV
• LOM
• Printer

FIGURE 2-1: KSZ8081MNX 32-QFN PIN ASSIGNMENT (TOP VIEW)

TABLE 2-1: PIN DESCRIPTION — KSZ8081MNX

TABLE 2-1: PIN DESCRIPTION — KSZ8081MNX (CONTINUED)

TABLE 2-1: PIN DESCRIPTION — KSZ8081MNX (CONTINUED)

GND = Ground.

I = Input.

O = Output.

I/O = Bi-directional.

Ipu = Input with internal pull-up (see Electrical Characteristics for value).

Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.

Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value).

NC = Pin is not bonded to the die.

• Note 2-2 RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the MAC.
• Note 2-3 RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.

Note 2-4 MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC. TXD[3:0] has no effect on the PHY when TXEN is de-asserted.

2016-2017 Microchip Technology Inc. DS00002202B-page 47

• (VDDIO, VDDA_3.3) –0.5V to +5.0V
• Input Voltage (all inputs) –0.5V to +5.0V
• Output Voltage (all outputs) –0.5V to +5.0V
• Lead Temperature (soldering, 10s) 260°C
• Storage Temperature (TS) –55°C to +150°C

* Exceeding the absolute maximum ratings can damage the device. Stresses greater than the absolute maximum rating can cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.