KSZ8081MNXIA
Physical Layer TransceiverThe KSZ8081MNXIA is a physical layer transceiver from Microchip Technology. View the full KSZ8081MNXIA datasheet below including pinout, electrical characteristics, absolute maximum ratings.
KSZ8081MNXIA shares its datasheet with KSZ8081, whose page lists every part number it covers.
Official KSZ8081MNXIA datasheet (PDF) — the source this page was extracted from.
KSZ8081MNXIA Overview
Part: KSZ8081 — Micrel Inc.
Type: 10Base-T/100Base-TX Ethernet Physical Layer Transceiver
Description: A single-supply 10Base-T/100Base-TX Ethernet physical-layer transceiver for data transmission and reception over standard CAT-5 UTP cable, featuring on-chip termination resistors, an integrated 1.2V regulator, and LinkMD TDR-based cable diagnostics.
Operating Conditions:
- Supply voltage: 3.3V (VDD I/O options for 1.8V, 2.5V, or 3.3V)
- Operating temperature: -40°C to +85°C
- Clock input: 25MHz crystal
Features:
- Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
- MII (KSZ8081MNX) and RMII v1.2 (KSZ8081RNB) interface support
- HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections
- Auto-negotiation to automatically select the highest linkup speed (10/100Mbps) and duplex (half/full)
- LinkMD TDR-based cable diagnostics to identify faulty copper cabling
- Built-in 1.2V regulator for core
Applications:
- Game console
- IP phone
- IP set-top box
- IP TV
- LOM
- Printer
Package:
- 32-pin (5mm × 5mm) QFN package
KSZ8081MNXIA Features
- Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
- MII interface support (KSZ8081MNX)
- RMII v1.2 Interface support with a 50MHz reference clock output to MAC, and an option to input a 50MHz reference clock (KSZ8081RNB)
- Back-to-back mode support for a 100Mbps copper repeater
- MDC/MDIO management interface for PHY register configuration
- Programmable interrupt output
- LED outputs for link, activity, and speed status indication
- On-chip termination resistors for the differential pairs
- Baseline wander correction
- HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option
- Auto-negotiation to automatically select the highest linkup speed (10/100Mbps) and duplex (half/full)
- Power-down and power-saving modes
- LinkMD TDR-based cable diagnostics to identify faulty copper cabling
- Parametric NAND Tree support for fault detection between chip I/Os and the board
- HBM ESD rating (6kV)
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. · 2180 Fortune Drive · San Jose, CA 95131 · USA · tel +1 (408) 944-0800 · fax + 1 (408) 474-1000 · http://www.micrel.com
KSZ8081MNXIA Applications
- Game console
- IP phone
- IP set-top box
- IP TV
- LOM
- Printer
KSZ8081MNXIA Pin Configuration
KSZ8081MNX — 32-Pin QFN Pinout
Note: The requested part number KSZ8081MNXIA does not appear in the provided datasheet section. The table below is extracted from TABLE 2-1: PIN DESCRIPTION - KSZ8081MNX (the closest variant in the source material). If KSZ8081MNXIA has a different pinout, a datasheet specific to that variant is required.
| Pin Number | Pin Name | Buffer Type | Description |
|---|---|---|---|
| 8 | XO | O | Crystal feedback for 25 MHz crystal. NC if oscillator or external clock source is used. |
| 9 | XI | I | Crystal / Oscillator / External Clock Input. 25 MHz ±50 ppm. |
| 10 | REXT | I | Set PHY transmit output current. Connect 6.49 kΩ resistor to ground. |
| 11 | MDIO | Ipu/Opu | Management Interface (MII) Data I/O. Open-drain with weak pull-up; requires external 1.0 kΩ pull-up resistor. |
| 12 | MDC | Ipu | Management Interface (MII) Clock Input. Synchronous to MDIO data pin. |
| 13 | PHYAD0 | Ipu/O | MII Mode: MII Receive Data Output[3]. Config Mode: Latched as PHYADDR[0] at reset de-assertion. |
| 14 | PHYAD1 | Ipd/O | MII Mode: MII Receive Data Output[2]. Config Mode: Latched as PHYADDR[1] at reset de-assertion. |
| 15 | RXD1/PHYAD2 | Ipd/O | MII Mode: MII Receive Data Output[1]. Config Mode: Latched as PHYADDR[2] at reset de-assertion. |
| 16 | RXD0/DUPLEX | Ipu/O | MII Mode: MII Receive Data Output[0]. Config Mode: Latched as DUPLEX at reset de-assertion. |
| 17 | VDDIO | P | 3.3V, 2.5V, or 1.8V digital VDD. |
| 18 | RXDV/CONFIG2 | Ipd/O | MII Mode: MII Receive Data Valid Output. Config Mode: Latched as CONFIG2 at reset de-assertion. |
| 19 | RXC/B-CAST_OFF | Ipd/O | MII Mode: MII Receive Clock Output. Config Mode: Latched as B-CAST_OFF at reset de-assertion. |
| 20 | RXER/ISO | Ipd/O | MII Mode: MII Receive Error Output. Config Mode: Latched as ISOLATE at reset de-assertion. |
| 21 | INTRP/NAND_Tree# | Ipu/Opu | Interrupt Output: Programmable, open-drain with weak pull-up; requires external 1.0 kΩ pull-up resistor. Config Mode: Latched as NAND_Tree# at reset de-assertion. |
| 22 | TXC | Ipd/O | MII Mode: MII Transmit Clock Output. Requires pull-down value latched at reset de-assertion. |
| 23 | TXEN | I | MII Mode: MII Transmit Enable Input. |
| 24 | TXD0 | I | MII Mode: MII Transmit Data Input[0]. |
| 25 | TXD1 | I | MII Mode: MII Transmit Data Input[1]. |
| 26 | TXD2 | I | MII Mode: MII Transmit Data Input[2]. |
| 27 | TXD3 | I | MII Mode: MII Transmit Data Input[3]. |
| 28 | COL/CONFIG0 | Ipd/O | MII Mode: MII Collision Detect Output. Config Mode: Latched as CONFIG0 at reset de-assertion. |
| 29 | CRS/CONFIG1 | Ipd/O | MII Mode: MII Carrier Sense Output. Config Mode: Latched as CONFIG1 at reset de-assertion. |
| 30 | LED0/NWAYEN | Ipu/O | LED Output: Programmable LED0. Config Mode: Latched as auto-negotiation enable at reset de-assertion. Programmable via Register 1Fh bits [5:4]. |
| 31 | LED1/SPEED | Ipu/O | LED Output: Programmable LED1. Config Mode: Latched as Speed at reset de-assertion. Programmable via Register 1Fh bits [5:4]. |
| 32 | RST# | Ipu | Chip Reset (active low). |
| PADDLE | GND | GND | Ground. |
Notes
- Part number mismatch: The datasheet section provided covers KSZ8081MNX, not the requested KSZ8081MNXIA. The pinout above is for KSZ8081MNX; verify that KSZ8081MNXIA has identical pinout before use.
- Dual-function pins: Many pins (PHYAD0–2, DUPLEX, CONFIG0–2, NWAYEN, SPEED, NAND_Tree#, B-CAST_OFF, ISO) serve different functions depending on mode (MII vs. Config) and are latched at reset de-assertion based on pull-up/pull-down state.
- Open-drain pins: MDIO (pin 11) and INTRP (pin 21) are open-drain and require external 1.0 kΩ pull-up resistors.
- REXT (pin 10): Requires external 6.49 kΩ resistor to ground to set transmit output current.
- TXC (pin 22): Requires external pull-down resistor to avoid MAC-side pull-high issues; see Register 16h, Bit [15] for details.
KSZ8081MNXIA Electrical Characteristics
| Symbol | Parameter | Condition | Min. | Typ. | Max. | Units |
|---|---|---|---|---|---|---|
| Supply Current (V DDIO , V DDA_3.3 = 3.3V) (14) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (14) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (14) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (14) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (14) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (14) | Supply Current (V DDIO , V DDA_3.3 = 3.3V) (14) |
| I DD1_3.3V | 10Base-T | Full-duplex traffic @100% utilization | 41 | mA | ||
| I DD2_3.3V | 100Base-TX | Full-duplex traffic @100% utilization | 47 | mA | ||
| I DD3_3.3V | EDPD Mode | Ethernet cable disconnected (reg. 18h.11 = 0) | 20 | mA | ||
| I DD4_3.3V | Power-Down Mode | Software power-down (reg. 0h.11 = 1) | 4 | mA | ||
| CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs |
| V IH | Input High Voltage | V DDIO = 3.3V | 2.0 | V | ||
| V IH | Input High Voltage | V DDIO = 2.5V | 1.8 | V | ||
| V IH | Input High Voltage | V DDIO = 1.8V | 1.3 | V | ||
| V IL | Input Low Voltage | V DDIO = 3.3V | 0.8 | |||
| V IL | Input Low Voltage | V DDIO = 2.5V | 0.7 | V | ||
| V IL | Input Low Voltage | V DDIO = 1.8V | 0.5 | |||
| \ | I IN \ | Input Current | V IN = GND ~ VDDIO | |||
| CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs |
| V OH | Output High Voltage | V DDIO = 3.3V | 2.4 | V | ||
| V OH | Output High Voltage | V DDIO = 2.5V | 2.0 | V | ||
| V OH | Output High Voltage | V DDIO = 1.8V | 1.5 | V | ||
| V OL | Output Low Voltage | V DDIO = 3.3V | 0.4 | V | ||
| V OL | Output Low Voltage | V DDIO = 2.5V | 0.4 | V | ||
| V OL | Output Low Voltage | V DDIO = 1.8V | 0.3 | V | ||
| \ | I oz \ | Output Tri-State Leakage | ||||
| LED Output | LED Output | LED Output | LED Output | LED Output | LED Output | LED Output |
| I LED | Output Drive Current | Each LED pin (LED0, LED1) | 8 | mA |
KSZ8081MNXIA Absolute Maximum Ratings
- (V DD_1.2 ) .................................................. -0.5V to +1.8V
- (V DDIO , V DDA_3.3 ) ...................................... -0.5V to +5.0V
- Input Voltage (all inputs) .............................. -0.5V to +5.0V
- Output Voltage (all outputs) ......................... -0.5V to +5.0V
- Lead Temperature (soldering, 10s)............................260°C
- Storage Temperature (T S ).........................-55°C to +150°C
KSZ8081MNXIA Package Information
Table 26. Compatible Single-Port 10/100 Magnetics
- Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
32-Pin 5mm × 5mm QFN
32-Pin 5mm × 5mm QFN
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| KSZ8081 | Microchip Technology | VQFN-32 5x5mm |
| KSZ8081MNX | Microchip Technology | QFN-32 5x5mm |
| KSZ8081MNX-EVAL | Microchip Technology | 32-Pin QFN |
| KSZ8081MNX/RNB | Microchip Technology | QFN-32 5x5mm |
| KSZ8081MNXCA | Microchip Technology | 32-VFQFN Exposed Pad |
| KSZ8081RNB | Microchip Technology | 32-Pin QFN |
| KSZ8081RNB-EVAL | Microchip Technology | 32-Pin QFN |
| KSZ8081RNBCA | Microchip Technology | 32-Pin QFN |
| KSZ8081RNBIA | Microchip Technology | 32-Pin QFN |
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