KSZ8081MNX32

KSZ8081MNX/KSZ8081RNB

Manufacturer

Microchip Technology

Overview

Part: KSZ8081MNX/KSZ8081RNB, Micrel Inc.

Type: 10Base-T/100Base-TX Physical Layer Transceiver

Key Specs:

Ethernet Standard: 10Base-T/100Base-TX
Core Supply: 1.2V (built-in regulator)
Single Power Supply: 3.3V
VDD I/O Options: 1.8V, 2.5V, or 3.3V
Crystal Frequency: 25MHz
RMII Reference Clock Output: 50MHz

Features:

Single-chip IEEE 802.3 compliant Ethernet transceiver
MII interface support (KSZ8081MNX)
RMII v1.2 Interface support (KSZ8081RNB)
Back-to-back mode support for a 100Mbps copper repeater
MDC/MDIO management interface
Programmable interrupt output
LED outputs for link, activity, and speed status indication
On-chip termination resistors for differential pairs
Baseline wander correction
HP Auto MDI/MDI-X with disable/enable option
Auto-negotiation (10/100Mbps speed, half/full duplex)
Power-down and power-saving modes
LinkMD TDR-based cable diagnostics
Parametric NAND Tree support for fault detection
Loopback modes for diagnostics

Applications:

Game console
IP phone
IP set-top box
IP TV
LOM
Printer

Package:

32-pin QFN: 5mm x 5mm

Features

Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
MII interface support (KSZ8081MNX)
RMII v1.2 Interface support with a 50MHz reference clock output to MAC, and an option to input a 50MHz reference clock (KSZ8081RNB)
Back-to-back mode support for a 100Mbps copper repeater
MDC/MDIO management interface for PHY register configuration
Programmable interrupt output
LED outputs for link, activity, and speed status indication
On-chip termination resistors for the differential pairs
Baseline wander correction
HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option
Auto-negotiation to automatically select the highest linkup speed (10/100Mbps) and duplex (half/full)
Power-down and power-saving modes
LinkMD TDR-based cable diagnostics to identify faulty copper cabling
Parametric NAND Tree support for fault detection between chip I/Os and the board

Applications

Game console
IP phone
IP set-top box
IP TV
LOM
Printer

Ordering Information

Part Number	Temperature Range	Package	Lead Finish	Wire Bonding	Description
KSZ8081MNXCA	0°C to 70°C	32-Pin QFN	Pb-Free	Gold	MII, Commercial Temperature, Gold Wire Bonding
KSZ8081MNXCC(1)	0°C to 70°C	32-Pin QFN	Pb-Free	Copper	MII, Commercial Temperature, Copper Wire Bonding
KSZ8081MNXIA(1)	40°C to 85°C	32-Pin QFN	Pb-Free	Gold	MII, Industrial Temperature, Gold Wire Bonding
KSZ8081MNXIC(1)	40°C to 85°C	32-Pin QFN	Pb-Free	Copper	MII, Industrial Temperature, Copper Wire Bonding
KSZ8081RNBCA	0°C to 70°C	32-Pin QFN	Pb-Free	Gold	RMII with 25MHz crystal/clock input and 50MHz RMII REF_CLK output (power-up default), Commercial Temperature, Gold Wire Bonding
KSZ8081RNBCC(1)	0°C to 70°C	32-Pin QFN	Pb-Free	Copper	RMII with 25MHz crystal/clock input and 50MHz RMII REF_CLK output (power-up default), Commercial Temperature, Copper Wire Bonding
KSZ8081RNBIA(1)	40°C to 85°C	32-Pin QFN	Pb-Free	Gold	RMII with 25MHz crystal/clock input and 50MHz RMII REF_CLK output (power-up default), Industrial Temperature, Gold Wire Bonding
KSZ8081RNBIC(1)	40°C to 85°C	32-Pin QFN	Pb-Free	Copper	RMII with 25MHz crystal/clock input and 50MHz RMII REF_CLK output (power-up default), Industrial Temperature, Copper Wire Bonding
KSZ8081MNX-EVAL	0°C to 70°C	32-Pin QFN	Pb-Free		KSZ8081MNX Evaluation Board (Mounted with KSZ8081MNX device in commercial temperature)
KSZ8081RNB-EVAL	0°C to 70°C	32-Pin QFN	Pb-Free		KSZ8081RNB Evaluation Board (Mounted with KSZ8081RNB device in commercial temperature)

Note:

Contact factory for lead time.

Revision History

Revision	Date	Summary of Changes
1.0	11/05/12	Data sheet created

| General Description 1 | | :------------------------------------------------------------------------------------------ | :---- | | Features 1 | 1 | | Functional Diagram 1 | 1 | | Features (Continued) 2 | 2 | | Applications 2 | 2 | | Ordering Information 2 | 2 | | Revision History 3 | 3 | | Contents 4 | 4 | | List of Figures 6 | 6 | | List of Tables 7 | 7 | | Pin Configuration– KSZ8081MNX 8 | 8 | | Pin Description– KSZ8081MNX 9 | 9 | | Strapping Options – KSZ8081MNX 12 | 12 | | Pin Configuration – KSZ8081RNB 13 | 13 | | Pin Description– KSZ8081RNB 14 | 14 | | Strapping Options – KSZ8081RNB 17 | 17 | | Functional Description: 10Base-T/100Base-TX Transceiver 18 | 18 | | 100Base-TX Transmit 18 | 18 | | 100Base-TX Receive 18 | 18 | | Scrambler/De-Scrambler (100Base-TX Only) 18 | 18 | | 10Base-T Transmit 18 | 18 | | 10Base-T Receive 19 | 19 | | SQE and Jabber Function (10Base-T Only) 19 | 19 | | PLL Clock Synthesizer 19 | 19 | | Auto-Negotiation 19 | 19 | | MII Interface (KSZ8081MNX only) 20 | 20 | | MII Signal Definition 20 | 20 | | MII Signal Diagram 22 | 22 | | RMII Data Interface (KSZ8081RNB only) 23 | 23 | | RMII – 25MHz Clock Mode 23 | 23 | | RMII – 50MHz Clock Mode 23 | 23 | | RMII Signal Definition 23 | 23 | | RMII Signal Diagram 25 | 25 | | Back-to-Back Mode – 100Mbps Copper Repeater 26 | 26 | | MII Back-to-Back Mode (KSZ8081MNX only) 26 | 26 | | RMII Back-to-Back Mode (KSZ8081RNB only) 27 | 27 | | MII Management (MIIM) Interface 27 | 27 | | Interrupt (INTRP) 28 | 28 | | HP Auto MDI/MDI-X 28 | 28 | | Straight Cable 28 | 28 | | Crossover Cable 29 | 29 | | Loopback Mode 30 | 30 | | Local (Digital) Loopback 30 | 30 | | Remote (Analog) Loopback 30 | 30 | | LinkMD® Cable Diagnostic 31 | 31 | | NAND Tree Support 31 | 31 | | NAND Tree I/O Testing 33 | 33 | | Power Management 34 | 34 | | Power-Saving Mode 34 | 34 | | Energy-Detect Power-Down Mode 34 | 34 | | Power-Down Mode 34 | 34 | | Slow-Oscillator Mode 34 | 34 | | Reference Circuit for Power and Ground Connections 35 | 35 | | Typical Current/Power Consumption 36 | 36 | | Transceiver (3.3V), Digital I/Os (3.3V) 36 | 36 | | Transceiver (3.3V), Digital I/Os (2.5V) 36 | 36 | | Transceiver (3.3V), Digital I/Os (1.8V) 37 | 37 | | Register Map 38 | 38 | | Register Description 39 | 39 | | Absolute Maximum Ratings(1) 48 | 48 | | Operating Ratings(2) 48 | 48 | | Electrical Characteristics(3) 48 | 48 | | Timing Diagrams 50 | 50 | | MII SQE Timing (10Base-T) 50 | 50 | | MII Transmit Timing (10Base-T) 51 | 51 | | MII Receive Timing (10Base-T) 52 | 52 | | MII Transmit Timing (100Base-TX) 53 | 53 | | MII Receive Timing (100Base-TX) 54 | 54 | | RMII Timing 55 | 55 | | Auto-Negotiation Timing 56 | 56 | | MDC/MDIO Timing 57 | 57 | | Power-Up/Reset Timing 58 | 58 | | Reset Circuit 59 | 59 | | Reference Circuits – LED Strap-In Pins 60 | 60 | | Reference Clock – Connection and Selection 61 | 61 | | Magnetic – Connection and Selection 62 | 62 | | Recommended Land Pattern 64 | 64 | | Package Information(1) 65 | 65 |

Figure 1. Auto-Negotiation Flow Chart20
Figure 2. KSZ8081MNX MII Interface22
Figure 3. KSZ8081RNB RMII Interface (25MHz Clock Mode)25
Figure 4. KSZ8081RNB RMII Interface (50MHz Clock Mode)25
Figure 5. KSZ8081MNX/RNB to KSZ8081MNX/RNB Back-to-Back Copper Repeater 26
Figure 6. Typical Straight Cable Connection 29
Figure 7. Typical Crossover Cable Connection 29
Figure 8. Local (Digital) Loopback 30
Figure 9. Remote (Analog) Loopback 31
Figure 10. KSZ8081MNX/RNB Power and Ground Connections35
Figure 11. MII SQE Timing (10Base-T) 50
Figure 12. MII Transmit Timing (10Base-T) 51
Figure 13. MII Receive Timing (10Base-T) 52
Figure 14. MII Transmit Timing (100Base-TX)53
Figure 15. MII Receive Timing (100Base-TX)54
Figure 16. RMII Timing – Data Received from RMII55
Figure 17. RMII Timing – Data Input to RMII 55
Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing 56
Figure 19. MDC/MDIO Timing57
Figure 20. Power-Up/Reset Timing58
Figure 21. Recommended Reset Circuit59
Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output 59
Figure 23. Reference Circuits for LED Strapping Pins60
Figure 24. 25MHz Crystal/Oscillator Reference Clock Connection 61
Figure 25. 50MHz Oscillator Reference Clock Connection 61
Figure 26. Typical Magnetic Interface Circuit62
Figure 27. Recommended Land Pattern, 32-Pin (5mm x 5mm) QFN 64

Pin Configuration

32-Pin (5mm x 5mm) QFN

Pin Description– KSZ8081MNX

Pin Number	Pin Name	Type(1)	Pin Function
1	GND	Gnd	Ground
2	VDD_1.2	P	1.2V core VDD (power supplied by KSZ8081MNX) Decouple with 2.2μF and 0.1μF capacitors to ground.
3	VDDA_3.3	P	3.3V analog VDD
4	RXM	I/O
5	RXP	I/O
6	TXM	I/O
7	TXP	I/O
8	XO	O
9	XI	I	25MHz ±50ppm
10	REXT	I
11	MDIO	Ipu/Opu
			pull-up resistor.
12	MDC	Ipu	Management Interface (MII) Clock input This clock pin is synchronous to the MDIO data pin.
13	RXD3/	Ipu/O	MII mode:
	PHYAD0		Config mode:
14	RXD2/	Ipd/O	MII mode:
	PHYAD1		Config mode:
15	RXD1/	Ipd/O	MII mode:
	PHYAD2		Config mode:
16	RXD0/	Ipu/O	MII mode:
	DUPLEX		Config mode:
17	VDDIO	P	3.3V, 2.5V, or 1.8V digital VDD
18	RXDV/	Ipd/O	MII mode: MII Receive Data Valid output
	CONFIG2		Config mode:
19	RXC/	Ipd/O	MII mode:
	B-CAST_OFF		Config mode:
Pin Number	Pin Name	Type(1)	Pin Function
------------	------------	---------	--------------------------------------------------
20	RXER/	Ipd/O	MII mode: MII Receive Error output
	ISO		Config mode: See the "Strapping Options" section for details.
21	INTRP/	Ipu/Opu
			resistor.
	NAND_Tree#		Config mode:
22	TXC	I/O	MII mode:
			MII back-to-back mode:
23	TXEN	I	MII mode:
24	TXD0	I	MII mode:
25	TXD1	I	MII mode:
26	TXD2	I	MII mode:
27	TXD3	I	MII Mode:
28	COL/	Ipd/O	MII mode:
	CONFIG0		Config mode: See the "Strapping Options" section for details.
29	CRS/	Ipd/O	MII mode: MII Carrier Sense output
	CONFIG1		Config mode: See the "Strapping Options" section for details.
30	LED0/	Ipu/O	LED output: Programmable LED0 output
	NWAYEN		Config mode:
			follows. LED mode = [00]
			Link/Activity
			No link
			Link
			Activity LED mode = [01]
			Link
			No link
			Link LED mode = [10], [11] Reserved
Pin Number	Pin Name	Type(1)	Pin Function
------------	----------	---------	-------------------------
31	LED1/	Ipu/O	LED output:
	SPEED		Config mode:
			follows.
			Speed
			10Base-T
			100Base-TX LED mode = [01]
			Activity
			No activity
			Activity
			LED mode = [10], [11]
32	RST#	Ipu	Chip reset (active low)
PADDLE	GND	Gnd	Ground

Notes:

1. P = Power supply.
- Gnd = Ground.
  - I = Input.
  - O = Output.
  - I/O = Bi-directional.
  - Ipu = Input with internal pull-up (see "Electrical Characteristics" for value).
  - Ipu/O = Input with internal pull-up (see "Electrical Characteristics" for value) during power-up/reset; output pin otherwise.
  - Ipd/O = Input with internal pull-down (see "Electrical Characteristics" for value) during power-up/reset; output pin otherwise.
- Ipu/Opu = Input with internal pull-up (see "Electrical Characteristics" for value) and output with internal pull-up (see "Electrical Characteristics" for value).
1. MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC. RXD[3:0] is invalid data from the PHY when RXDV is de-asserted.
1. MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC. TXD[3:0] has no effect on the PHY when TXEN is de-asserted.

Strapping Options – KSZ8081MNX

Pin Number	Pin Name	Type(1)	Pin Function
15	PHYAD2	Ipd/O	PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value from 0
14	PHYAD1	Ipd/O	to 7 with PHY Address 1 as the default value.
13	PHYAD0	Ipu/O	PHY Address 0 is assigned by default as the broadcast PHY address, but it can be assigned as a unique PHY address after pulling the B

Note:

Ipu/O = Input with internal pull-up (see "Electrical Characteristics" for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see "Electrical Characteristics" for value) during power-up/reset; output pin otherwise.

Ipu/Opu = Input with internal pull-up (see "Electrical Characteristics" for value) and output with internal pull-up (see "Electrical Characteristics" for value).

The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly.

Electrical Characteristics

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
Supply Current (VDDIO, VDDA_3.3 = 3.3V)(4)
IDD1_3.3V	10Base-T	Full-duplex traffic @ 100% utilization		41		mA
IDD2_3.3V	100Base-TX	Full-duplex traffic @ 100% utilization		47		mA
IDD3_3.3V	EDPD Mode	Ethernet cable disconnected (reg. 18h.11 = 0)		20		mA
IDD4_3.3V	Power-Down Mode	Software power-down (reg. 0h.11 = 1)		4		mA
CMOS Level Inputs
VIH	Input High Voltage	VDDIO = 3.3V	2.0			V
		VDDIO = 2.5V VDDIO = 1.8V	1.8 1.3			V V
VIL	Input Low Voltage	VDDIO = 3.3V			0.8	V
		VDDIO = 2.5V VDDIO = 1.8V			0.7 0.5	V V
IIN	Input Current	VIN = GND ~ VDDIO			10	μA
CMOS Level Outputs
VOH	Output High Voltage	VDDIO = 3.3V	2.4			V
		VDDIO = 2.5V VDDIO = 1.8V	2.0 1.5			V V
VOL	Output Low Voltage	VDDIO = 3.3V			0.4	V
		VDDIO = 2.5V VDDIO = 1.8V			0.4 0.3	V V
Ioz	Output Tri-State Leakage				10	μA
LED Output
ILED	Output Drive Current	Each LED pin (LED0, LED1)		8		mA

Exceeding the absolute maximum rating can damage the device. Stresses greater than the absolute maximum rating can cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
The device is not guaranteed to function outside its operating rating.
TA = 25°C. Specification is for packaged product only.
Current consumption is for the single 3.3V supply KSZ8081MNX/RNB device only, and includes the transmit driver current and the 1.2V supply voltage (VDD_1.2) that are supplied by the KSZ8081MNX/RNB.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
All Pull-Up/Pull-Down Pins (including Strapping Pins)
		VDDIO = 3.3V	30	45	73	kΩ
pu	Internal Pull-Up Resistance	VDDIO = 2.5V	39	61	102	kΩ
		VDDIO = 1.8V	48	99	178	kΩ
		VDDIO = 3.3V	26	43	79	kΩ
pd	Internal Pull-Down Resistance	VDDIO = 2.5V	34	59	113	kΩ
	100Base-TX Transmit (measured differentially after 1:1 transformer)	VDDIO = 1.8V	53	99	200	kΩ
VO	Peak Differential Output Voltage	100Ω termination across differential output	0.95		1.05	V
VIMB	Output Voltage Imbalance	100Ω termination across differential output			2	%
tr, tf	Rise/Fall Time		3		5	ns
	Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot		0		0.5 ±0.25 5	ns ns %
	Output Jitter 10Base-T Transmit (measured differentially after 1:1 transformer)	Peak-to-peak		0.7		ns
VP	Peak Differential Output Voltage	100Ω termination across differential output	2.2		2.8	V
	Jitter Added	Peak-to-peak			3.5	ns
tr, tf	Rise/Fall Time			25		ns
10Base-T Receive
VSQ	Squelch Threshold Transmitter – Drive Setting	5MHz square wave		400		mV
VSET	Reference Voltage of ISET	R(ISET) = 6.49kΩ		0.65		V
REF_CLK Output
	50MHz RMII Clock Output Jitter 100Mbps Mode – Industrial Applications Parameters	Peak-to-peak (Applies only to KSZ8081RNB in RMII – 25MHz clock mode)		300		ps
	Clock Phase Delay – XI Input to MII TXC Output	XI (25MHz clock input) to MII TXC (25MHz clock output) delay, referenced to rising edges of both clocks. (Applies only to KSZ8081MNX in MII mode)	15	20	25	ns
tllr	Link Loss Reaction (Indication) Time	Link loss detected at receive differential inputs to PHY signal indication time for each of the following: 1. For LED mode 00, Speed LED output changes from low (100Mbps) to high (10Mbps, default state for link-down). 2. For LED mode 01, Link LED output changes from low (link-up) to high (link-down). 3. INTRP pin asserts for link-down status change.		4.4		μs

Absolute Maximum Ratings

Parameter	Value
Supply Voltage (VIN)
(VDD_1.2)	-0.5V to +1.8V
(VDDIO, VDDA_3.3)	-0.5V to +5.0V
Input Voltage (all inputs)	-0.5V to +5.0V
Output Voltage (all outputs)	-0.5V to +5.0V
Lead Temperature (soldering, 10sec.)	260°C
Storage Temperature (TS)	-55°C to +150°C

Related Variants

The following components are covered by the same datasheet.

Part Number	Manufacturer	Package
KSZ8081	Microchip Technology	—
KSZ8081MNX	Microchip Technology	—
KSZ8081MNX-EVAL	Microchip Technology	—
KSZ8081MNX/RNB	Microchip Technology	—
KSZ8081MNXCA	Microchip Technology	32-VFQFN Exposed Pad
KSZ8081MNXCC	Microchip Technology	—
KSZ8081MNXIA	Microchip Technology	—
KSZ8081MNXIC	Microchip Technology	—
KSZ8081RNB	Microchip Technology	—
KSZ8081RNB-EVAL	Microchip Technology	—
KSZ8081RNBCA	Microchip Technology	—
KSZ8081RNBCC	Microchip Technology	—
KSZ8081RNBIA	Microchip Technology	—
KSZ8081RNBIC	Microchip Technology	—

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