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KSZ8081MNX/RNB28

10Base-T/100Base-TX Physical Layer Transceiver

Physical Layer Transceiver

The KSZ8081MNX/RNB28 is a physical layer transceiver from Microchip Technology. 10Base-T/100Base-TX Physical Layer Transceiver. View the full KSZ8081MNX/RNB28 datasheet below including electrical characteristics, absolute maximum ratings.

Manufacturer

Microchip Technology

Category

Physical Layer Transceiver

Overview

Part: KSZ8081MNX/KSZ8081RNB, Micrel, Inc.

Type: 10Base-T/100Base-TX Physical Layer Transceiver

Description: The KSZ8081 is a single-supply 10Base-T/100Base-TX Ethernet physical-layer transceiver offering MII or RMII interfaces, integrated 1.2V core regulator, on-chip termination resistors, and LinkMD TDR-based cable diagnostics.

Operating Conditions:

  • Supply voltage: Single 3.3V (core), 1.8V/2.5V/3.3V (VDD I/O options)
  • Operating temperature: 0°C to 85°C (commercial and industrial ranges combined)
  • Reference clock input: 25MHz crystal/oscillator (or 50MHz oscillator for RMII mode)

Absolute Maximum Ratings:

  • Max supply voltage: null
  • Max continuous current: null
  • Max junction/storage temperature: null

Key Specs:

  • Data rates: 10Base-T and 100Base-TX
  • Interface options: MII (KSZ8081MNX) or RMII v1.2 (KSZ8081RNB)
  • Integrated 1.2V regulator for core supply
  • On-chip termination resistors for differential pairs
  • HP Auto MDI/MDI-X support
  • Auto-negotiation for 10/100Mbps speed and half/full duplex
  • LinkMD TDR-based cable diagnostics
  • MDC/MDIO management interface

Features:

  • Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
  • MII interface support (KSZ8081MNX)
  • RMII v1.2 Interface support with a 50MHz reference clock output to MAC, and an option to input a 50MHz reference clock (KSZ8081RNB)
  • Back-to-back mode support for a 100Mbps copper repeater
  • MDC/MDIO management interface for PHY register configuration
  • Programmable interrupt output
  • LED outputs for link, activity, and speed status indication
  • On-chip termination resistors for the differential pairs
  • Baseline wander correction
  • HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option
  • Auto-negotiation to automatically select the highest linkup speed (10/100Mbps) and duplex (half/full)
  • Power-down and power-saving modes
  • LinkMD TDR-based cable diagnostics to identify faulty copper cabling
  • Parametric NAND Tree support for fault detection between chip I/Os and the board
  • Loopback modes for diagnostics
  • Single 3.3V power supply with VDD I/O options for 1.8V, 2.5V, or 3.3V
  • Built-in 1.2V regulator for core

Applications:

  • Game console
  • IP phone
  • IP set-top box
  • IP TV
  • LOM
  • Printer

Package:

  • 32-pin QFN (5mm x 5mm)

Features

  • Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver
  • MII interface support (KSZ8081MNX)
  • RMII v1.2 Interface support with a 50MHz reference clock output to MAC, and an option to input a 50MHz reference clock (KSZ8081RNB)
  • Back-to-back mode support for a 100Mbps copper repeater
  • MDC/MDIO management interface for PHY register configuration
  • Programmable interrupt output
  • LED outputs for link, activity, and speed status indication
  • On-chip termination resistors for the differential pairs
  • Baseline wander correction
  • HP Auto MDI/MDI-X to reliably detect and correct straight-through and crossover cable connections with disable and enable option
  • Auto-negotiation to automatically select the highest linkup speed (10/100Mbps) and duplex (half/full)
  • · Power-down and power-saving modes
  • LinkMD TDR-based cable diagnostics to identify faulty copper cabling
  • Parametric NAND Tree support for fault detection between chip I/Os and the board

Applications

  • Game console
  • IP phone
  • IP set-top box
  • IP TV
  • LOM
  • Printer

Pin Configuration

32-Pin (5mm x 5mm) QFN

November 2012 8 M9999-110512-1.0

Electrical Characteristics

SymbolParameterConditionMin.Typ.Max.Units
Supply Current (VDDIO, VDDA_3.3 = 3.3V)(4)
IDD1_3.3V10Base-TFull-duplex traffic @ 100% utilization41mA
IDD2_3.3V100Base-TXFull-duplex traffic @ 100% utilization47mA
IDD3_3.3VEDPD ModeEthernet cable disconnected (reg.
IDD3_3.3VEDPD ModeEthernet cable disconnected (reg. mode)25mA
IDD4_3.3VPower-Down ModeAll clocks stopped, no traffic10mA
IDD5_3.3VSleep ModeAll clocks stopped, no traffic10mA
IDD6_3.3VDeep Power-Down ModeAll clocks stopped, no traffic1mA
Supply Current (VDDIO, VDDA_2.5 = 2.5V)(4)
IDD7_2.5V100Base-TXFull-duplex traffic @ 100% utilization47mA
IDD8_2.5V10Base-TFull-duplex traffic @ 100% utilization41mA
IDD9_2.5VEDPD ModeEthernet cable disconnected (reg. mode)25mA
IDD10_2.5VPower-Down ModeAll clocks stopped, no traffic10mA
IDD11_2.5VSleep ModeAll clocks stopped, no traffic10mA
IDD12_2.5VDeep Power-Down ModeAll clocks stopped, no traffic1mA
Supply Current (VDDIO, VDDA_1.8 = 1.8V)(4)
IDD13_1.8V100Base-TXFull-duplex traffic @ 100% utilization47mA
IDD14_1.8V10Base-TFull-duplex traffic @ 100% utilization41mA
IDD15_1.8VEDPD ModeEthernet cable disconnected (reg. mode)25mA
IDD16_1.8VPower-Down ModeAll clocks stopped, no traffic10mA
IDD17_1.8VSleep ModeAll clocks stopped, no traffic10mA
IDD18_1.8VDeep Power-Down ModeAll clocks stopped, no traffic1mA

Notes:

    1. Exceeding the absolute maximum rating can damage the device. Stresses greater than the absolute maximum rating can cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
    1. The device is not guaranteed to function outside its operating rating.
    1. TA = 25°C. Specification is for packaged product only.
    1. Current consumption is for the single 3.3V supply KSZ8081MNX/RNB device only, and includes the transmit driver current and the 1.2V supply voltage (VDD_1.2) that are supplied by the KSZ8081MNX/RNB.

November 2012 48 M9999-110512-1.0

SymbolParameterConditionMin.Typ.Max.Units
All Pull-Up/Pull-Down Pins (including Strapping Pins)
VDDIO = 3.3V304573
puInternal Pull-Up ResistanceVDDIO = 2.5V3961102
VDDIO = 1.8V4899178
VDDIO = 3.3V264379
pdInternal Pull-Down ResistanceVDDIO = 2.5V3459113
100Base-TX Transmit (measured differentially after 1:1 transformer)VDDIO = 1.8V5399200
VOPeak Differential Output Voltage100Ω termination across differential output0.951.05V
VIMBOutput Voltage Imbalance100Ω termination across differential output2%
tr, tfRise/Fall Time35ns
Rise/Fall Time Imbalance
Duty Cycle Distortion
Overshoot
00.5
±0.25
5
ns
ns
%
Output Jitter
10Base-T Transmit (measured differentially after 1:1 transformer)
Peak-to-peak0.7ns
VPPeak Differential Output Voltage100Ω termination across differential output2.22.8V
Jitter AddedPeak-to-peak3.5ns
tr, tfRise/Fall Time25ns
10Base-T Receive
VSQSquelch Threshold
Transmitter – Drive Setting
5MHz square wave400mV
VSETReference Voltage of ISETR(ISET) = 6.49kΩ0.65V
REF_CLK Output
50MHz RMII Clock Output Jitter
100Mbps Mode – Industrial Applications Parameters
Peak-to-peak
(Applies only to KSZ8081RNB in RMII –
25MHz clock mode)
300ps
Clock Phase Delay – XI Input to
MII TXC Output
XI (25MHz clock input) to MII TXC (25MHz
clock output) delay, referenced to rising edges
of both clocks.
(Applies only to KSZ8081MNX in MII mode)
152025ns
tllrLink Loss Reaction (Indication)
Time
Link loss detected at receive differential inputs
to PHY signal indication time for each of the
following:
1. For LED mode 00, Speed LED output
changes from low (100Mbps) to high (10Mbps,
default state for link-down).
2. For LED mode 01, Link LED output changes
from low (link-up) to high (link-down).
3. INTRP pin asserts for link-down status
change.
4.4μs

Absolute Maximum Ratings

ParameterRating
Supply Voltage (VIN)
(VDD_1.2)-0.5V to +1.8V
(VDDIO, VDDA_3.3)-0.5V to +5.0V
Input Voltage (all inputs)-0.5V to +5.0V
Output Voltage (all outputs)-0.5V to +5.0V
Lead Temperature (soldering, 10sec.)260°C
Storage Temperature (Ts)-55°C to +150°C

Package Information

Figure 27. Recommended Land Pattern, 32-Pin (5mm x 5mm) QFN

Red circles indicate thermal vias. They should be 0.350mm in diameter and be connected to the GND plane for maximum thermal performance.

Green rectangles (with shaded area) indicate solder stencil openings on the exposed pad area. They should be 0.87 x 0.87mm in size, 1.07mm pitch.

November 2012 64 M9999-110512-1.0

Related Variants

The following components are covered by the same datasheet.

Part NumberManufacturerPackage
KSZ8081Microchip Technology
KSZ8081MNXMicrochip Technology
KSZ8081MNX-EVALMicrochip Technology32-Pin QFN
KSZ8081MNX/RNBMicrochip Technology
KSZ8081MNX32Microchip Technology
KSZ8081MNXCAMicrochip Technology32-VFQFN Exposed Pad
KSZ8081MNXCCMicrochip Technology32-Pin QFN
KSZ8081MNXIAMicrochip Technology32-Pin QFN
KSZ8081MNXICMicrochip Technology32-Pin QFN
KSZ8081RNBMicrochip Technology32-Pin QFN
KSZ8081RNB-EVALMicrochip Technology32-Pin QFN
KSZ8081RNB33Microchip Technology
KSZ8081RNBCAMicrochip Technology32-Pin QFN
KSZ8081RNBCCMicrochip Technology32-Pin QFN
KSZ8081RNBIAMicrochip Technology32-Pin QFN
KSZ8081RNBICMicrochip Technology32-Pin QFN
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