EFR32FG28B322F1024IM68-A

Part: EFR32FG28 Wireless SoC Family — Silicon Labs

Type: Wireless System-on-Chip (SoC)

Description: A dual-band Sub-GHz + 2.4 GHz BLE SoC featuring a 78 MHz ARM Cortex-M33 core, up to 1024 kB Flash, up to 256 kB RAM, integrated PAs with up to 20 dBm for Sub-GHz and 10 dBm for BLE, and a Matrix Vector Processor for AI/ML acceleration, designed for secure IoT applications.

Operating Conditions:

• Supply voltage: 1.71 V to 3.8 V
• Operating temperature: -40 °C to +125 °C
• Max operating frequency: 78 MHz (ARM Cortex-M33)

Absolute Maximum Ratings:

Key Specs:

• CPU: 32-bit ARM Cortex-M33 with DSP and FPU
• Flash memory: Up to 1024 kB
• RAM data memory: Up to 256 kB
• Sub-GHz TX power: Up to +20 dBm
• 2.4 GHz BLE TX power: Up to +10 dBm
• EM2 DeepSleep current: 2.8 μA (256 kB RAM retention, RTC from LFXO)
• ADC resolution/speed: 12-bit @ 1 Msps, 16-bit @ 76.9 ksps
• GPIO: Up to 49

Features:

• Matrix Vector Processor for AI/ML acceleration
• Energy-efficient radio core with low active and sleep currents
• Hardware Cryptographic Acceleration (AES128/192/256, ChaCha20-Poly1305, SHA, ECDSA, Ed25519, Curve25519, J-PAKE, PBKDF2)
• True Random Number Generator (TRNG)
• ARM TrustZone, Secure Boot, Secure Debug Unlock, DPA Countermeasures, Secure Key Management with PUF, Anti-Tamper, Secure Attestation
• Wide selection of MCU peripherals including ADC, DAC, ACMP, LESENSE, Timers, Watchdog, EUSART, UART/SPI/SmartCard/IrDA/I2S, I2C, LCD Controller, Keypad scanner
• Preamble Sense Mode (PSM) low duty-cycle listen

Applications:

• Metering
• Home and Building Automation and Security
• Industrial Automation
• Street Lighting

Package:

• QFN68 (8 mm × 8 mm × 0.85 mm)
• QFN48 (6 mm × 6 mm × 0.85 mm)

• 32-bit ARM® Cortex®-M33 core with 78 MHz maximum operating frequency
• 1024 kB of flash and up to 256 kB of RAM
• Energy-efficient radio core with low active and sleep currents
• Integrated PAs with up to 20 dBm for subGHz and 10 dBm for BLE transmit power
• Robust peripheral set and up to 49 GPIO
• QFN48 and QFN68 package options

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:

• Typical values are based on T A =25 °C and all supplies at 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output power-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature, unless stated otherwise.

Due to on-chip circuitry (e.g., diodes), some EFR32FG28 power supply pins have a dependent relationship with one or more other power supply pins. These internal relationships between the external voltages applied to the various EFR32FG28 supply pins are defined below. Exceeding the below constraints can result in damage to the device and/or increased current draw.

• VREGVDD and DVDD
• In systems using the DCDC converter, DVDD (the buck converter output) should not be driven externally and VREGVDD (the buck converter input) must be greater than DVDD (VREGVDD ≥ DVDD)
• In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD = DVDD)
• AVDD, IOVDD: No dependency with each other or any other supply pin. Additional leakage may occur if DVDD remains unpowered with power applied to these supplies.
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 4.1. Absolute Maximum Ratings

1. When operating as an LCD driver, the output voltage on a GPIO may safely exceed this specification. The pin output voltage may be up to 3.8 V in this case.

2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at DVDD.

Table 4.4. Thermal Characteristics, 68QFN

1. PCB Center Land with 9 Via to top internal plane of PCB per JESD51- 5.

2. Based on 2 layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm.

Table 4.5. Thermal Characteristics, 48QFN

1. PCB Center Land with 9 Via to top internal plane of PCB per JESD51- 5.

2. Based on 2 layer PCB with dimension 3" x 4.5", PCB Thickness of 1.6 mm.

Figure 7.1. QFN48 Package Drawing

Table 7.1. QFN48 Package Dimensions

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to the JEDEC Outline MS-013, Variation AA.

4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.