DRV8320

Three-Phase Smart Gate Driver

The DRV8320 is a three-phase smart gate driver from Texas Instruments. View the full DRV8320 datasheet below including key specifications, electrical characteristics, absolute maximum ratings.

DRV8320 shares its datasheet with DRV8323, whose page lists every part number it covers.

Official DRV8320 datasheet (PDF) — the source this page was extracted from.

Manufacturer

Texas Instruments

DRV8320 Key Specifications

Parameter	Value
Ambient Temperature Range High	125 °C
Applications	Brushless DC (BLDC)
Case/Package	VQFN
Output Current	5mA
Function	Controller - Commutation, Direction Management
Height	1 mm
Interface	SPI
Length	7 mm
Lifecycle Status	Production (Last Updated: 2 days ago)
Manufacturer Lifecycle Status	ACTIVE (Last Updated: 2 days ago)
Max Junction Temperature (Tj)	150 °C
Max Operating Temperature	125 °C
Max Supply Voltage	60 V
Min Operating Temperature	-40 °C
Min Supply Voltage	4 V
Motor Type (DC)	Brushless DC (BLDC)
Motor Type (Stepper)	Multiphase
Mounting Type	Surface Mount
Nominal Supply Current	10.5 mA
Number of Pins	48
Operating Temperature	-40°C ~ 125°C (TA)
Output Configuration	Pre-Driver - Half Bridge (3)
Output Current	5 mA
Package / Case	48-VFQFN Exposed Pad
Packaging	MouseReel
RoHS	Compliant
Standard Pack Qty	2500
Supplier Device Package	48-VQFN (7x7)
Switching Frequency	700 kHz
Diode Technology	Power MOSFET
Thickness	900 µm
Supply Voltage	6V ~ 60V
Width	7 mm

DRV8320 Overview

Part: DRV8323R (DRV8323RS / DRV8323RH) — Texas Instruments

Type: Three-Phase Smart Gate Driver with Current Sense Amplifiers and Integrated Buck Regulator

Description: 6–60 V three-phase smart gate driver with up to 1 A source / 2 A sink peak gate current, three integrated current sense amplifiers, and a 600 mA buck regulator.

Operating Conditions:

Gate driver supply voltage (VM): 6–60 V
Buck regulator supply voltage (VIN): 4–60 V
Operating ambient temperature: -40 to 125 °C
Applied PWM frequency (INHx, INLx): up to 200 kHz
External DVDD load current: up to 30 mA

Absolute Maximum Ratings:

Max supply voltage (VM): 65 V
Max buck supply voltage (VIN): 65 V
Max operating junction temperature: 150 °C
Storage temperature: -65 to 150 °C

Key Specs:

Gate driver supply range: 6–60 V (VM)
Peak gate drive current: 10 mA to 1 A source, 20 mA to 2 A sink
Buck regulator output: 0.8 to 60 V, 600 mA
Current sense amplifier gain: 5, 10, 20, 40 V/V (adjustable), bidirectional or unidirectional
Sleep mode current: 12 μA (typical)
DVDD linear regulator: 3.3 V, 30 mA
Logic inputs: 1.8 V, 3.3 V, and 5 V supported
Input PWM modes: 6x, 3x, 1x, and independent

Features:

Triple half-bridge gate driver for N-channel MOSFETs
Smart Gate Drive architecture with adjustable slew rate control
Integrated high-side charge pump and low-side linear regulator
Supports 100% PWM duty cycle
Integrated buck regulator (LMR16006X SIMPLE SWITCHER)
Three integrated current sense amplifiers
SPI and hardware interface variants
Protection: VM UVLO, charge pump UV, MOSFET OCP, gate driver fault, thermal warning and shutdown
nFAULT fault indicator

Applications:

Brushless-DC (BLDC) and PMSM motor modules
Fans, pumps, and servo drives
E-bikes, e-scooters, and e-mobility
Cordless garden and power tools, lawnmowers
Cordless vacuum cleaners
Drones, robotics, and RC toys
Industrial and logistics robots

Package:

VQFN (48), 7.00 mm × 7.00 mm (DRV8323R)

DRV8320 Features

Triple Half-Bridge Gate Driver
-Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
Smart Gate Drive Architecture
-Adjustable Slew Rate Control
-10-mA to 1-A Peak Source Current
-20-mA to 2-A Peak Sink Current
Integrated Gate Driver Power Supplies
-Supports 100% PWM Duty Cycle
-High-Side Charge Pump
-Low-Side Linear Regulator
6 to 60-V Operating Voltage Range
Optional Integrated Buck Regulator
-LMR16006X SIMPLE SWITCHER ®
-4 to 60-V Operating Voltage Range
-0.8 to 60-V, 600-mA Output Capability
Optional Integrated Triple Current Sense Amplifiers (CSAs)
-Adjustable Gain (5, 10, 20, 40 V/V)
-Bidirectional or Unidirectional Support
SPI and Hardware Interface Available
6x, 3x, 1x, and Independent PWM Modes
Supports 1.8-V, 3.3-V, and 5-V Logic Inputs
Low-Power Sleep Mode (12 μA)
Linear Voltage Regulator, 3.3 V, 30 mA
Compact QFN Packages and Footprints
Efficient System Design With Power Blocks
Integrated Protection Features
-VM Undervoltage Lockout (UVLO)
-Charge Pump Undervoltage (CPUV)
-MOSFET Overcurrent Protection (OCP)
-Gate Driver Fault (GDF)
-Thermal Warning and Shutdown (OTW/OTSD)
-Fault Condition Indicator (nFAULT)

DRV8320 Applications

Brushless-DC (BLDC) Motor Modules and PMSM
Fans, Pumps, and Servo Drives
E-Bikes, E-Scooters, and E-Mobility
Cordless Garden and Power Tools, Lawnmowers
Cordless Vacuum Cleaners
Drones, Robotics, and RC Toys
Industrial and Logistics Robots

DRV8320 Pin Configuration

Pin Functions-32-Pin DRV8320 Devices

PIN - NAME	PIN - NO. - DRV8320H	PIN - NO. - DRV8320S	TYPE (1)	DESCRIPTION
AGND	23	23	PWR	Device analog ground. Connect to system ground.
CPH	1	1	PWR	Charge pump switching node. Connect aX5R or X7R, 47-nF, VM-rated ceramic capacitor betweentheCPH and CPLpins.
CPL	32	32	PWR	Charge pump switching node. Connect aX5R or X7R, 47-nF, VM-rated ceramic capacitor betweentheCPH and CPLpins.
DVDD	24	24	PWR	3.3-V internal regulator output. Connect aX5R or X7R, 1-μF, 6.3-V ceramic capacitor betweentheDVDD andAGND pins. This regulator can source up to 30 mAexternally.
ENABLE	22	22	I	Gate driver enable. When this pin is logic lowthe device goes to a low-power sleep mode. An8to 40-μs pulse can be used to reset fault conditions.
GHA	5	5	O	High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB	12	12	O	High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC	13	13	O	High-side gate driver output. Connect to the gate of the high-side power MOSFET.

Pin Functions-32-Pin DRV8320 Devices

DRV8320 Electrical Characteristics

at TA = -40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWERSUPPLIES (DVDD, VCP, VM)	POWERSUPPLIES (DVDD, VCP, VM)	POWERSUPPLIES (DVDD, VCP, VM)	POWERSUPPLIES (DVDD, VCP, VM)	POWERSUPPLIES (DVDD, VCP, VM)	POWERSUPPLIES (DVDD, VCP, VM)	POWERSUPPLIES (DVDD, VCP, VM)
I VM	VM operating supply current	V VM = 24 V, ENABLE = 3.3 V, INHx/INLx = 0 V		10.5	14	mA
I	VM sleep mode supply current	ENABLE = 0 V, V VM = 24 V, T A = 25°C		12	20	μA
VMQ		ENABLE = 0 V, V VM = 24 V, T A = 125°C (1)			50
t RST (1)	Reset pulse time	ENABLE = 0 V period to reset faults	8		40	μs
t WAKE t	Turnon time	V VM > V UVLO , ENABLE = 3.3 V to outputs ready mode			1 1	ms
SLEEP	Turnoff time DVDD regulator	ENABLE = 0 V to device sleep				ms
V DVDD	voltage	I DVDD = 0 to 30 mA	3	3.3	3.6	V
V VCP	VCP operating voltage with respect to VM	V VM = 13 V, I VCP = 0 to 25 mA V VM = 10 V, I VCP = 0 to 20 mA V VM = 8 V, I VCP = 0 to 15mA	8.4 6.3 5.4	11 9 7	12.5 10 8	V
LOGIC-LEVELINPUTS V IL	(CAL, ENABLE, INHx, Input logic lowvoltage Input logic highvoltage Input logic hysteresis	V VM = 6 V, I VCP = 0 to 10mA INLx, nSCS, SCLK, SDI)	4	5 100	6 0.8 5.5
V IH V	Input logic lowcurrent Input logic highcurrent Pulldown resistance Propagation delay INPUTS (GAIN,	V VIN = 0 V V VIN = 5 V Hi-Z Tied to DVDD	0 1.5 -5	0.5 1.1		V V
HYS I IL I IH R PD t PD V I1 V I2	Input mode 1 voltage Input mode 2 voltage	Internal pullup to DVDD		3.3 50 84		V
V I3 V I4	Input mode 4 voltage Pullup resistance	Hi-Z 75 k Ω ± 5%tied to DVDD		50 100 150 0
V I1 V I2 V I3	Pulldown resistance	Internal pulldown to AGND		1.2 2		V V mV
	(nFAULT, SDO)	Tied to AGND		2.2	5 70
V I4 V I5 V I6	(IDRIVE, Input mode 1 voltage Input mode 2 voltage Input mode 3 voltage Input mode 4 voltage Input mode 5 voltage Input mode 6 voltage	45 k Ω ± 5%to		2.8 3.3 73 73		μA μA k Ω
	Input mode 3 voltage	I O = 5 mA To AGND INHx/INLx transition to GHx/GLx transition	-2			ns
FOUR-LEVEL H/W MODE)	FOUR-LEVEL H/W MODE)	FOUR-LEVEL H/W MODE) Tied to AGND tied AGND	FOUR-LEVEL H/W MODE)	FOUR-LEVEL H/W MODE)	FOUR-LEVEL H/W MODE)	FOUR-LEVEL H/W MODE) V
R PU						k Ω
R PD	Pulldown resistance	Internal pulldown to AGND				k Ω
SEVEN-LEVELH/WINPUTS VDS)	SEVEN-LEVELH/WINPUTS VDS)	SEVEN-LEVELH/WINPUTS VDS) 18 k Ω ± 5%tied to AGND 75 k Ω ± 5%tied to AGND 18 k Ω ± 5%tied to DVDD	SEVEN-LEVELH/WINPUTS VDS)	SEVEN-LEVELH/WINPUTS VDS) 0 1.65	SEVEN-LEVELH/WINPUTS VDS)	SEVEN-LEVELH/WINPUTS VDS) V V V V V V
V I7	Input mode 7 voltage	Tied to DVDD				V
R PU	Pullup resistance	Internal pullup to DVDD				k Ω
R PD						k Ω
OPENDRAIN OUTPUTS	OPENDRAIN OUTPUTS	OPENDRAIN OUTPUTS	OPENDRAIN OUTPUTS	OPENDRAIN OUTPUTS	OPENDRAIN OUTPUTS	OPENDRAIN OUTPUTS
V OL	Output logic lowvoltage			0.1		V
I OZ	Output high impedance leakage	V O = 5 V			2	μA

at TA = -40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

PARAMETER	PARAMETER	TEST CONDITIONS	TYP	MAX	UNIT
MIN GATE DRIVERS (GHx, GLx)	MIN GATE DRIVERS (GHx, GLx)	MIN GATE DRIVERS (GHx, GLx)	MIN GATE DRIVERS (GHx, GLx)	MIN GATE DRIVERS (GHx, GLx)	MIN GATE DRIVERS (GHx, GLx)	MIN GATE DRIVERS (GHx, GLx)	MIN GATE DRIVERS (GHx, GLx)
		V VM = 13 V, I VCP = 0 to 25 mA	11	12.5	V
	V (1)	V VM = 10 , I VCP = 0 to 20mA	9	10	V
	GSH	V VM = 8 V, I VCP = 0 to 15mA	7	8	V
		V VM = 6 V, I VCP = 0 to 10mA	5	6	V
		V VM = 12 V, I VGLS = 0 to 25mA	11	12	V
	V (1)	V VM = 10 V, I VGLS = 0 to 20mA	9	10	V
	GSL	V VM = 8 V, I VGLS = 0 to 15 mA	7	8	V
		V VM = 6 V, I VGLS = 0 to 10 mA	5	6	V
	t DEAD	DEAD_TIME = 00b DEAD_TIME = 01b DEAD_TIME = 10b DEAD_TIME = 11b	50 100 200 400 100		ns ns ns ns ns
	t DRIVE	TDRIVE = 00b TDRIVE = 01b TDRIVE = 10b TDRIVE = 11b	500 1000 2000 4000 4000		ns ns ns ns
	I DRIVEP	IDRIVEP_HS orIDRIVEP_LS = 0000b IDRIVEP_HS orIDRIVEP_LS = 0001b IDRIVEP_HS orIDRIVEP_LS = 0010b IDRIVEP_HS orIDRIVEP_LS = 0011b IDRIVEP_HS orIDRIVEP_LS = 0100b IDRIVEP_HS orIDRIVEP_LS = 0101b IDRIVEP_HS orIDRIVEP_LS = 0110b IDRIVEP_HS orIDRIVEP_LS = 0111b IDRIVEP_HS orIDRIVEP_LS = 1000b IDRIVEP_HS orIDRIVEP_LS = 1001b IDRIVEP_HS orIDRIVEP_LS = 1010b IDRIVEP_HS orIDRIVEP_LS = 1011b IDRIVEP_HS orIDRIVEP_LS = 1100b IDRIVEP_HS orIDRIVEP_LS = 1101b IDRIVEP_HS orIDRIVEP_LS = 1110b IDRIVEP_HS orIDRIVEP_LS = 1111b IDRIVE = Tied to AGND IDRIVE = 18 k Ω ± 5% tied to AGND IDRIVE = 75 k Ω ± 5% tied to AGND Device IDRIVE = Hi-Z IDRIVE = 75 k Ω ± 5%tied to DVDD IDRIVE = 18 k Ω ± 5%tied to DVDD IDRIVE = Tied to DVDD	10 30 60 80 120 140 170 190 260 330 370 440 570 680 820 1000 10 30 60 120 260 570 1000		mA

at TA = -40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

at TA = -40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

	PARAMETER	TEST CONDITIONS	MIN TYP	MAX
I DRIVEN		IDRIVEN_HS orIDRIVEN_LS = 0000b IDRIVEN_HS orIDRIVEN_LS = 0001b IDRIVEN_HS orIDRIVEN_LS = 0010b IDRIVEN_HS orIDRIVEN_LS = 0011b IDRIVEN_HS orIDRIVEN_LS = 0100b IDRIVEN_HS orIDRIVEN_LS = 0101b IDRIVEN_HS orIDRIVEN_LS = 0110b IDRIVEN_HS orIDRIVEN_LS = 0111b IDRIVEN_HS orIDRIVEN_LS = 1000b IDRIVEN_HS orIDRIVEN_LS = 1001b IDRIVEN_HS orIDRIVEN_LS = 1010b	20 60 120 160 240 280 340 380 520 660 740		UNIT
		IDRIVEN_HS orIDRIVEN_LS = 1011b IDRIVEN_HS orIDRIVEN_LS = 1100b IDRIVEN_HS orIDRIVEN_LS = 1101b IDRIVEN_HS orIDRIVEN_LS = 1110b IDRIVEN_HS orIDRIVEN_LS = 1111b IDRIVE = Tied to AGND IDRIVE = 18 k Ω ± 5% tied to AGND IDRIVE = 75 k Ω ± 5% tied to AGND Device IDRIVE = Hi-Z IDRIVE = 75 k Ω ± 5%tied to DVDD IDRIVE = 18 k Ω ± 5%tied to DVDD IDRIVE = Tied to DVDD	880 1140 1360 1640 2000 20 60 120 240 520 1140 2000		mA
I HOLD	Gate holding current	Source current after t DRIVE	10		mA
I HOLD		Sink current after t DRIVE	50		mA
I STRONG	Gate strong pulldown current	GHx to SHx and GLxto PGND	2		A
R OFF	Gate hold off resistor	GHx to SHx and GLxto PGND	150		k Ω
G CSA		CSA_GAIN=00b	4.85 5	5.15	V/V
		CSA_GAIN=01b	9.7 10 20	10.3
		CSA_GAIN=10b	19.4	20.6
		CSA_GAIN=11b	38.8 40	41.2
		GAIN= Tied to AGND Device GAIN= 47 k Ω ± 5%tied to AGND	4.85 5 10 9.7	5.15 10.3
		GAIN= Hi-Z	19.4 20	20.6
		GAIN= Tied to DVDD V O_STEP = 0.5 V, G CSA = 5 V/V	38.8 40 150	41.2
t SET (1)		V O_STEP = 0.5 V, G VSA = 20 V/V V O_STEP = 0.5 V, G CSA = 40 V/V	600 1200		ns
V COM	Common modeinput range	Common modeinput range	-0.15	0.15	V
V DIFF	Differentialmode inputrange	Differentialmode inputrange	-0.3	0.3	V
V OFF	Input offset error	V SP = V SN = 0 V, CAL = 3.3 V,VREF = 3.3 V	-4	4	mV
V DRIFT (1)	Drift offset	V SP = V SN = 0 V	10		μV/°C
V LINEAR	SOxoutput voltagelinearrange	SOxoutput voltagelinearrange	0.25	V VREF - 0.25	V

at TA = -40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

PARAMETER	PARAMETER	PARAMETER	TEST CONDITIONS	MIN	MAX	UNIT
			V SP = V SN = 0 V, CAL = 3.3 V, VREF_DIV	TYP - 0.3		V
V BIAS	SOxoutput voltage bias	SPI Device	= 0b V SP = V SN = 0 V, CAL = 3.3 V, VREF_DIV = 1b	V VREF V VREF / 2 V / 2		V V
		H/W Device	V SP = V SN = 0 V, CAL = 3.3 V	VREF		V
I BIAS	SPx/SNx input biascurrent	SPx/SNx input biascurrent	VREF_DIV = 1b		100	μA
V SLEW (1)	SOxoutput slew rate	SOxoutput slew rate	60-pF load	10		V/μs
I VREF	VREF input current	VREF input current	V VREF = 5 V	2	3	mA
UGB (1)	Unity gain bandwidth	Unity gain bandwidth	60-pF load	1		MHz
PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS	PROTECTION CIRCUITS
			VM falling, UVLOreport	5.4 5.6	5.8	V
V UVLO	VM undervoltage lockout	VM undervoltage lockout	VM rising, UVLOrecovery	5.6 5.8	6	V
V UVLO_HYS	VM undervoltage hysteresis	VM undervoltage hysteresis	Rising to falling threshold	200	mV	V
t UVLO_DEG	VM undervoltage deglitch time	VM undervoltage deglitch time	VM falling, UVLOreport	10	μs	V
V CPUV	Charge pump undervoltage lockout	Charge pump undervoltage lockout	VCP falling,CPUV report	V VM + 2.8	V	V
V	High-side gate clamp	High-side gate clamp	Positive clamping voltage	15 16.5	18	V
GS_CLAMP		SPI Device	Negative clampingvoltage VDS_LVL = 0000b VDS_LVL = 0001b VDS_LVL = 0010b VDS_LVL = 0011b VDS_LVL = 0100b VDS_LVL = 0101b VDS_LVL = 0110b VDS_LVL = 0111b VDS_LVL = 1000b VDS_LVL = 1001b VDS_LVL = 1010b	-0.7 0.06 0.13 0.2 0.26 0.31 0.45 0.53 0.6 0.68 0.75 0.94	V
V VDS_OCP	V DS overcurrent trip voltage	H/W Device	VDS_LVL = 1011b VDS_LVL = 1100b VDS_LVL = 1101b VDS_LVL = 1110b VDS_LVL = 1111b VDS = Tied to AGND VDS = 18 k Ω ± 5%tied to AGND VDS = 75 k Ω ± 5%tied to AGND VDS = Hi-Z VDS = 75 k Ω ± 5%tied to DVDD VDS = 18 k Ω ± 5%tied to DVDD VDS = Tied to DVDD OCP_DEG=00b	1.13 1.3 1.5 1.7 1.88 0.06 0.13 0.26 0.6 1.13 1.88 Disabled 2	V
t OCP_DEG	V DS and V SENSE overcurrent deglitchtime	H/W Device	OCP_DEG=11b	4 6 8 4	μs

at TA = -40°C to +125°C, VVM = 6 to 60 V (unless otherw ise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
		SPI Device	SEN_LVL = 00b SEN_LVL = 01b		0.25 0.5
V SEN_OCP V SENSE trip voltage	overcurrent H/W	Device	SEN_LVL = 10b SEN_LVL = 11b		0.75 1 1		V
t RETRY	Overcurrent retry	SPI Device	TRETRY = 0b		4		ms
time		H/W Device	TRETRY = 1b		50 4		μ s ms
T OTW (1)	Thermal warningtemperature		Die temperature, T J	130	150	165	°C
T OTSD (1)	Thermal shutdown temperature		Die temperature, T J	150	170	185	°C
T HYS (1)	Thermal hysteresis		Die temperature, T J		20		°C
BUCK REGULATOR SUPPLY (VIN)
I nSHDN	Shutdown supply current		V nSHDN = 0 V		1	3	μA
I Q	Operating quiescent current		V VIN = 12 V, no load; not switching		28		μA
V VIN_UVLO	VINundervoltagelockout		VIN Rising			4	V
threshold			VINFalling	3
BUCK REGULATOR SHUTDOWN (nSHDN)
V nSHDN_TH	Rising nSHDNthreshold			1.05	1.25	1.38	V
I nSHDN	Input current		V nSHDN = 2.3 V V nSHDN = 0.9 V		-4.2 -1		μA
I nSHDN_HYS	Hysteresis current				-3		μA
BUCK REGULATOR HIGH-SIDE MOSFET
R DS_ON	MOSFET on resistance		V VIN = 12 V, V CB to V SW = 5.8 V, T A = 25°C		900		m Ω
BUCK REGULATOR VOLTAGE REFERENCE (FB)
V FB	Feedbackvoltage			0.747	0.765	0.782	V
BUCK REGULATOR CURRENT LIMIT
I LIMIT	Peak current limit		V VIN = 12 V, T A = 25°C		1200	1700	mA
BUCK REGULATOR SWITCHING (SW)
f SW	Switching frequency			595	700	805	kHz
D MAX	Maximumdutycycle				96%
BUCK REGULATOR THERMAL SHUTDOWN
T SHDN (1)	Thermal shutdown threshold				170		°C
T HYS (1)	Thermal shutdownhysteresis				10		°C

DRV8320 Absolute Maximum Ratings

at TA = -40°C to +125°C (unless otherw ise noted) (1)

	MIN	MAX	UNIT
GATE DRIVER
Powersupply pin voltage (VM)	-0.3	65	V
Voltage differentialbetween ground pins(AGND, BGND, DGND, PGND)	-0.3	0.3	V
MOSFET drain sense pin voltage (VDRAIN)	-0.3	65	V
Charge pump pin voltage(CPH, VCP)	-0.3	V VM + 13.5	V
Charge pump negative-switching pinvoltage(CPL)	-0.3	V VM	V
Internal logic regulator pinvoltage (DVDD)	-0.3	3.8	V
Digital pin voltage (CAL, ENABLE,GAIN, IDRIVE, INHx, INLx, MODE,nFAULT, nSCS, SCLK, SDI, SDO, VDS)	-0.3	5.75	V
Continuoushigh-side gate drivepinvoltage (GHx)	-5 (2)	V VCP + 0.5	V
Transient 200-nshigh-side gate drive pin voltage (GHx)	-7	V VCP + 0.5	V
High-side gate drive pinvoltage withrespect to SHx(GHx)	-0.3	13.5	V
Continuoushigh-side source sense pin voltage(SHx)	-5 (2)	V VM + 5	V
Transient 200-nshigh-side source sense pin voltage (SHx)	-7	V VM + 7	V
Continuouslow-side gate drivepin voltage (GLx)	-0.5	13.5	V
Gate drive pin source current (GHx, GLx)	Internally limited	Internally limited	A
Gate drive pin sinkcurrent (GHx, GLx)	Internally limited	Internally limited	A
Continuouslow-side source sense pin voltage(SLx)	-1	1	V
Transient 200-nslow-side source sense pin voltage (SLx)	-3	3	V
Continuousinput pinvoltage (SNx, SPx)	-1	1	V
Transient 200-nsinput pin voltage (SNx, SPx)	-3	3	V
Reference input pin voltage(VREF)	-0.3	5.75	V
output pin voltage(SOx)	-0.3	V VREF + 0.3	V
BUCK REGULATOR
Powersupply pin voltage (VIN)	-0.3	65	V
Shutdown control pin voltage (nSHDN)	-0.3	V VIN	V
Voltage feedbackpin voltage (FB)	-0.3	7	V
Bootstrap pin voltagewith respect to SW(CB)	-0.3	7	V
Switching node pinvoltage(SW)	-0.3	V VIN	V
Switching node pinvoltagelessthan 30-nstransients(SW)	-2	V VIN	V
DRV832x
Operating junctiontemperature, T J	-40	150	°C
Storage temperature, T stg	-65	150	°C

DRV8320 Recommended Operating Conditions

at TA = -40°C to +125°C (unless otherw ise noted)

		MIN	MAX	UNIT
GATE DRIVER	GATE DRIVER
V VM	Powersupply voltage (VM)	6	60	V
V I	Input voltage(CAL, ENABLE, GAIN, IDRIVE, INHx, INLx, MODE,nSCS, SCLK, SDI, VDS)	0	5.5	V
f PWM	AppliedPWM signal (INHx, INLx)	0	200 (1)	kHz
I GATE_HS	High-side average gate drivecurrent (GHx)	0	25 (1)	mA
I GATE_LS	Low-side average gate drive current (GLx)	0	25 (1)	mA
I DVDD	External loadcurrent (DVDD)	0	30 (1)	mA
V VREF	Reference voltageinput (VREF)	3	5.5	V
I SO	output current (SOx)	0	5	mA
V OD	Open drain pullupvoltage(nFAULT, SDO)	0	5.5	V
I OD	Open drain output current (nFAULT, SDO)	0	5	mA
BUCK REGULATOR	BUCK REGULATOR
V VIN	Powersupply voltage (VIN)	4	60	V
V nSHDN	Shutdown control input voltage(nSHDN)	0	60	V
DRV832x	DRV832x
T A	Operating ambient temperature	-40	125	°C

DRV8320 Thermal Information

	THERMAL METRIC (1)	DRV832x - RTV (WQFN) - 32 PINS	DRV832x - RHA (VQFN) - 40 PINS	DRV832x - RTA (WQFN) - 40 PINS	DRV832x - RGZ (VQFN) - 48 PINS	UNIT
R θ JA	Junction-to-ambient thermal resistance	32.9	30.1	32.1	26.6	°C/W
R θ JC(top)	Junction-to-case (top) thermal resistance	15.8	16.7	11	13.9	°C/W
R θ JB	Junction-to-board thermal resistance	6.8	9.9	7.1	9.2	°C/W
ψ JT	Junction-to-topcharacterization parameter	0.2	0.5	0.1	0.3	°C/W
ψ JB	Junction-to-board characterizationparameter	6.8	9.9	7.1	9.1	°C/W
R θ JC(bot)	Junction-to-case (bottom) thermal resistance	2.1	2.2	2.1	2	°C/W

DRV8320 Typical Application

The DRV832x family of devices is primarily used in applications for three-phase brushless DC motor control. The design procedures in the Typical Application section highlight how to use and configure the DRV832x family of devices.

DRV8320 Package Information

PLASTIC QUAD FLATPACK - NO LEAD

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
This drawing is subject to change without notice.
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

PLASTIC QUAD FLATPACK - NO LEAD

NOTES: (continued)

This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

PLASTIC QUAD FLATPACK - NO LEAD

NOTES: (continued)

6.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

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7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD

Variants on the same datasheet

These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.

Part Number	Manufacturer	Package
DRV8320R	Texas Instruments	VQFN-40 6x6mm
DRV8323	Texas Instruments	WQFN-40 6x6mm
DRV8323H	Texas Instruments	WQFN (40)
DRV8323HRTAR	Texas Instruments	40-WFQFN Exposed Pad
DRV8323HRTAT	Texas Instruments	WQFN-40
DRV8323R	Texas Instruments	VQFN-48 7x7mm
DRV8323RH	Texas Instruments	VQFN (48)
DRV8323RS	Texas Instruments	WQFN (32)
DRV8323RSRGZR	Texas Instruments	48-VFQFN Exposed Pad
DRV8323S	Texas Instruments	WQFN (40)
DRV8323SRTAR	Texas Instruments	WQFN-40
DRV8323SRTAT	Texas Instruments	WQFN-40
DRV8323XS	Texas Instruments	—

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