CY7C68013A-56PVXCT

Part: CY7C68013A/14A/15A/16A — Infineon Technologies (formerly Cypress)

Type: USB Microcontroller

Description: A low-power USB 2.0 Hi-Speed peripheral controller with an integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor, offering data transfer rates over 53 Mbytes/second and 16 KB of on-chip code/data RAM.

Operating Conditions:

• Supply voltage: 3.3 V (with 5-V tolerant inputs)
• Operating temperature: 0 to +70 °C (Commercial), -40 to +105 °C (Industrial)
• 8051 CPU operation: 48-MHz, 24-MHz, or 12-MHz

Absolute Maximum Ratings:

• Max supply voltage: +4.0 V
• Max output current, per I/O port: 10 mA
• Max output current, all five I/O ports (128-pin and 100-pin packages): 50 mA
• Max storage temperature: +150 °C

Key Specs:

• USB speed: Full speed (12 Mbps), High speed (480 Mbps)
• On-chip RAM: 16 KB
• CPU clock frequency: 48 MHz, 24 MHz, or 12 MHz
• I2C controller speed: 100 kHz or 400 kHz (measured 85 kHz and 300 kHz)
• Suspend current (CY7C68014A/16A): 100 μA (typ)
• Suspend current (CY7C68013A/15A): 300 μA (typ)
• Supply current (Icc): 85 mA (max)
• USART baud rate: 230 KBaud (max)

Features:

• 3.3-V operation with 5-V tolerant inputs
• USB 2.0 USB IF Hi-Speed certified
• Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor
• Fit-, form-, and function-compatible with the FX2
• Ultra-low power
• Four programmable BULK, INTERRUPT, and ISOCHRONOUS endpoints
• 8-bit or 16-bit external data interface
• GPIF™ (general programmable interface)
• Integrated I2C controller
• Four integrated FIFOs
• Available in commercial and industrial temperature grades

Applications:

• Portable video recorder
• MPEG/TV conversion
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Wireless LAN
• MP3 players
• Networking

Package:

• 128-pin TQFP (40 GPIOs)
• 100-pin TQFP (40 GPIOs)
• 56-pin QFN (24 or 26 GPIOs)
• 56-pin SSOP (24 GPIOs)
• 56-pin VFBGA (24 GPIOs)

• ■ 3.3-V operation with 5-V tolerant inputs
• ■ USB 2.0 USB IF Hi-Speed certified (TID # 40460272)
• ■ Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor
• ■ Fit-, form-, and function-compatible with the FX2 ❐ Pin-compatible0
• ❐ Object-code-compatible
• ❐ Functionally compatible (FX2LP is a superset)
• ■ Ultra-low power: I CC no more than 85 mA in any mode ❐ Ideal for bus- and battery-powered applications
• ■ Software: 8051 code runs from: ❐ Internal RAM, which is downloaded through USB ❐ Internal RAM, which is loaded from EEPROM ❐ External memory device (128-pin package)
• ■ 16 KB of on-chip code/data RAM
• Four programmable BULK, INTERRUPT, and
• ■ ISOCHRONOUS endpoints ❐ Buffering options: Double, triple, and quad
• ■ Additional programmable (BULK/INTERRUPT) 64-byte endpoint
• ■ 8-bit or 16-bit external data interface
• ■ Smart media standard ECC generation
• ■ GPIF™ (general programmable interface)
• ❐ Enables direct connection to most parallel interfaces
• ❐ Programmable waveform descriptors and configuration registers to define waveforms
• ❐ Supports multiple ready (RDY) inputs and control (CTL) outputs
• ■ Integrated, industry-standard, enhanced 8051
• ❐ 48-MHz, 24-MHz, or 12-MHz CPU operation
• ❐ Four clocks per instruction cycle
• ❐ Two USARTs
• ❐ Three counter/timers
• ❐ Expanded interrupt system
• ❐ Two data pointers
• ■ Vectored USB interrupts and GPIF/FIFO interrupts
• ■ Separate data buffers for the setup and data portions of a CONTROL transfer
• ■ Integrated I 2 C controller; runs at 100 or 400 kHz [1]
• ■ Four integrated FIFOs
• ❐ Integrated glue logic and FIFOs lower system cost ❐ Automatic conversion to and from 16-bit buses ❐ Master or slave operation Uses external clock or asynchronous strobes
• ❐ ❐ Easy interface to ASIC and DSP ICs
• ■ Available in commercial and industrial temperature grades (all packages except VFBGA)

• ■ Portable video recorder
• ■ MPEG/TV conversion
• ■ DSL modems
• ■ ATA interface
• ■ Memory card readers
• ■ Legacy conversion devices
• ■ Cameras
• ■ Scanners
• ■ Wireless LAN
• ■ MP3 players
• ■ Networking

The 'Reference Designs' section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Visit www.cypress.com for more information.

Figure 6 on page 19 identifies all signals for the five package types. The following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are available in the 128-pin, 100-pin, and 56-pin packages.

The signals on the left edge of the 56-pin package in Figure 6 on page 19 are common to all versions in the FX2LP family with the noted differences between the CY7C68013A/14A and the CY7C68015A/16A.

Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register bits. Port mode is the power on default configuration.

The 100-pin package adds functionality to the 56-pin package by adding these pins:

• ■ PORTC or alternate GPIFADR[7:0] address signals
• ■ PORTE or alternate GPIFADR[8] address signal and seven additional 8051 signals
• ■ Three GPIF Control signals
• ■ Four GPIF Ready signals
• ■ Nine 8051 signals (two USARTs, three timer inputs, INT4, and INT5#)
• ■ BKPT, RD#, WR#.

The 128-pin package adds the 8051 address and data buses plus control signals. Note that two of the required signals, RD# and WR#, are present in the 100-pin version.

In the 100-pin and 128-pin versions, an 8051 control bit can be set to pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC. This feature is enabled by setting the PORTCSTB bit in the CPUCS register.

PORTC Strobe Feature Timings on page 46 displays the timing diagram of the read and write strobing function on accessing PORTC.

• denotes programmable polarity

Figure 9. CY7C68013A/CY7C68014A 56-Pin SSOP Pin Assignment

Table 14. DC Characteristics

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Maximum junction temperature ................................. 125 °C

The following table displays the thermal characteristics of various packages:

Table 13. Thermal Characteristics

The junction temperature j , can be calculated using the following equation: j = P* Ja + a Where,

P = Power

Ja = Junction to ambient temperature ( Jc + Ca )

a = Ambient temperature (70 °C)

The case temperature c , can be calculated using the following equation: c = P* Ca + a where,

P = Power

Ca = Case to ambient temperature

a = Ambient temperature (70 °C)

1. Do not power I/O with the chip power OFF.