Part: CY7C68013A/14A/15A/16A — Infineon Technologies (formerly Cypress)

Type: USB Microcontroller

Description: A low-power USB 2.0 Hi-Speed peripheral controller with an integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor, offering data transfer rates over 53 Mbytes/second and 16 KB of on-chip code/data RAM.

Operating Conditions:

• Supply voltage: 3.3 V (with 5-V tolerant inputs)
• Operating temperature: 0 to +70 °C (Commercial), -40 to +105 °C (Industrial)
• 8051 CPU operation: 48-MHz, 24-MHz, or 12-MHz

Absolute Maximum Ratings:

• Max supply voltage: +4.0 V
• Max output current, per I/O port: 10 mA
• Max output current, all five I/O ports (128-pin and 100-pin packages): 50 mA
• Max storage temperature: +150 °C

Key Specs:

• USB speed: Full speed (12 Mbps), High speed (480 Mbps)
• On-chip RAM: 16 KB
• CPU clock frequency: 48 MHz, 24 MHz, or 12 MHz
• I2C controller speed: 100 kHz or 400 kHz (measured 85 kHz and 300 kHz)
• Suspend current (CY7C68014A/16A): 100 μA (typ)
• Suspend current (CY7C68013A/15A): 300 μA (typ)
• Supply current (Icc): 85 mA (max)
• USART baud rate: 230 KBaud (max)

Features:

• 3.3-V operation with 5-V tolerant inputs
• USB 2.0 USB IF Hi-Speed certified
• Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor
• Fit-, form-, and function-compatible with the FX2
• Ultra-low power
• Four programmable BULK, INTERRUPT, and ISOCHRONOUS endpoints
• 8-bit or 16-bit external data interface
• GPIF™ (general programmable interface)
• Integrated I2C controller
• Four integrated FIFOs
• Available in commercial and industrial temperature grades

Applications:

• Portable video recorder
• MPEG/TV conversion
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Wireless LAN
• MP3 players
• Networking

Package:

• 128-pin TQFP (40 GPIOs)
• 100-pin TQFP (40 GPIOs)
• 56-pin QFN (24 or 26 GPIOs)
• 56-pin SSOP (24 GPIOs)
• 56-pin VFBGA (24 GPIOs)

• ■ 3.3-V operation with 5-V tolerant inputs
• ■ USB 2.0 USB IF Hi-Speed certified (TID # 40460272)
• ■ Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor
• ■ Fit-, form-, and function-compatible with the FX2 ❐ Pin-compatible0
• ❐ Object-code-compatible
• ❐ Functionally compatible (FX2LP is a superset)
• ■ Ultra-low power: I CC no more than 85 mA in any mode ❐ Ideal for bus- and battery-powered applications
• ■ Software: 8051 code runs from: ❐ Internal RAM, which is downloaded through USB ❐ Internal RAM, which is loaded from EEPROM ❐ External memory device (128-pin package)
• ■ 16 KB of on-chip code/data RAM
• Four programmable BULK, INTERRUPT, and
• ■ ISOCHRONOUS endpoints ❐ Buffering options: Double, triple, and quad
• ■ Additional programmable (BULK/INTERRUPT) 64-byte endpoint
• ■ 8-bit or 16-bit external data interface
• ■ Smart media standard ECC generation
• ■ GPIF™ (general programmable interface)
• ❐ Enables direct connection to most parallel interfaces
• ❐ Programmable waveform descriptors and configuration registers to define waveforms
• ❐ Supports multiple ready (RDY) inputs and control (CTL) outputs
• ■ Integrated, industry-standard, enhanced 8051
• ❐ 48-MHz, 24-MHz, or 12-MHz CPU operation
• ❐ Four clocks per instruction cycle
• ❐ Two USARTs
• ❐ Three counter/timers
• ❐ Expanded interrupt system
• ❐ Two data pointers
• ■ Vectored USB interrupts and GPIF/FIFO interrupts
• ■ Separate data buffers for the setup and data portions of a CONTROL transfer
• ■ Integrated I 2 C controller; runs at 100 or 400 kHz [1]
• ■ Four integrated FIFOs
• ❐ Integrated glue logic and FIFOs lower system cost ❐ Automatic conversion to and from 16-bit buses ❐ Master or slave operation Uses external clock or asynchronous strobes
• ❐ ❐ Easy interface to ASIC and DSP ICs
• ■ Available in commercial and industrial temperature grades (all packages except VFBGA)

• ■ Portable video recorder
• ■ MPEG/TV conversion
• ■ DSL modems
• ■ ATA interface
• ■ Memory card readers
• ■ Legacy conversion devices
• ■ Cameras
• ■ Scanners
• ■ Wireless LAN
• ■ MP3 players
• ■ Networking

The 'Reference Designs' section of the Cypress web site provides additional tools for typical USB 2.0 applications. Each reference design comes complete with firmware source and object code, schematics, and documentation. Visit www.cypress.com for more information.

CY7C68013A – 128 TQFP Package Pinout

Pin	Name	Type	Default	Reset	Description
1	CLKOUT	O/Z	12 MHz	Clock Driven	12-, 24- or 48-MHz clock, phase-locked to the 24-MHz input clock. The 8051 defaults to 12-MHz operation. The 8051 may three-state this output by setting CPUCS.1 = 1.
2	VCC	Power	N/A	N/A	Connect to the 3.3-V power source.
3	GND	Ground	N/A	N/A	Ground
4	RDY0 or SLRD	Input	N/A	N/A	Multiplexed pin. RDY0 is a GPIF input signal. SLRD is the input-only read strobe with programmable polarity (FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7..0] or FD[15..0].
5	RDY1 or SLWR	Input	N/A	N/A	Multiplexed pin. RDY1 is a GPIF input signal. SLWR is the input-only write strobe with programmable polarity (FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7..0] or FD[15..0].
6	RDY2	Input	N/A	N/A	RDY2 is a GPIF input signal.
7	RDY3	Input	N/A	N/A	RDY3 is a GPIF input signal.
8	RDY4	Input	N/A	N/A	RDY4 is a GPIF input signal.
9	RDY5	Input	N/A	N/A	RDY5 is a GPIF input signal.
10	AVCC	Power	N/A	N/A	Analog VCC. Connect this pin to the 3.3 V power source. This signal provides power to the analog section of the chip.
11	XTALOUT	Output	N/A	N/A	Crystal Output. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open.
12	XTALIN	Input	N/A	N/A	Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental mode crystal and load capacitor to GND. It is also correct to drive XTALIN with an external 24-MHz square wave derived from another clock source. When driving from an external source, the driving signal should be a 3.3-V square wave.
13	AGND	Ground	N/A	N/A	Analog Ground. Connect to ground with as short a path as possible.
14	NC	N/A	N/A	N/A	No Connect. This pin must be left open.
15	NC	N/A	N/A	N/A	No Connect. This pin must be left open.
16	NC	N/A	N/A	N/A	No Connect. This pin must be left open.
17	AVCC	Power	N/A	N/A	Analog VCC. Connect this pin to the 3.3 V power source. This signal provides power to the analog section of the chip.
18	DPLUS	I/O/Z	Z	Z	USB D+ Signal. Connect to the USB D+ signal.
19	DMINUS	I/O/Z	Z	Z	USB D- Signal. Connect to the USB D- signal.
20	AGND	Ground	N/A	N/A	Analog Ground. Connect to ground with as short a path as possible.
21	A11	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
22	A12	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
23	A13	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
24	A14	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
25	A15	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
26	VCC	Power	N/A	N/A	Connect to the 3.3-V power source.
27	GND	Ground	N/A	N/A	Ground
28	INT4	Input	N/A	N/A	INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin is edge-sensitive, active HIGH.
29	T0	Input	N/A	N/A	T0 is the active HIGH T0 signal for 8051 Timer0, which provides the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use this bit.
30	T1	Input	N/A	N/A	T1 is the active HIGH T1 signal for 8051 Timer1, which provides the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit.
31	T2	Input	N/A	N/A	T2 is the active HIGH T2 input signal to 8051 Timer2, which provides the input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2 does not use this pin.
32	IFCLK	I/O/Z	Z	Z	Interface Clock. Timing reference for data into or out of the slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1) the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced, by setting the bit IFCONFIG.4 = 1.
33	Reserved	Input	N/A	N/A	Reserved. Connect to ground.
34	BKPT	Output	L	L	Breakpoint. This pin goes active (HIGH) when the 8051 address bus matches the BPADDRH/L registers and breakpoints are enabled in the BREAKPT register (BPEN=1). If the BPPULSE bit in the BREAKPT register is HIGH, this signal pulses HIGH for eight 12-/24-/48-MHz clocks. If the BPPULSE bit is LOW, the signal remains HIGH until the 8051 clears the BP bit (by writing 1 to it) in the BREAKPT register.
35	EA	Input	N/A	N/A	External Access. This pin determines where the 8051 fetches code between addresses 0x0000 and 0x3FFF. If EA = 0 the 8051 fetches this code from its internal RAM. If EA = 1 the 8051 fetches this code from external memory.
36	SCL	OD	Z	Z (if booting is done)	Clock for the I²C interface. Connect to VCC with a 2.2-kΩ resistor, even if no I²C peripheral is attached.
37	SDA	OD	Z	Z (if booting is done)	Data for I²C compatible interface. Connect to VCC with a 2.2-kΩ resistor, even if no I²C compatible peripheral is attached.
38	OE#	Output	H	H	OE# is the active LOW output enable for external memory.
39	RDY0 or SLRD	Input	N/A	N/A	Multiplexed pin. RDY0 is a GPIF input signal. SLRD is the input-only read strobe with programmable polarity (FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7..0] or FD[15..0].
40	RD#	Output	H	H	RD# is the active LOW read strobe output for external memory.
41	WR#	Output	H	H	WR# is the active LOW write strobe output for external memory.
42	CS#	Output	H	H	CS# is the active LOW chip select for external memory.
43	VCC	Power	N/A	N/A	Connect to the 3.3-V power source.
44	PB0 or FD[0]	I/O/Z	I (PB0)	Z (PB0)	Multiplexed pin. PB0 is a bidirectional I/O port pin. FD[0] is the bidirectional FIFO/GPIF data bus.
45	PB1 or FD[1]	I/O/Z	I (PB1)	Z (PB1)	Multiplexed pin. PB1 is a bidirectional I/O port pin. FD[1] is the bidirectional FIFO/GPIF data bus.
46	PB2 or FD[2]	I/O/Z	I (PB2)	Z (PB2)	Multiplexed pin. PB2 is a bidirectional I/O port pin. FD[2] is the bidirectional FIFO/GPIF data bus.
47	PB3 or FD[3]	I/O/Z	I (PB3)	Z (PB3)	Multiplexed pin. PB3 is a bidirectional I/O port pin. FD[3] is the bidirectional FIFO/GPIF data bus.
48	VCC	Power	N/A	N/A	Connect to 3.3-V power source.
49	GND	Ground	N/A	N/A	Ground
50	TXD0	Output	H	L	TXD0 is the active HIGH TXD0 output from 8051 UART0, which provides the output clock in sync mode, and the output data in async mode.
51	RXD0	Input	N/A	N/A	RXD0 is the active HIGH RXD0 input to 8051 UART0, which provides data to the UART in all modes.
52	TXD1	Output	H	L	TXD1 is an active HIGH output pin from 8051 UART1, which provides the output clock in sync mode, and the output data in async mode.
53	RXD1	Input	N/A	N/A	RXD1 is an active HIGH input signal for 8051 UART1, which provides data to the UART in all modes.
54	PB4 or FD[4]	I/O/Z	I (PB4)	Z (PB4)	Multiplexed pin. PB4 is a bidirectional I/O port pin. FD[4] is the bidirectional FIFO/GPIF data bus.
55	PB5 or FD[5]	I/O/Z	I (PB5)	Z (PB5)	Multiplexed pin. PB5 is a bidirectional I/O port pin. FD[5] is the bidirectional FIFO/GPIF data bus.
56	PB6 or FD[6]	I/O/Z	I (PB6)	Z (PB6)	Multiplexed pin. PB6 is a bidirectional I/O port pin. FD[6] is the bidirectional FIFO/GPIF data bus.
57	PB7 or FD[7]	I/O/Z	I (PB7)	Z (PB7)	Multiplexed pin. PB7 is a bidirectional I/O port pin. FD[7] is the bidirectional FIFO/GPIF data bus.
58	GND	Ground	N/A	N/A	Ground
59	D0	I/O/Z	Z	Z	8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.
60	D1	I/O/Z	Z	Z	8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.
61	D2	I/O/Z	Z	Z	8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.
62	D3	I/O/Z	Z	Z	8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.
63	D4	I/O/Z	Z	Z	8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.
64	VCC	Power	N/A	N/A	Connect to the 3.3-V power source.
65	GND	Ground	N/A	N/A	Ground
66	CTL4	Output	H	L	CTL4 is a GPIF control output.
67	CTL3	Output	H	L	CTL3 is a GPIF control output.
68	VCC	Power	N/A	N/A	Connect to the 3.3-V power source.
69	CTL0 or FLAGA	O/Z	H	L	Multiplexed pin. CTL0 is a GPIF control output. FLAGA is a programmable slave-FIFO output status flag signal. Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.
70	CTL1 or FLAGB	O/Z	H	L	Multiplexed pin. CTL1 is a GPIF control output. FLAGB is a programmable slave-FIFO output status flag signal. Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
71	CTL2 or FLAGC	O/Z	H	L	Multiplexed pin. CTL2 is a GPIF control output. FLAGC is a programmable slave-FIFO output status flag signal. Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
72	PC0 or GPIFADR0	I/O/Z	I (PC0)	Z (PC0)	Multiplexed pin. PC0 is a bidirectional I/O port pin. GPIFADR0 is a GPIF address output pin.
73	PC1 or GPIFADR1	I/O/Z	I (PC1)	Z (PC1)	Multiplexed pin. PC1 is a bidirectional I/O port pin. GPIFADR1 is a GPIF address output pin.
74	PC2 or GPIFADR2	I/O/Z	I (PC2)	Z (PC2)	Multiplexed pin. PC2 is a bidirectional I/O port pin. GPIFADR2 is a GPIF address output pin.
75	PC3 or GPIFADR3	I/O/Z	I (PC3)	Z (PC3)	Multiplexed pin. PC3 is a bidirectional I/O port pin. GPIFADR3 is a GPIF address output pin.
76	PC4 or GPIFADR4	I/O/Z	I (PC4)	Z (PC4)	Multiplexed pin. PC4 is a bidirectional I/O port pin. GPIFADR4 is a GPIF address output pin.
77	PC5 or GPIFADR5	I/O/Z	I (PC5)	Z (PC5)	Multiplexed pin. PC5 is a bidirectional I/O port pin. GPIFADR5 is a GPIF address output pin.
78	PC6 or GPIFADR6	I/O/Z	I (PC6)	Z (PC6)	Multiplexed pin. PC6 is a bidirectional I/O port pin. GPIFADR6 is a GPIF address output pin.
79	PC7 or GPIFADR7	I/O/Z	I (PC7)	Z (PC7)	Multiplexed pin. PC7 is a bidirectional I/O port pin. GPIFADR7 is a GPIF address output pin.
80	GND	Ground	N/A	N/A	Ground
81	VCC	Power	N/A	N/A	Connect to the 3.3-V power source.
82	PA0 or INT0#	I/O/Z	I (PA0)	Z (PA0)	Multiplexed pin. PA0 is a bidirectional I/O port pin. INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either edge-triggered (IT0 = 1) or level-triggered (IT0 = 0).
83	PA1 or INT1#	I/O/Z	I (PA1)	Z (PA1)	Multiplexed pin. PA1 is a bidirectional I/O port pin. INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either edge-triggered (IT1 = 1) or level-triggered (IT1 = 0).
84	PA2 or SLOE	I/O/Z	I (PA2)	Z (PA2)	Multiplexed pin. PA2 is a bidirectional I/O port pin. SLOE is an input-only output enable with programmable polarity (FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0].
85	PA3 or WU2	I/O/Z	I (PA3)	Z (PA3)	Multiplexed pin. PA3 is a bidirectional I/O port pin. WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in suspend and WU2EN = 1, a transition on this pin starts up the oscillator and interrupts the 8051 to enable it to exit the suspend mode. Asserting this pin inhibits the chip from suspending if WU2EN = 1.
86	D5	I/O/Z	Z	Z	8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.
87	D6	I/O/Z	Z	Z	8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.
88	D7	I/O/Z	Z	Z	8051 Data Bus. This bidirectional bus is high impedance when inactive, input for bus reads, and output for bus writes. The data bus is used for external 8051 program and data memory. The data bus is active only for external bus accesses, and is driven LOW in suspend.
89	PA4 or FIFOADR0	I/O/Z	I (PA4)	Z (PA4)	Multiplexed pin. PA4 is a bidirectional I/O port pin. FIFOADR0 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0].
90	PA5 or FIFOADR1	I/O/Z	I (PA5)	Z (PA5)	Multiplexed pin. PA5 is a bidirectional I/O port pin. FIFOADR1 is an input-only address select for the slave FIFOs connected to FD[7..0] or FD[15..0].
91	PA6 or PKTEND	I/O/Z	I (PA6)	Z (PA6)	Multiplexed pin. PA6 is a bidirectional I/O port pin. PKTEND is an input used to commit the FIFO packet data to the endpoint and whose polarity is programmable via FIFOPINPOLAR.5.
92	PA7 or FLAGD or SLCS#	I/O/Z	I (PA7)	Z (PA7)	Multiplexed pin. PA7 is a bidirectional I/O port pin. FLAGD is a programmable slave-FIFO output status flag signal. SLCS# gates all other slave FIFO enable/strobes.
93	GND	Ground	N/A	N/A	Ground
94	A0	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
95	A1	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
96	A2	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
97	A3	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
98	CTL5	Output	H	L	CTL5 is a GPIF control output.
99	RESET#	Input	N/A	N/A	Active LOW Reset. Resets the entire chip. See section 'Reset and Wakeup' on page 9 for more details.
100	RDY1 or SLWR	Input	N/A	N/A	Multiplexed pin. RDY1 is a GPIF input signal. SLWR is the input-only write strobe with programmable polarity (FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7..0] or FD[15..0].
101	WAKEUP	Input	N/A	N/A	USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscillator and interrupts the 8051 to enable it to exit the suspend mode. Holding WAKEUP asserted inhibits the EZ-USB chip from suspending. This pin has programmable polarity (WAKEUP.4).
102	PD0 or FD[8]	I/O/Z	I (PD0)	Z (PD0)	Multiplexed pin. PD0 is a bidirectional I/O port pin. FD[8] is the bidirectional FIFO/GPIF data bus.
103	PD1 or FD[9]	I/O/Z	I (PD1)	Z (PD1)	Multiplexed pin. PD1 is a bidirectional I/O port pin. FD[9] is the bidirectional FIFO/GPIF data bus.
104	PD2 or FD[10]	I/O/Z	I (PD2)	Z (PD2)	Multiplexed pin. PD2 is a bidirectional I/O port pin. FD[10] is the bidirectional FIFO/GPIF data bus.
105	PD3 or FD[11]	I/O/Z	I (PD3)	Z (PD3)	Multiplexed pin. PD3 is a bidirectional I/O port pin. FD[11] is the bidirectional FIFO/GPIF data bus.
106	INT5#	Input	N/A	N/A	INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin is edge-sensitive, active LOW.
107	VCC	Power	N/A	N/A	Connect to the 3.3-V power source.
108	PE0 or T0OUT	I/O/Z	I (PE0)	Z (PE0)	Multiplexed pin. PE0 is a bidirectional I/O port pin. T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT outputs a high level for one CLKOUT clock cycle when Timer0 overflows. If Timer0 is operated in Mode 3 (two separate timer/counters), T0OUT is active when the low byte timer/counter overflows.
109	PE1 or T1OUT	I/O/Z	I (PE1)	Z (PE1)	Multiplexed pin. PE1 is a bidirectional I/O port pin. T1OUT is an active HIGH signal from 8051 Timer-counter1. T1OUT outputs a high level for one CLKOUT clock cycle when Timer1 overflows. If Timer1 is operated in Mode 3 (two separate timer/counters), T1OUT is active when the low byte timer/counter overflows.
110	PE2 or T2OUT	I/O/Z	I (PE2)	Z (PE2)	Multiplexed pin. PE2 is a bidirectional I/O port pin. T2OUT is the active HIGH output signal from 8051 Timer2. T2OUT is active (HIGH) for one clock cycle when Timer/Counter 2 overflows.
111	PE3 or RXD0OUT	I/O/Z	I (PE3)	Z (PE3)	Multiplexed pin. PE3 is a bidirectional I/O port pin. RXD0OUT is an active HIGH signal from 8051 UART0. If RXD0OUT is selected and UART0 is in Mode 0, this pin provides the output data for UART0 only when it is in sync mode. Otherwise it is a 1.
112	PE4 or RXD1OUT	I/O/Z	I (PE4)	Z (PE4)	Multiplexed pin. PE4 is a bidirectional I/O port pin. RXD1OUT is an active-HIGH output from 8051 UART1. When RXD1OUT is selected and UART1 is in Mode 0, this pin provides the output data for UART1 only when it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.
113	PE5 or INT6	I/O/Z	I (PE5)	Z (PE5)	Multiplexed pin. PE5 is a bidirectional I/O port pin. INT6 is the 8051 INT6 interrupt request input signal. The INT6 pin is edge-sensitive, active HIGH.
114	PE6 or T2EX	I/O/Z	I (PE6)	Z (PE6)	Multiplexed pin. PE6 is a bidirectional I/O port pin. T2EX is an active HIGH input signal to the 8051 Timer2. T2EX reloads timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set in T2CON.
115	PE7 or GPIFADR8	I/O/Z	I (PE7)	Z (PE7)	Multiplexed pin. PE7 is a bidirectional I/O port pin. GPIFADR8 is a GPIF address output pin.
116	GND	Ground	N/A	N/A	Ground
117	A4	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
118	A5	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
119	A6	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
120	A7	Output	L	L	8051 Address Bus. This bus is driven at all times. When the 8051 is addressing internal RAM it reflects the internal address.
121	PD4 or FD[12]	I/O/Z	I (PD4)	Z (PD4)	Multiplexed pin. PD4 is a bidirectional I/O port pin. FD[12] is the bidirectional FIFO/GPIF data bus.
122	PD5 or FD[13]	I/O/Z	I (PD5)	Z (PD5)	Multiplexed pin. PD5 is a bidirectional I/O port pin. FD[13] is the bidirectional FIFO/GPIF data bus.
123	PD6 or FD[

Table 14. DC Characteristics

Parameter	Description	Conditions	Min	Typ	Max	Unit
VCC	Supply voltage	-	3.00	3.3	3.60	V
VCC Ramp Up	0 to 3.3 V	-	200	-	-	s
V IH	Input HIGH voltage	-	2	-	5.25	V
V IL	Input LOW voltage	-	-0.5	-	0.8	V
V IH_X	Crystal input HIGH voltage	-	2	-	5.25	V
V IL_X	Crystal input LOW voltage	-	-0.5	-	0.8	V
I I	Input leakage current	0< V IN < V CC	-	-	±10	A
V OH	Output voltage HIGH	I OUT = 4 mA	2.4	-	-	V
V OL	Output LOW voltage	I OUT = -4 mA	-	-	0.4	V
I OH	Output current HIGH	-	-	-	4	mA
I OL	Output current LOW	-	-	-	4	mA
C IN	Input pin capacitance	Except D+/D-	-	-	10	pF
C IN	Input pin capacitance	D+/D-	-	-	15	pF
I SUSP	Suspend current CY7C68014/CY7C68016	Connected	-	300	380 [27]	A
I SUSP	Suspend current CY7C68014/CY7C68016	Disconnected	-	100	150 [27]	A
I SUSP	Suspend current CY7C68013/CY7C68015	Connected	-	0.5	1.2 [27]	mA
I SUSP	Suspend current CY7C68013/CY7C68015	Disconnected	-	0.3	1.0 [27]	mA
I CC	Supply current	8051 running, connected to USB HS	-	50	85	mA
I CC	Supply current	8051 running, connected to USB FS	-	35	65	mA
T RESET	Reset time after valid power	V CC min = 3.0 V	5.0	-	-	ms
T RESET	Pin reset after powered on	V CC min = 3.0 V	200	-	-	s

Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.

Storage temperature	................................ -65 °C to +150 °C
Ambient temperature with power supplied (Commercial).........................	0 °C to +70 °C
Ambient temperature with power supplied (Industrial)	...................... -40 °C to +105 °C
Supply voltage to ground potential	..............-0.5 V to +4.0 V
DC input voltage to any input pin [26]	...........................5.25 V
DC voltage applied to outputs in high Z state ....................................	-0.5 V to V CC + 0.5 V
Power dissipation	....................................................300mW
Static discharge voltage	...........................................>2000 V
Max output current, per I/O port	.................................10 mA
Max output current, all five I/O ports (128-pin and 100-pin packages)	.................................50 mA

Maximum junction temperature ................................. 125 °C

The following table displays the thermal characteristics of various packages:

Table 13. Thermal Characteristics

Package	Ambient Temperature (°C)	Jc Junction to Case Thermal Resistance (°C/W)	Ja Junction to Ambient Thermal Resistance (°C/W)
56 SSOP	70	24.4	47.7
100 TQFP	70	11.9	45.9
128 TQFP	70	15.5	43.2
56 QFN	70	10.6	25.2
56 VFBGA	70	30.9	58.6

The junction temperature j , can be calculated using the following equation: j = P* Ja + a Where,

P = Power

Ja = Junction to ambient temperature ( Jc + Ca )

a = Ambient temperature (70 °C)

The case temperature c , can be calculated using the following equation: c = P* Ca + a where,

P = Power

Ca = Case to ambient temperature

a = Ambient temperature (70 °C)

1. Do not power I/O with the chip power OFF.