ATMEGA644P-15MZ

Part: ATmega644PA-AU (ATmega164P/324P/644P Automotive family) — Atmel

Type: 8-bit AVR Microcontroller

Description: Low-power 8-bit AVR microcontroller with 64 KB in-system self-programmable Flash, 2 KB EEPROM and 4 KB SRAM, running at up to 16 MHz (16 MIPS) from 2.7–5.5 V.

Operating Conditions:

• Supply voltage: 2.7–5.5 V
• Operating temperature: -40 to +125 °C (automotive grade, identifier Z)
• Speed grades: 0–8 MHz at 2.7–5.5 V; 0–16 MHz at 4.5–5.5 V

Absolute Maximum Ratings:

• Maximum operating voltage: 6.0 V
• Voltage on any pin except RESET: -0.5 V to VCC + 0.5 V
• Voltage on RESET: -0.5 V to +13.0 V
• DC current per I/O pin: 40.0 mA
• DC current on VCC and GND pins: 200.0 mA
• Injection current at VCC = 0 V: ±5.0 mA (maximum per port ±30 mA)
• Injection current at VCC = 5 V: ±1.0 mA
• Storage temperature: -65 to +150 °C
• Operating temperature (abs-max table): -55 to +125 °C

Key Specs:

• Throughput: up to 16 MIPS at 16 MHz
• Flash: 64 KB (10,000 write/erase cycles); EEPROM: 2 KB (100,000 write/erase cycles); SRAM: 4 KB
• Power at 8 MHz, 5 V, 25 °C (ATmega644P): active 8 mA, idle 2.4 mA, power-down 0.8 μA
• ADC: 8-channel, 10-bit, differential mode with selectable gain of 1x, 10x or 200x
• Timers: two 8-bit and one 16-bit Timer/Counter, plus an RTC with a separate oscillator
• PWM: 6 channels
• Communication: 2 USARTs, SPI, byte-oriented two-wire interface (TWI)
• I/O: 32 programmable I/O lines

Features:

• Advanced RISC architecture with 131 instructions, most executing in a single clock cycle
• 32 × 8 general purpose working registers and an on-chip 2-cycle multiplier
• Optional boot code section with independent lock bits and true read-while-write operation
• JTAG (IEEE 1149.1) interface with boundary scan, on-chip debug and programming
• Power-on reset and programmable brown-out detection
• Internal calibrated RC oscillator
• Programmable watchdog timer with separate on-chip oscillator
• On-chip analog comparator
• Pin-change interrupt and wake-up
• Six sleep modes: Idle, ADC noise reduction, power-save, power-down, standby and extended standby
• AEC-Q100 grade 1 qualified, developed to ISO-TS-16949

Applications:

• Automotive embedded control

Package:

• 44-lead TQFP
• 44-pad QFN/MLF

• High-performance, low-power AVR ® 8-bit microcontroller

• Advanced RISC architecture

• 131 powerful Instructions - most single-clock cycle execution

• 32 8 general purpose working registers

• Fully static operation

• Up to 16 MIPS throughput at 16MHz

• On-chip 2-cycle multiplier

• Nonvolatile program and data memories

• 16/32/64Kbytes of in-system self-programmable flash

• Endurance: 10,000 write/erase cycles

• Optional boot code section with independent lock bits

• In-system programming by on-chip boot program

• True read-while-write operation

• 512B/1K/2Kbytes EEPROM

• Endurance: 100,000 write/erase cycles

• 1/2/4Kbytes internal SRAM

• Programming lock for software security

• JTAG (IEEE std. 1149.1 compliant) interface

• Boundary-scan capabilities according to the JTAG standard

• Extensive on-chip debug support

• Programming of flash, EEPROM, fuses, and lock bits through the JTAG interface

• Peripheral features

• Two 8-bit Timer/Counters with separate prescalers and compare modes

• One 16-bit Timer/Counter with separate prescaler, compare mode, and capture mode

• Real time counter with separate oscillator

• Six PWM channels

• 8-channel, 10-bit ADC

• Differential mode with selectable gain at 1x, 10x or 200x (1)

• Byte-oriented two-wire serial interface

• Two programmable serial USART

• Master/slave SPI serial interface

• Programmable watchdog timer with separate on-chip oscillator

• On-chip analog comparator

• Interrupt and wake-up on pin change

• Special microcontroller features

• Power-on reset and programmable brown-out detection

• Internal calibrated RC oscillator

• External and internal interrupt sources

• Six sleep modes: Idle, ADC noise reduction, power-save, power-down, standby and extended standby

• I/O and packages

• 32 programmable I/O lines

• 44-lead TQFP, and 44-pad QFN/MLF

• Operating voltages

• 2.7 to 5.5V for ATmega164P/324P/644P

• Speed grades

• ATmega164P/324P/644P: 0 to 8MHz at 2.7 to 5.5V, 0 to 16MHz at 4.5 to 5.5V

• Power consumption at 8MHz, 5V, 25°C for ATmega644P

• Active mode: 8mA

• Idle mode: 2.4mA

• Power-down mode: 0.8μA

Figure 1-1. Pinout ATmega164P/324P/644P

Note: The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.

Figure 1-1. Pinout ATmega164P/324P/644P

Table 26-1. TA = -40 C to 125 C, V CC = 2.7V to 5.5V(Unless Otherwise Noted)| Parameter | Condition | Symbol | Min. | Typ. | Max. | Unit | |-----------------------------------------------|--------------------|----------|--------|--------|-------------|--------| | Input low voltage, except XTAL1 and reset pin | V CC = 2.7V - 5.5V | V IL | -0.5 | | 0.3V CC(1)| V | | Input low voltage, XTAL1 pin | V CC = 2.7V - 5.5V | V IL1 | -0.5 | | 0.1V CC(1)| V | | Input low voltage, RESET pin | V CC = 2.7V - 5.5V | V IL2 | -0.5 | | 0.3V CC(1)| V |

Notes: 1. 'Max' means the highest value where the pin is guaranteed to be read as low

1. 'Min' means the lowest value where the pin is guaranteed to be read as high
2. Although each I/O port can sink more than the test conditions(20mA at VCC = 5V, 10mA at VCC = 3V)under steady state conditions(non-transient), the following must be observed:
3. 1.)The sum of all IOL, for ports A0-A7, G2, C4-C7 should not exceed 100mA.
4. 2.)The sum of all IOL, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA.
5. 3.)The sum of all IOL, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA.
6. 4.)The sum of all IOL, for ports F0-F7 should not exceed 100mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.

1. Although each I/O port can source more than the test conditions(20mA at VCC = 5V, 10mA at VCC = 3V)under steady state conditions(non-transient), the following must be observed:

• 1)The sum of all IOH, for ports A0-A7, G2, C4-C7 should not exceed 100mA.
• 2)The sum of all IOH, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA.
• 3)The sum of all IOH, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA.
• 4)The sum of all IOH, for ports F0-F7 should not exceed 100mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.

1. Values indicated represent typical data from design simulation.

Table 26-1. TA = -40 C to 125 C, V CC = 2.7V to 5.5V(Unless Otherwise Noted)(Continued)| Parameter | Condition | Symbol | Min. | Typ. | Max. | Unit | |-------------------------------------------------|---------------------------------------------------|------------|-------------|---------|------------|--------| | Input high voltage, except XTAL1 and RESET pins | V CC = 2.7V - 5.5V | V IH | 0.6V CC(2)| | V CC + 0.5 | V | | Input high voltage, XTAL1 pin | V CC = 2.7V - 5.5V | V IH1 | 0.7V CC(2)| | V CC + 0.5 | V | | Input high voltage, RESET pin | V CC = 2.7V - 5.5V | V IH2 | 0.9V CC(2)| | V CC + 0.5 | V | | Output low voltage(3), | I OL = 20 mA, V CC = 5V I OL = 5 mA, V CC = 3V | V OL | | | 0.8 0.5 | V | | Output high voltage(4), | I OH = -20 mA, V CC = 5V I OH = -10 mA, V CC = 3V | V OH | 4.1 2.3 | | | V | | Input leakage Current I/O pin | V CC = 5.5V, pin low(absolute value)| I IL | | | 1 | μA | | Input leakage Current I/O pin | V CC = 5.5V, pin high(absolute value)| I IH | | | 1 | μA | | Reset pull-up resistor | | R RST | 30 | | 60 | k | | I/O pin pull-up resistor | | R PU | 20 | | 50 | k | | Analog comparator Input offset voltage | V CC = 5V V in = V CC /2 | V ACIO | | <10 | 40 | mV | | Analog comparator Input leakage current | V CC = 5V V in = V CC /2 | I ACLK | -50 | | 50 | nA | | Analog comparator Propagation delay | V CC = 2.7V V CC = 4.0V | t ACID(5)| | 750 500 | | ns |

1. 'Min' means the lowest value where the pin is guaranteed to be read as high
2. Although each I/O port can sink more than the test conditions(20mA at VCC = 5V, 10mA at VCC = 3V)under steady state conditions(non-transient), the following must be observed:
3. 1.)The sum of all IOL, for ports A0-A7, G2, C4-C7 should not exceed 100mA.
4. 2.)The sum of all IOL, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA.
5. 3.)The sum of all IOL, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA.
6. 4.)The sum of all IOL, for ports F0-F7 should not exceed 100mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.

1. Although each I/O port can source more than the test conditions(20mA at VCC = 5V, 10mA at VCC = 3V)under steady state conditions(non-transient), the following must be observed:

• 1)The sum of all IOH, for ports A0-A7, G2, C4-C7 should not exceed 100mA.
• 2)The sum of all IOH, for ports C0-C3, G0-G1, D0-D7 should not exceed 100mA.
• 3)The sum of all IOH, for ports G3-G5, B0-B7, E0-E7 should not exceed 100mA.
• 4)The sum of all IOH, for ports F0-F7 should not exceed 100mA.

1. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
2. Values indicated represent typical data from design simulation.

26.2.1 ATmega644P DC Characteristics

Table 26-2. TA = -40 C to 125 C, V CC = 2.7V to 5.5V(Unless Otherwise Noted)| Parameter | Condition | Symbol | Min. | Typ. | Max. | Unit | |--------------------------|-------------------------|----------|--------|--------|--------|--------| | Power supply current(1)| Active 4MHz, V CC = 3V | I CC | | 2.7 | 4.0 | mA | | Power supply current(1)| Active 8MHz, V CC = 5V | I CC | | 9.5 | 12 | mA | | Power supply current(1)| Idle 4MHz, V CC = 3V | I CC | | 0.7 | 1.2 | mA | | Power supply current(1)| Idle 8MHz, V CC = 5V)| I CC | | 3.0 | 4.0 | mA | | Power-down mode | WDT enabled, V CC = 3V | I CC | | 10 | 60 | μA | | Power-down mode | WDT enabled, V CC = 5V | I CC | | 15 | 95 | μA | | Power-down mode | WDT disabled, V CC = 3V | I CC | | 7 | 54 | μA | | Power-down mode | WDT disabled, V CC = 5V | I CC | | 10 | 85 | μA |

Note: 1. All bits set in the Section 8.12.3 'PRR - Power Reduction Register' on page 37.

Stresses beyond those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note: 1. Maximum current per port = ±30mA