Part: ATmega640/V-1280/V-1281/V-2560/V-2561/V — Atmel Type: 8-bit AVR Microcontroller Description: High-performance, low-power 8-bit AVR microcontroller with up to 256KB In-System Self-Programmable Flash, 4KB EEPROM, 8KB SRAM, and up to 86 programmable I/O lines.

Operating Conditions:

• Supply voltage: 1.8V–5.5V
• Operating temperature: -40 to 85 °C
• Max clock frequency: 16 MHz @ 4.5V - 5.5V

Absolute Maximum Ratings:

Key Specs:

• Flash Memory: 64KB/128KB/256KB
• EEPROM: 4KB
• Internal SRAM: 8KB
• CPU Throughput: Up to 16 MIPS at 16MHz
• Data Retention: 20 years at 85°C / 100 years at 25°C
• Active Mode Current: 500μA at 1MHz, 1.8V
• Power-down Mode Current: 0.1μA at 1.8V
• ADC: 8/16-channel, 10-bit

Features:

• Advanced RISC Architecture with 135 powerful instructions
• JTAG (IEEE std. 1149.1 compliant) Interface for debug and programming
• Two 8-bit Timer/Counters and Four 16-bit Timer/Counters
• Four 8-bit PWM Channels and Six/Twelve PWM Channels with programmable resolution
• Two/Four Programmable Serial USARTs
• Master/Slave SPI Serial Interface
• Byte Oriented 2-wire Serial Interface
• Atmel QTouch library support for capacitive touch sensing

Applications:

• Embedded control applications

Package:

• 64-pad QFN/MLF (ATmega1281/2561)
• 64-lead TQFP (ATmega1281/2561)
• 100-lead TQFP (ATmega640/1280/2560)
• 100-ball CBGA (ATmega640/1280/2560)

• High Performance, Low Power Atmel ® AVR ® 8-Bit Microcontroller
• Advanced RISC Architecture
• -135 Powerful Instructions - Most Single Clock Cycle Execution
• -32 × 8 General Purpose Working Registers
• -Fully Static Operation
• -Up to 16 MIPS Throughput at 16MHz
• -On-Chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments
• -64K/128K/256KBytes of In-System Self-Programmable Flash
• -4Kbytes EEPROM
• -8Kbytes Internal SRAM
• -Write/Erase Cycles:10,000 Flash/100,000 EEPROM
• -Data retention: 20 years at 85 C/ 100 years at 25 C
• -Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program

· True Read-While-Write Operation

• -Programming Lock for Software Security

• Endurance: Up to 64Kbytes Optional External Memory Space

• Atmel ® QTouch ® library support

• -Capacitive touch buttons, sliders and wheels

• -QTouch and QMatrix acquisition

• -Up to 64 sense channels

• JTAG (IEEE ® std. 1149.1 compliant) Interface

• -Boundary-scan Capabilities According to the JTAG Standard

• -Extensive On-chip Debug Support

• -Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

• -Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

• -Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode

• -Real Time Counter with Separate Oscillator

• -Four 8-bit PWM Channels

• -Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits (ATmega1281/2561, ATmega640/1280/2560)

• -Output Compare Modulator

• -8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)

• -Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560)

• -Master/Slave SPI Serial Interface

• -Byte Oriented 2-wire Serial Interface

• -Programmable Watchdog Timer with Separate On-chip Oscillator

• -On-chip Analog Comparator

• -Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

• -Power-on Reset and Programmable Brown-out Detection

• -Internal Calibrated Oscillator

• -External and Internal Interrupt Sources

• -Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

• -54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560)

• -64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561)

• -100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560)

• -RoHS/Fully Green

• Temperature Range:

• --40 C to 85 C Industrial

• Ultra-Low Power Consumption

• -Active Mode: 1MHz, 1.8V: 500μA

• -Power-down Mode: 0.1μA at 1.8V

• Speed Grade:

• 0 - 16MHz @ 4.5V - 5.5V

• ATmega640V/ATmega1280V/ATmega1281V:

• 0 - 4MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V

• ATmega2560V/ATmega2561V:

• 0 - 2MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V

• ATmega640/ATmega1280/ATmega1281:

• 0 - 8MHz @ 2.7V - 5.5V, 0 - 16MHz @ 4.5V - 5.5V

• ATmega2560/ATmega2561:

ATMEGA2560V Pinout

Package: TQFP-100

Pin	Name	Type	Description/Alternate Functions
1	PG5	I/O	Port G, Bit 5 (OC0B)
2	PE0	I/O	Port E, Bit 0 (RXD0/PCINT8)
3	PE1	I/O	Port E, Bit 1 (TXD0)
4	PE2	I/O	Port E, Bit 2 (XCK0/AIN0)
5	PE3	I/O	Port E, Bit 3 (OC3A/AIN1)
6	PE4	I/O	Port E, Bit 4 (OC3B/INT4)
7	PE5	I/O	Port E, Bit 5 (OC3C/INT5)
8	PE6	I/O	Port E, Bit 6 (T3/INT6)
9	PE7	I/O	Port E, Bit 7 (CLKO/ICP3/INT7)
10	VCC	P	Power Supply
11	GND	P	Ground
12	PH0	I/O	Port H, Bit 0 (RXD2)
13	PH1	I/O	Port H, Bit 1 (TXD2)
14	PH2	I/O	Port H, Bit 2 (XCK2)
15	PH3	I/O	Port H, Bit 3 (OC4A)
16	PH4	I/O	Port H, Bit 4 (OC4B)
17	PH5	I/O	Port H, Bit 5 (OC4C)
18	PH6	I/O	Port H, Bit 6 (OC2B)
19	PB0	I/O	Port B, Bit 0 (SS/PCINT0)
20	PB1	I/O	Port B, Bit 1 (SCK/PCINT1)
21	PB2	I/O	Port B, Bit 2 (MOSI/PCINT2)
22	PB3	I/O	Port B, Bit 3 (MISO/PCINT3)
23	PB4	I/O	Port B, Bit 4 (OC2A/PCINT4)
24	PB5	I/O	Port B, Bit 5 (OC1A/PCINT5)
25	PB6	I/O	Port B, Bit 6 (OC1B/PCINT6)
26	PB7	I/O	Port B, Bit 7 (OC0A/OC1C/PCINT7)
27	PH7	I/O	Port H, Bit 7 (T4/PCINT16)
28	PG3	I/O	Port G, Bit 3 (TOSC2/PCINT4)
29	PG4	I/O	Port G, Bit 4 (TOSC1/PCINT3)
30	RESET	I	Reset (active low)
31	VCC	P	Power Supply
32	GND	P	Ground
33	XTAL2	I	Crystal Oscillator Pin 2
34	XTAL1	I	Crystal Oscillator Pin 1
35	PL0	I/O	Port L, Bit 0 (ICP4)
36	PL1	I/O	Port L, Bit 1 (ICP5)
37	PL2	I/O	Port L, Bit 2 (T5)
38	PL3	I/O	Port L, Bit 3 (OC5A)
39	PL4	I/O	Port L, Bit 4 (OC5B)
40	PL5	I/O	Port L, Bit 5 (OC5C)
41	PL6	I/O	Port L, Bit 6 (PCINT15)
42	PL7	I/O	Port L, Bit 7 (PCINT14)
43	PD0	I/O	Port D, Bit 0 (SCL/INT0)
44	PD1	I/O	Port D, Bit 1 (SDA/INT1)
45	PD2	I/O	Port D, Bit 2 (RXD1/INT2)
46	PD3	I/O	Port D, Bit 3 (TXD1/INT3)
47	PD4	I/O	Port D, Bit 4 (ICP1)
48	PD5	I/O	Port D, Bit 5 (XCK1)
49	PD6	I/O	Port D, Bit 6 (T1)
50	PD7	I/O	Port D, Bit 7 (T0)
51	PG0	I/O	Port G, Bit 0 (WR)
52	PG1	I/O	Port G, Bit 1 (RD)
53	PC0	I/O	Port C, Bit 0 (A8)
54	PC1	I/O	Port C, Bit 1 (A9)
55	PC2	I/O	Port C, Bit 2 (A10)
56	PC3	I/O	Port C, Bit 3 (A11)
57	PC4	I/O	Port C, Bit 4 (A12)
58	PC5	I/O	Port C, Bit 5 (A13)
59	PC6	I/O	Port C, Bit 6 (A14)
60	PC7	I/O	Port C, Bit 7 (A15)
61	VCC	P	Power Supply
62	GND	P	Ground
63	PJ0	I/O	Port J, Bit 0 (RXD3/PCINT9)
64	PJ1	I/O	Port J, Bit 1 (TXD3/PCINT10)
65	PJ2	I/O	Port J, Bit 2 (XCK3/PCINT11)
66	PJ3	I/O	Port J, Bit 3 (PCINT12)
67	PJ4	I/O	Port J, Bit 4 (PCINT13)
68	PJ5	I/O	Port J, Bit 5 (PCINT14)
69	PJ6	I/O	Port J, Bit 6 (PCINT15)
70	PG2	I/O	Port G, Bit 2 (ALE)
71	PA7	I/O	Port A, Bit 7 (AD7)
72	PA6	I/O	Port A, Bit 6 (AD6)
73	PA5	I/O	Port A, Bit 5 (AD5)
74	PA4	I/O	Port A, Bit 4 (AD4)
75	PA3	I/O	Port A, Bit 3 (AD3)
76	PA2	I/O	Port A, Bit 2 (AD2)
77	PA1	I/O	Port A, Bit 1 (AD1)
78	PA0	I/O	Port A, Bit 0 (AD0)
79	PJ7	I/O	Port J, Bit 7 (PCINT16)
80	VCC	P	Power Supply
81	GND	P	Ground
82	PK7	I/O	Port K, Bit 7 (PCINT23)
83	PK6	I/O	Port K, Bit 6 (PCINT22)
84	PK5	I/O	Port K, Bit 5 (PCINT21)
85	PK4	I/O	Port K, Bit 4 (PCINT20)
86	PK3	I/O	Port K, Bit 3 (PCINT19)
87	PK2	I/O	Port K, Bit 2 (PCINT18)
88	PK1	I/O	Port K, Bit 1 (PCINT17)
89	PK0	I/O	Port K, Bit 0 (PCINT16)
90	PF7	I/O	Port F, Bit 7 (ADC7)
91	PF6	I/O	Port F, Bit 6 (ADC6)
92	PF5	I/O	Port F, Bit 5 (ADC5)
93	PF4	I/O	Port F, Bit 4 (ADC4)
94	PF3	I/O	Port F, Bit 3 (ADC3)
95	PF2	I/O	Port F, Bit 2 (ADC2)
96	PF1	I/O	Port F, Bit 1 (ADC1)
97	PF0	I/O	Port F, Bit 0 (ADC0)
98	AREF	I	Analog Reference
99	GND	P	Ground
100	AVCC	P	Analog Power Supply

Notes

• ATMEGA2560V is a 100-pin TQFP package variant of the ATmega2560 microcontroller.
• Pin numbers extracted from the TQFP pinout diagram (Figure 1-1) in the datasheet.
• Port A (PA0–PA7) serves as the lower 8 bits of the external address bus (AD0–AD7) when external memory is used.
• Port C (PC0–PC7) serves as the upper 8 bits of the external address bus (A8–A15) when external memory is used.
• Port G provides control signals: PG0 (WR), PG1 (RD), PG2 (ALE).
• Multiple VCC and GND pins must all be connected for proper operation.
• AREF and AVCC are separate analog supply pins and should be properly decoupled.