AT32F435CGT7

Part: AT32F435CGT7 — Artery (AT32F435/437 series)

Type: ARM Cortex-M4F 32-bit MCU with FPU

Description: 288 MHz ARM Cortex-M4F MCU+FPU with 1024 KB Flash (AT32F435CGT7 variant), 384 to 512 KB SRAM, dual QSPI, SDRAM-capable XMC, dual OTGFS, 3 ADCs and 18 timers.

Operating Conditions:

• Supply voltage: 2.6–3.6 V application supply
• Operating temperature: -40 to 105 °C
• Maximum CPU frequency: 288 MHz

Key Specs:

• Core: Cortex-M4F with FPU, MPU, DSP instructions, single-cycle multiply, hardware divide
• Flash: 1024 KB for the AT32F435CGT7 (family range 256 to 4032 KB), with sLib secure library area
• SRAM: 384 to 512 KB (family)
• ADC: 3 × 12-bit, 5.33 MSPS, up to 24 channels, hardware oversampling up to equivalent 16-bit resolution
• DAC: 2 × 12-bit
• HICK internal 48 MHz oscillator: ±1% at TA = 25 °C, ±2.5% at TA = -40 to +105 °C
• Crystal oscillator: 4 to 25 MHz (HEXT); 32.768 kHz (LEXT)
• GPIO: up to 116 fast I/Os, almost 5 V-tolerant
• DMA: 2 × general-purpose DMAs and 1 × EDMA, 22 channels in total

Features:

• External memory controller (XMC) with 16-bit data bus supporting CF, SRAM, PSRAM, NOR, NAND and SDRAM
• Up to 2 × QSPI interfaces with memory mapping mode
• LCD parallel interface (8080/6800 modes)
• Power control with POR/LVR and PVM; Sleep, Deepsleep and Standby modes
• VBAT supply for LEXT, ERTC and 20 × 32-bit battery power registers
• Up to 18 timers (13 × 16-bit, 2 × 32-bit), 2 watchdog timers, SysTick
• Up to 3 × I²C, 4 × USART and 4 × UART, 4 × SPI (36 Mbit/s, I²S multiplexed), 2 × CAN 2.0B, 2 × OTG FS (crystal-less), 2 × SDIO
• Infrared transmitter (IRTMR)
• 8 to 14-bit DVP camera interface
• CRC unit, 96-bit UID
• SWD and JTAG debug
• 10/100M Ethernet MAC (AT32F437 only)

Applications:

Package:

• LQFP144 20 × 20 mm
• LQFP100 14 × 14 mm
• LQFP64 10 × 10 mm
• LQFP48 7 × 7 mm
• QFN48 6 × 6 mm

• Three power domains: VDD/VDDA domain, 1.2 V domain and battery powered domain
• Three types of power saving modes: Sleep mode, Deepsleep mode, and Standby mode
• Internal voltage regulator supplies 1.2 V voltage source for the core domain
• Power voltage detector is provided to issue an interrupt when the supply voltage is lower or higher than a programmed threshold
• The battery powered domain is powered by VBAT when VDD is powered off
• VDD/VDDA applies separated digital and analog module to reduce noise on external power

• VDDA: Analog supply, ADC analog supply
• VSSA: Analog supply ground, ADC analog supply ground
• VREF+: Analog reference positive, high/positive reference voltage for the ADC
• VREF-: Analog reference negative, low/negative reference voltage for the ADC
• ADCx_IN: Analog input signal channels

Refer to the Datasheet for more information about the input pin connections and voltage ranges.