ADRV9009-W/PCBZ

Part: ADRV9009BBCZ — Analog Devices

Type: Integrated Dual RF Transceiver (Transmitter, Receiver, and Observation Receiver)

Description: Dual-transmitter, dual-receiver RF agile transceiver with a shared observation receiver, 75 MHz to 6000 MHz tuning range, 200 MHz maximum receiver bandwidth, 450 MHz maximum transmitter synthesis and observation receiver bandwidth, and a JESD204B interface at up to 12.288 Gbps.

Operating Conditions:

• Core supplies: VDDA1P3 = 1.3 V, VDDD1P3_DIG = 1.3 V, VDDA1P8_TX = 1.8 V (specification test conditions)
• Center frequency (Tx and ORx): 75 MHz to 6000 MHz
• Electrical characteristics are specified over the full junction temperature (TJ) operating range; the range itself is not given in the provided text

Absolute Maximum Ratings:

• VDDA1P3 and VDDD1P3_DIG to VSS: -0.3 V to +1.4 V
• VDDA_3P3 to VSSA: -0.3 V to +3.9 V
• VDDA1P8_TX to VSSA: -0.3 V to +2.0 V
• VDD_INTERFACE to VSSA: -0.3 V to +3.0 V
• Input current to any pin except supplies: ±10 mA
• Maximum input power into RF port: 23 dBm (peak)
• Maximum junction temperature (TJ): 110 °C
• Storage temperature: -65 °C to +150 °C

Key Specs:

• Transmitter center frequency: 75 to 6000 MHz; synthesis bandwidth up to 450 MHz; large signal bandwidth up to 200 MHz
• Transmitter attenuation range: 0 to 32 dB in 0.05 dB steps
• Transmitter maximum output power (0 dBFS CW, 50 Ω load): 9 dBm (75–600 MHz), 7 dBm (600–3000 MHz), 6 dBm (3000–4800 MHz), 4.5 dBm (4800–6000 MHz)
• Transmitter OIP3: 29 dBm (75–600 MHz), 27 dBm (600–4000 MHz), 23 dBm (4000–6000 MHz)
• Transmitter ACLR (20 MHz LTE at -12 dBFS): -67 dB (75–2800 MHz), -64 dB (2800–4800 MHz), -60 dB (4800–6000 MHz)
• Transmitter EVM (3GPP): 0.5% (75 MHz LO), 0.7% (1900 MHz LO), 0.7% (3800 MHz LO), 1.1% (5900 MHz LO)
• Transmitter output impedance: 50 Ω differential
• Observation receiver gain range: 30 dB

Features:

• Dual transmitters, dual receivers, and dual-input shared observation receiver
• Maximum receiver bandwidth 200 MHz
• Maximum tunable transmitter synthesis bandwidth 450 MHz
• Maximum observation receiver bandwidth 450 MHz
• Fully integrated fractional-N RF synthesizers and clock synthesizer
• Multichip phase synchronization for RF LO and baseband clocks
• JESD204B datapath interface, up to 12.288 Gbps lane rates
• Automatic and manual gain control, DC offset correction, and quadrature error correction
• Integrated ADCs, DACs, and GPIOs for PA and RF front-end control
• 4-wire SPI control and comprehensive power-down modes

Applications:

• 3G, 4G, and 5G TDD macrocell base stations
• TDD active antenna systems
• Massive MIMO
• Phased array radar
• Electronic warfare
• Military communications
• Portable test equipment

Package:

• 196-ball CSP_BGA, 12 mm × 12 mm

Dual transmitters Dual receivers Dual input shared observation receiver Maximum receiver bandwidth: 200 MHz

Maximum tunable transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz

3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

Table 3.

• 1 VDDA1P3 refers to all analog 1.3 V supplies.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

The ADRV9009 is a high power device that can dissipate over 3 W depending on the user application and configuration. Because of the power dissipation, the ADRV9009 uses an exposed die package to provide the customer with the most effective method of controlling the die temperature. The exposed die allows cooling of the die directly. Figure 5 shows the profile view of the device mounted to a user printed circuit board (PCB) and a heat sink (typically the aluminum case) to keep the junction (exposed die) below the maximum TJ detailed in Table 3. The device is designed for a lifetime of 10 years when operating at the maximum TJ.