ADRV9009BBCZ-REEL
The ADRV9009BBCZ-REEL is an electronic component from Analog Devices Inc.. View the full ADRV9009BBCZ-REEL datasheet below including absolute maximum ratings.
Manufacturer
Analog Devices Inc.
Category
RF / WirelessOverview
Part: ADRV9009 — Analog Devices
Type: Highly Integrated RF Agile Transceiver
Description: A highly integrated RF agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions, delivering high performance and low power for 3G, 4G, and 5G macro cell TDD base station applications.
Operating Conditions:
- Supply voltage: 1.3 V (VDDA1P3, VDDD1P3_DIG), 1.8 V (VDDA1P8_TX)
- LO frequency: 1800 MHz (unless otherwise noted)
- Receiver bandwidth: 200 MHz
- Transmitter synthesis bandwidth: 450 MHz
- Observation receiver bandwidth: 450 MHz
Absolute Maximum Ratings:
- Max supply voltage (VDDA1P3, VDDD1P3_DIG): 1.4 V
- Max supply voltage (VDD_INTERFACE): 3.0 V
- Max supply voltage (VDDA_3P3): 3.9 V
- Max supply voltage (VDDA1P8_TX): 2.0 V
- Max input current to any pin except supplies: ±10 mA
- Max input power into RF Port: 23 dBm (peak)
- Max junction temperature: 110 °C
Key Specs:
- Transmitter Center Frequency: 75 to 6000 MHz
- Transmitter Synthesis Bandwidth: 450 MHz
- Transmitter Attenuation Power Control Range: 0 to 32 dB
- Transmitter Attenuation Power Control Resolution: 0.05 dB
- Adjacent Channel Leakage Ratio (ACLR) LTE: -67 dB (75 MHz < f ≤ 2800 MHz)
- In Band Noise Floor: -147 dBm/Hz (75 MHz < f ≤ 600 MHz, 0 dB attenuation)
- Image Rejection Within Large Signal Bandwidth: 70 dB (75 MHz < f ≤ 600 MHz, QEC active)
- Maximum Output Power: 9 dBm (75 MHz < f ≤ 600 MHz, 0 dBFS, CW tone into 50Ω load, 0 dB attenuation)
- Observation Receiver Center Frequency: 75 to 6000 MHz
- Observation Receiver Gain Range: 30 dB
Features:
- Dual transmitters
- Dual receivers
- Dual input shared observation receiver
- Maximum receiver bandwidth: 200 MHz
- Maximum tunable transmitter synthesis bandwidth: 450 MHz
- Maximum observation receiver bandwidth: 450 MHz
- Fully integrated fractional-N RF synthesizers
- Fully integrated clock synthesizer
- Multichip phase synchronization for RF LO and baseband clocks
- JESD204B datapath interface
- Tuning range (center frequency): 75 MHz to 6000 MHz
Applications:
- 3G, 4G, and 5G TDD macrocell base stations
- TDD active antenna systems
- Massive multiple input, multiple output (MIMO)
- Phased array radar
- Electronic warfare
- Military communications
- Portable test equipment
Package:
- 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA)
Features
Dual transmitters Dual receivers Dual input shared observation receiver Maximum receiver bandwidth: 200 MHz
Maximum tunable transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz
Applications
3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment
Pin Configuration
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| A VSSA | ORX2_IN+ | ORX2_IN- | VSSA | RX2_IN+ | RX2_IN- | VSSA | VSSA | RX1_IN+ | RX1_IN- | VSSA | ORX1_IN+ | ORX1_IN- | VSSA |
| B VDDA1P3_ RX_RF | VSSA | VSSA | VSSA | VSSA | VSSA | RF_EXT_ LO_I/O- | RF_EXT_ LO_I/O+ | VSSA | VSSA | VSSA | VSSA | VSSA | VSSA |
| C GPIO_3P3_0 | GPIO_3P3_3 | VDDA1P3_ RX_TX | VSSA | VDDA1P3_ RF_VCO_LDO | VDDA1P3_ RF_VCO_LDO | VDDA1P1_ RF_VCO | VDDA1P3_ RF_LO | VSSA | VDDA1P3_ AUX_VCO_ LDO | VSSA | VDDA_3P3 | GPIO_3P3_9 | RBIAS |
| D GPIO_3P3_1 | GPIO_3P3_4 | VSSA | VSSA | VSSA | VSSA | VSSA | VSSA | VSSA | VDDA1P1_ AUX_VCO | VSSA | VSSA | GPIO_3P3_8 | GPIO_3P3_10 |
| E GPIO_3P3_2 | GPIO_3P3_5 | GPIO_3P3_6 | VDDA1P8_BB | VDDA1P3_BB | VSSA | REF_CLK_IN+ | REF_CLK_IN- | VSSA | AUX_SYNTH_ OUT | AUXADC_3 | VDDA1P8_TX | GPIO_3P3_7 | GPIO_3P3_11 |
| F VSSA | VSSA | AUXADC_0 | AUXADC_1 | VSSA | VSSA | VSSA | VSSA | VSSA | VSSA | AUXADC_2 | VSSA | VSSA | VSSA |
| G VSSA | VSSA | VSSA | VSSA | VDDA1P3_ CLOCK_ SYNTH | VSSA | VDDA1P3_ RF_SYNTH | VDDA1P3_ AUX_SYNTH | RF_SYNTH_ VTUNE | VSSA | VSSA | VSSA | VSSA | VSSA |
| H TX2_OUT- | VSSA | VSSA | VSSA | VSSA | VSSA | VSSA | VSSA | VSSA | VSSA | GPIO_12 | GPIO_11 | VSSA | TX1_OUT+ |
| J TX2_OUT+ | VSSA | GPIO_18 | RESET | GP_ INTERRUPT | TEST | GPIO_2 | GPIO_1 | SDIO | SDO | GPIO_13 | GPIO_10 | VSSA | TX1_OUT- |
| K VSSA | VSSA | SYSREF_IN+ | SYSREF_IN- | GPIO_5 | GPIO_4 | GPIO_3 | GPIO_0 | SCLK | CS | GPIO_14 | GPIO_9 | VSSA | VSSA |
| L VSSA | VSSA | SYNCIN1- | SYNCIN1+ | GPIO_6 | GPIO_7 | VSSD | VDDD1P3_ DIG | VDDD1P3_ DIG | VSSD | GPIO_15 | GPIO_8 | SYNCOUT1- | SYNCOUT1+ |
| M VDDA1P1_ CLOCK_VCO | VSSA | SYNCIN0- | SYNCIN0+ | RX1_ENABLE | TX1_ENABLE | RX2_ENABLE | TX2_ENABLE | VSSA | GPIO_17 | GPIO_16 | VDD_ INTERFACE | SYNCOUT0- | SYNCOUT0+ |
| N VDDA1P3_ CLOCK_ VCO_LDO | VSSA | SERDOUT3- | SERDOUT3+ | SERDOUT2- | SERDOUT2+ | VSSA | VDDA1P3_ SER | VDDA1P3_ DES | SERDIN1- | SERDIN1+ | SERDIN0- | SERDIN0+ | VSSA |
| P AUX_SYNTH_ VTUNE | VSSA | VSSA | SERDOUT1- | SERDOUT1+ | SERDOUT0- | SERDOUT0+ | VDDA1P3_ SER | VDDA1P3_ DES | VSSA | SERDIN3- | SERDIN3+ | SERDIN2- | SERDIN2+ |
Absolute Maximum Ratings
Table 3.
| Parameter | Rating |
|---|---|
| VDDA1P3 1 toVSSA VDDD1P3_DIG | -0.3V to +1.4V -0.3V to +1.4V |
| toVSSD | |
| VDD_INTERFACE toVSSA | -0.3V to +3.0V |
| VDDA_3P3 toVSSA | -0.3V to +3.9V |
| VDDA1P8_TX toVSSA | -0.3V to +2.0V |
| VDD_INTERFACE Logic Inputs and Outputs toVSSD | -0.3VtoVDD_ INTERFACE+ 0.3V |
| JESD204B Logic Outputs toVSSA | -0.3V to VDDA1P3_SER |
| JESD204B Logic Inputs toVSSA | -0.3V to VDDA1P3_DES +0.3V |
| Input Current to any Pin Except Supplies | ±10mA |
| Maximum Input Power into RF Port | 23dBm (peak) |
| MaximumTransmitter Voltage StandingWave Ratio (VSWR) | 3:1 |
| MaximumT J | 110°C |
| Storage Temperature Range | -65°C to +150°C |
- 1 VDDA1P3 refers to all analog 1.3 V supplies.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
Thermal Information
The ADRV9009 is a high power device that can dissipate over 3 W depending on the user application and configuration. Because of the power dissipation, the ADRV9009 uses an exposed die package to provide the customer with the most effective method of controlling the die temperature. The exposed die allows cooling of the die directly. Figure 5 shows the profile view of the device mounted to a user printed circuit board (PCB) and a heat sink (typically the aluminum case) to keep the junction (exposed die) below the maximum TJ detailed in Table 3. The device is designed for a lifetime of 10 years when operating at the maximum TJ.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| ADRV9009 | Analog Devices Inc. | — |
| ADRV9009-W/PCBZ | Analog Devices Inc. | 196-ball CSP_BGA (12 mm x |
| ADRV9009BBCZ | Analog Devices Inc. | 196-LFBGA, CSPBGA |
Get structured datasheet data via API
Get started free