AD5065BRUZ-REEL7

Part: AD5065BRUZ (AD5025/AD5045/AD5065 family) — Analog Devices

Type: Dual 16-bit Buffered Voltage-Output DAC (nano DAC), SPI interface

Description: Dual 16-bit (AD5065; 14-bit AD5045, 12-bit AD5025) voltage-output DAC with ±1 LSB INL (B grade, TA = -40 to +105 °C), individual reference pins, 4.5–5.5 V supply and 50 MHz SPI interface in a 14-lead TSSOP.

Operating Conditions:

• Supply voltage: 4.5–5.5 V
• Operating temperature: -40 to +125 °C
• Reference input range: 2.2 V to VDD
• SCLK up to 50 MHz

Absolute Maximum Ratings:

• VDD to GND: -0.3 V to +7 V
• Digital input, VOUT and VREF pins to GND: -0.3 V to VDD + 0.3 V
• Max junction temperature: 150 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• Resolution (AD5065): 16 bits
• Relative accuracy (AD5065 B grade): ±1 LSB max (TA = -40 to +105 °C); ±2 LSB max (to +125 °C)
• DNL: ±1 LSB max
• Total unadjusted error: ±2.5 mV max (VREF = 2.5 V, VDD = 5.5 V)
• Offset error: ±1.8 mV max; gain error: ±0.05 %FSR max
• Settling time: 5.8 μs typ, 8 μs max (¼ to ¾ scale to ±1 LSB, RL = 5 kΩ, single channel)
• Slew rate: 1.5 V/μs typ
• IDD normal mode: 2.2 mA typ, 2.7 mA max
• IDD power-down: 0.4 μA typ, 2 μA max (to +105 °C), 30 μA max (to +125 °C)
• Output noise: 6 μV p-p (0.1–10 Hz); noise density 64 nV/√Hz at 1 kHz
• Short-circuit current: 60 mA typ

Features:

• Rail-to-rail output; individual voltage reference pins per channel
• Power-on reset to zero scale or midscale
• Three power-down functions, per-channel power-down, hardware power-down lockout (PDL)
• Low glitch on power-up
• Hardware LDAC with software LDAC override
• CLR function to programmable code (zero, midscale, full scale)
• SDO daisy-chaining option
• 3-wire Schmitt trigger serial interface, compatible with SPI, QSPI, MICROWIRE, DSP

Applications:

• Process controls
• Data acquisition systems
• Portable battery-powered instruments
• Digital gain and offset adjustment
• Programmable voltage and current sources
• Programmable attenuators

Package:

• 14-lead TSSOP

Low power dual 12-/14-/16-bit DAC, ±1 LSB INL Individual voltage reference pins Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale Power down to 400 nA @ 5 V 3 power-down functions Per channel power-down Low glitch upon power-up Hardware power-down lockout capability Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option

14-lead TSSOP

Process controls Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

Figure 5. Pin Configuration

VDD = 4.5 V to 5.5 V , RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD. All specifications TMIN to TMAX, unless otherwise noted.