AD5065ARUZ

Dual 16-bit Voltage Output DAC

The AD5065ARUZ is a dual 16-bit voltage output dac from Analog Devices. View the full AD5065ARUZ datasheet below including key specifications, electrical characteristics.

AD5065ARUZ shares its datasheet with AD5065, whose page lists every part number it covers.

Official AD5065ARUZ datasheet (PDF) — the source this page was extracted from.

Manufacturer

Analog Devices

AD5065ARUZ Key Specifications

Parameter	Value
Package	14-lead TSSOP (RU-14)
Channels	2
Gain Error	±0.05 %FSR max
Resolution	16 bits
Offset Error	±1.8 mV max
Supply Voltage	4.5V to 5.5V
Power-Down Current	400 nA typ @ 5V
Output Voltage Range	0 to VDD
Short-Circuit Current	60 mA
Serial Interface Clock	up to 50 MHz (SPI/QSPI/MICROWIRE/DSP)
Total Unadjusted Error	±2.5 mV max
Reference Voltage Range	2.5V to VDD
Differential Nonlinearity	±1 LSB max
Operating Temperature Range	-40°C to +125°C
Relative Accuracy (INL), A Grade	±4 LSB max

AD5065ARUZ Overview

Part: AD5065BRUZ (AD5025/AD5045/AD5065 family) — Analog Devices

Type: Dual 16-bit Buffered Voltage-Output DAC (nano DAC), SPI interface

Description: Dual 16-bit (AD5065; 14-bit AD5045, 12-bit AD5025) voltage-output DAC with ±1 LSB INL (B grade, TA = -40 to +105 °C), individual reference pins, 4.5–5.5 V supply and 50 MHz SPI interface in a 14-lead TSSOP.

Operating Conditions:

Supply voltage: 4.5–5.5 V
Operating temperature: -40 to +125 °C
Reference input range: 2.2 V to VDD
SCLK up to 50 MHz

Absolute Maximum Ratings:

VDD to GND: -0.3 V to +7 V
Digital input, VOUT and VREF pins to GND: -0.3 V to VDD + 0.3 V
Max junction temperature: 150 °C
Storage temperature: -65 to +150 °C

Key Specs:

Resolution (AD5065): 16 bits
Relative accuracy (AD5065 B grade): ±1 LSB max (TA = -40 to +105 °C); ±2 LSB max (to +125 °C)
DNL: ±1 LSB max
Total unadjusted error: ±2.5 mV max (VREF = 2.5 V, VDD = 5.5 V)
Offset error: ±1.8 mV max; gain error: ±0.05 %FSR max
Settling time: 5.8 μs typ, 8 μs max (¼ to ¾ scale to ±1 LSB, RL = 5 kΩ, single channel)
Slew rate: 1.5 V/μs typ
IDD normal mode: 2.2 mA typ, 2.7 mA max
IDD power-down: 0.4 μA typ, 2 μA max (to +105 °C), 30 μA max (to +125 °C)
Output noise: 6 μV p-p (0.1–10 Hz); noise density 64 nV/√Hz at 1 kHz
Short-circuit current: 60 mA typ

Features:

Rail-to-rail output; individual voltage reference pins per channel
Power-on reset to zero scale or midscale
Three power-down functions, per-channel power-down, hardware power-down lockout (PDL)
Low glitch on power-up
Hardware LDAC with software LDAC override
CLR function to programmable code (zero, midscale, full scale)
SDO daisy-chaining option
3-wire Schmitt trigger serial interface, compatible with SPI, QSPI, MICROWIRE, DSP

Applications:

Process controls
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

Package:

14-lead TSSOP

AD5065ARUZ Features

Low power dual 12-/14-/16-bit DAC, ±1 LSB INL Individual voltage reference pins Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to zero scale or midscale Power down to 400 nA @ 5 V 3 power-down functions Per channel power-down Low glitch upon power-up Hardware power-down lockout capability Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining option

14-lead TSSOP

AD5065ARUZ Applications

Process controls Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

AD5065ARUZ Pin Configuration

Figure 5. Pin Configuration

Pin No.	Mnemonic	Description
1	LDAC	Pulsing this pin low allows any or all DACregisters to be updated if the input registers have newdata.This allows all DACoutputs to simultaneously update.This pin can be tied permanently low in standalone mode.Whendaisy-chain modeis enabled, this pin cannot be tied permanently low.The LDAC pin should be used in asynchronous LDAC update mode, as shown in Figure 3, and the LDAC pin must be brought high after pulsing. This allows all DAC outputs to simultaneously update.
2	SYNC	Active Low Control Input. This is the frame synchronization signal for the input data.When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32 nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.
3	V DD	Power Supply Input.These parts can be operated from 4.5V to 5.5 V, and the supply should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4	V REF A	DAC A Reference Input. This is the reference voltage input pin for DAC A.
5	V OUT A	Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
6	POR	Power-On Reset Pin. Tying this pin to GNDpowers up the part to 0 V. Tying this pin toV DD powers up the part to midscale.
7	SDO	Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock.
8	CLR	Asynchronous Clear Input. The CLR input is falling edge sensitive.When CLR is low, all LDAC pulses are ignored.When CLR is activated, the input register and the DAC register are updated with the data contained in the clear code register-zero, midscale, or full scale. Default setting clears the output to 0V.
9	V REF B	DAC B Reference Input. This is the reference voltage input pin for DAC B.
10	V OUT B	Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
11	GND	Ground Reference Point for All Circuitry on the Part.
12	PDL	The PDL pin is used to ensure hardware shutdown lockout of the device under any circumstance. A Logic 1 at the PLO pin causes the device to behave as normal. The user may successfully enter software power-down over the serial interface while Logic 1 is applied to the PDL pin. If a Logic 0 is applied to this pin, it ensures that the device cannot enter software power-down under any circumstances. If the device had previously been placed in software power-down mode, a high-to- low transition at the PDLpincauses the DAC(s) to exitpower-downandoutput a voltage corresponding to the previous code in the DAC register before the device entered software power-down.
13	DIN	Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.
14	SCLK	Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz.

AD5065ARUZ Electrical Characteristics

VDD = 4.5 V to 5.5 V , RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD. All specifications TMIN to TMAX, unless otherwise noted.

Variants on the same datasheet

These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.

Part Number	Manufacturer	Package
AD5065	Analog Devices	14-lead TSSOP
AD5065ARUZ-REEL7	Analog Devices	TSSOP-14
AD5065BRUZ	Analog Devices	14-TSSOP (0.173", 4.40mm Width)
AD5065BRUZ-REEL7	Analog Devices	TSSOP-14

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