XC2S100

DS001-2 (v2.2) September 3, 2003 46 pages

• Architectural Description
• -Spartan-II Array
• -Input/Output Block
• -Configurable Logic Block
• -Block RAM
• -Clock Distribution: Delay-Locked Loop
• -Boundary Scan
• Development System
• Configuration
• -Configuration Timing
• Design Considerations

• Second generation ASIC replacement technology
• -Densities as high as 5,292 logic cells with up to 200,000 system gates
• -Streamlined features based on Virtex architecture
• -Unlimited reprogrammability
• -Very low cost
• -Advanced 0.18 micron process

Table 1: Spartan-II FPGA Family Members

1. All user I/O counts do not include the four global clock/user input pins. See details in Table 2, page 3.

© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Use the BUFGDLL macro as the simplest way to provide zero propagation delay for a high-fanout on-chip clock from an external input. This macro uses the IBUFG, CLKDLL and BUFG primitives to implement the most basic DLL application as shown in Figure 24.

Figure 24: BUFGDLL Schematic

This symbol does not provide access to the advanced clock domain controls or to the clock multiplication or clock division features of the DLL. This symbol also does not provide access to the RST, or LOCKED pins of the DLL. For access to these features, a designer must use the library DLL primitives described in the following sections.

1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. The I/O leakage current specification applies only when the V CCINT and V CCO supply voltages have reached their respective minimum Recommended Operating Conditions.
3. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors do not provide valid logic levels when input pins are connected to other circuits.

1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Power supplies may turn on in any order.
3. VIN should not exceed V CCO by more than 3.6V over extended periods of time (e.g., longer than a day).
4. Spartan-II I/Os are 5V Tolerant whenever the LVTTL, LVCMOS2, or PCI33_5 signal standard has been selected. With 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either +5.5V or 10 mA, and undershoot must be limited to either -0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to -2.0V or overshoot to +7.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
5. Without 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either V CCO + 0.5V or 10 mA, and undershoot must be limited to -0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to -2.0V or overshoot to V CCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
6. For soldering guidelines, see the Packaging Information on the Xilinx web site: http://www.xilinx.com/publications/products/packaging/index.htm

© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm . All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Functional operation is guaranteed down to a minimum V CCINT of 2.25V (Nominal V CCINT - 10%). For every 50 mV reduction in VCCINT below 2.375V (nominal V CCINT - 5%), all delay parameters increase by 3%.
3. Minimum and maximum values for V CCO vary according to the I/O standard selected.
4. Input and output measurement threshold is ~50% of V CCO .
5. Supply voltages may be applied in any order desired.