STM32U585OI

Part: STM32U585AII6 — STMicroelectronics (STM32U585xx family)

Type: Ultra-low-power Arm Cortex-M33 32-bit MCU with TrustZone and FPU

Description: Ultra-low-power Arm Cortex-M33 MCU at up to 160 MHz (240 DMIPS) with up to 2 MB Flash, 786 KB SRAM, crypto, and a 1.71–3.6 V supply range.

Operating Conditions:

• Supply voltage (VDD): 1.71–3.6 V (1.71–2.7 V when IO_VDD_HSLV = 1)
• Operating temperature: -40 to +85 °C (suffix 6; suffix 3 parts extend to +125 °C)
• Max HCLK: 160 MHz (Range 1), 110 MHz (Range 2), 55 MHz (Range 3), 25 MHz (Range 4)
• VBAT: 1.65–3.6 V; VDDA: 1.62–3.6 V with ADC used

Absolute Maximum Ratings:

• Max external supply voltage (VDDX - VSS): 4.0 V
• Max current into each VDD pin: 100 mA; total into all VDD lines: 200 mA
• Max output current sunk or sourced by any I/O pin: 20 mA
• Max junction temperature: 140 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• Supply: VDD 1.71–3.6 V; VDDIO2 1.08–3.6 V when PG[15:2] I/Os used
• Core voltage (VCORE): 1.21 V typ in Range 1, 1.1 V typ in Range 2, 1.0 V typ in Range 3, 0.9 V typ in Range 4
• Max HCLK/PCLK frequency: 160 MHz in Range 1
• Run mode: 19.5 μA/MHz at 3.3 V
• Shutdown mode: 160 nA (24 wake-up pins)
• Standby mode: 210 nA; 530 nA with RTC
• Stop 3 mode: 1.9 μA with 16 KB SRAM; 4.3 μA with full SRAM
• Stop 2 mode: 4.0 μA with 16 KB SRAM; 8.95 μA with full SRAM
• Benchmarks: 651 CoreMark (4.07 CoreMark/MHz), 1.5 DMIPS/MHz

Features:

• Arm Cortex-M33 with TrustZone, MPU, DSP, and FPU
• 2 MB Flash with ECC (2 banks, read-while-write); 786 KB SRAM
• 8 KB instruction cache and 4 KB data cache (ART Accelerator)
• SESIP3 and PSA Level 3 certified; AES (including a DPA-resistant coprocessor), PKA, HASH, TRNG, OTFDEC, and active tampers
• Embedded LDO and SMPS step-down converter
• Up to 136 I/Os; 2 Octo-SPI interfaces; FSMC
• 14-bit and 12-bit ADCs (2.5 Msps), 2 DACs, 2 op-amps, 2 comparators
• USB OTG FS, USB Type-C/PD controller, FDCAN, 2 SDMMC, 4 I2C, 6 U(S)ART, 3 SPI, 2 SAI
• Up to 17 timers, 2 watchdogs, RTC
• LPBAM autonomous low-power mode
• SWD, JTAG, and ETM debug

Applications:

• Not listed in the provided text

Package:

• LQFP48 (7 x 7 mm)
• UFQFPN48 (7 x 7 mm)
• LQFP64 (10 x 10 mm)
• WLCSP90 (4.2 x 3.95 mm)
• LQFP100 (14 x 14 mm)
• UFBGA132 (7 x 7 mm)
• LQFP144 (20 x 20 mm)
• UFBGA169 (7 x 7 mm)

• Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
• 1 digital camera interface

Table 26. Legend/abbreviations used in the pinout table

Table 26. Legend/abbreviations used in the pinout table

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DS13086 Rev 10

• 118/350 Table 27. STM32U585xx pin definitions (continued) - Pin number - LQFP48 SMPS UFQFPN48 SMPS Table 27. STM32U585xx pin definitions (continued) - Pin number - LQFP64 SMPS Table 27. STM32U585xx pin definitions (continued) - Pin number - WLCSP90 SMPS LQFP100 SMPS Table 27. STM32U585xx pin definitions (continued) - Pin number - UFBGA132 SMPS Table 27. STM32U585xx pin definitions (continued) - Pin number - LQFP144 SMPS Table 27. STM32U585xx pin definitions (continued) - Pin number - UFBGA169 SMPS Table 27. STM32U585xx pin definitions (continued) - Pin number - LQFP48 UFQFPN48 Table 27. STM32U585xx pin definitions (continued) - Pin number - LQFP64 Table 27. STM32U585xx pin definitions (continued) - Pin number - LQFP100 Table 27. STM32U585xx pin definitions (continued) - Pin number - UFBGA132 Table 27. STM32U585xx pin definitions (continued) - Pin number - LQFP144 Table 27. STM32U585xx pin definitions (continued) - Pin name (function after reset) Table 27. STM32U585xx pin definitions (continued) - Pin type Table 27. STM32U585xx pin definitions (continued) - I/O structure Table 27. STM32U585xx pin definitions (continued) - Notes Table 27. STM32U585xx pin definitions (continued) - Alternate functions Table 27. STM32U585xx pin definitions (continued) - Additional functions Table 27. STM32U585xx pin definitions (continued)
• • 27 H6 44 K9 66 K9 21 29 47 K9 69 PB10 I/O FT_ fhv - TIM2_CH3, LPTIM3_CH1, I2C4_SCL, I2C2_SCL(boot), SPI2_SCK, USART3_TX, LPUART1_RX, TSC_SYNC, OCTOSPIM_P1_CLK, LPGPIO1_P4, COMP1_OUT, SAI1_SCK_A, EVENTOUT WKUP8
• DS13086 Rev - - - 45 L9 67 L9 - - - L9 - PB11 I/O FT_fh - TIM2_CH4, I2C4_SDA, I2C2_SDA(boot), SPI2_RDY, USART3_RX, LPUART1_TX, OCTOSPIM_P1_NCS, COMP2_OUT, EVENTOUT -
• 10 20 28 K6 46 M10 68 N9 - - - - - VLXSMPS S - - - -
• 21 29 K4 47 M9 69 N10 - - - - - VDDSMPS S - - - -
• 22 30 J5 48 L10 70 M10 - - - - - VSSSMPS S - - - -
• • • • • • • • 22 30 48 L10 70 VCAP S - - - -
• 23 31 K2 49 M11 71 N11 - - - - - VDD11 S - - - -
• 24 32 J3 50 E9 72 M11 23 31 49 E9 71 VSS S - - - -
• 25 33 J1 51 D4 73 N12 24 32 50 D4 72 VDD S - - - -

1. PC13, PC14 and PC15 are supplied through the power switch (by V SW ). Since the switch only sinks a limited amount of current (3 mA), the use of PC13 to PC15 GPIOs in output mode is limited:

• PC13 speed must not exceed 2 MHz with a maximum load of 30 pF. Refer to FT_o electrical characteristics for PC14, PC15.
• These GPIOs must not be used as current sources (for example to drive a LED).

1. After a backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function depends then on the content of the RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the backup domain and RTC register descriptions in the product reference manual.
2. After reset, a pull-down resistor (Rd = 5.1 k Ω from UCPD peripheral) can be activated on PA15 and PB15 (UCPD1_CC1, UCPD1_CC2). The pull-down on PA15 (UCPD1_CC1) is activated by high level on PB5 (UCPD1_DBCC1). The pull-down on PB15 (UCPD1_CC2) is activated by high level on PB14 (UCPD1_DBCC2). This pull-down control (dead battery support on UCPD) can be disabled by setting UCPD_DBDIS = 1 in the PWR_UCPDR register.
3. After reset, this pin is configured as JTAG/SWD alternate functions. The internal pull-up on PA15, PA13, PB4 pins and the internal pull-down on PA14 pin are activated.

The definition and values of output AC characteristics are given in Figure 37: Output AC characteristics definition and in the table below respectively.

Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 33 .

Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode and FT_o I/Os (1) ) (2)(3)(4)

Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode and FT_o I/Os (1) ) (2)(3)(4)

309

Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode and FT_o I/Os (1) ) (2)(3)(4) (continued)

Table 98. Output AC characteristics, HSLV OFF (all I/Os except FT_c, FT_t in V BAT mode and FT_o I/Os (1) ) (2)(3)(4) (continued)

Stresses above the absolute maximum ratings listed in Table 30 , Table 31 and Table 32 may cause permanent damage to the device. These are stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Device mission profile (application conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on demand.

309

Table 30. Voltage characteristics (1)(2)

1. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.
2. VDDIO1 or V DDIO2 or V SW , V DDIO1 = V DD .
3. VIN maximum must always be respected. Refer to Table 31 for the maximum allowed injected current values.
4. To sustain a voltage higher than 4 V, the internal pull-up/pull-down resistors must be disabled.
5. This formula has to be applied only on the power supplies related to the I/O structure described in the pin definition table.
6. Including VREF- pin.

Table 31. Current characteristics

Table 31. Current characteristics

1. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins, referring to high pin count QFP packages.
2. Positive injection (when V IN > V DDIOx ) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
3. A negative injection is induced by V IN < V SS . I INJ(PIN) must never be exceeded. Refer also to Table 30 for the minimum allowed input voltage values.
4. When several inputs are submitted to a current injection, the maximum ∑ |I INJ(PIN) is the absolute sum of the negative injected currents (instantaneous values).

Table 32. Thermal characteristics

Table 32. Thermal characteristics

309

The maximum chip-junction temperature, T J max, in degrees Celsius, can be calculated using the following equation:

$$T_{J\ max} = T_{A\ max} + (P_{D\ max} \times \Theta_{JA})$$

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com . ECOPACK is an ST trademark.