STM32F446ZE

Part: STM32F446RCT6 — STMicroelectronics

Type: ARM Cortex-M4 32-bit MCU with FPU

Description: Arm Cortex-M4 MCU with FPU at up to 180 MHz (225 DMIPS), 256 KB Flash (RC variant) / up to 512 KB in the family, 128+4 KB RAM, 1.7–3.6 V supply, USB OTG HS/FS, three 12-bit ADCs and 20 communication interfaces.

Operating Conditions:

• Supply voltage (VDD): 1.7–3.6 V
• Operating temperature: -40 to 85 °C (suffix 6 version, maximum power dissipation; up to 105 °C at low power dissipation)
• Max HCLK: 180 MHz (Power Scale 1, over-drive ON); 168 MHz with over-drive OFF
• VDDA: 1.7–3.6 V (2.4–3.6 V for ADC up to 2.4 MSPS); VBAT: 1.65–3.6 V

Absolute Maximum Ratings:

• Max external supply voltage (VDD–VSS): 4.0 V (min -0.3 V)
• Input voltage on FT/FTf pins: VDD + 4.0 V max; on TTa and other pins: 4.0 V max; BOOT0: 9.0 V max
• Total current into all VDD lines: 240 mA; per VDD pin: 100 mA
• Output current per I/O pin: 25 mA sunk / -25 mA sourced; total all I/Os: 120 mA sunk / -120 mA sourced
• Max junction temperature: 125 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• VDD standard operating voltage: 1.7–3.6 V
• fHCLK: up to 180 MHz (Scale 1, over-drive ON); 168 MHz (Scale 1/2, over-drive OFF/ON); 144 MHz (Scale 2, over-drive OFF); 120 MHz (Scale 3)
• fPCLK1: up to 45 MHz; fPCLK2: up to 90 MHz (over-drive ON)
• Input voltage on RST/FT/FTf pins: -0.3 to 5.5 V (2 V ≤ VDD ≤ 3.6 V); 5.2 V max for 1.7 V ≤ VDD ≤ 2 V
• Power dissipation (TA = 85 °C, suffix 6): 345 mW (LQFP64)
• VDDUSB: 3–3.6 V when USB is used
• Internal 1.2 V regulator output (VCAP): 1.26–1.40 V in Power Scale 1

Features:

• Arm Cortex-M4 with FPU, MPU, DSP instructions and ART Accelerator for 0-wait-state Flash execution
• Flexible memory controller (SRAM, PSRAM, SDRAM, NOR/NAND) and dual-mode QuadSPI
• 3× 12-bit 2.4 MSPS ADCs (7.2 MSPS interleaved), 2× 12-bit DACs
• Up to 17 timers, 16-stream DMA
• Up to 4× I2C, 4 USARTs + 2 UARTs, 4 SPIs (3 with I2S), 2× SAI, 2× CAN 2.0B, SDIO, HDMI-CEC, SPDIF-Rx
• USB 2.0 OTG FS and HS (with ULPI), 8–14-bit camera interface
• POR, PDR, PVD, BOR; RTC with VBAT supply and backup SRAM
• SWD, JTAG and Cortex-M4 ETM trace
• 96-bit unique ID, CRC unit

Applications:

Package:

• LQFP64 (10 × 10 mm) — the RC/T6 variant

• Core: Arm ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
• -512 Kbytes of Flash memory
• -128 Kbytes of SRAM
• -Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memories
• -Dual mode QuadSPI interface
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
• -1.7 V to 3.6 V application supply and I/Os
• -POR, PDR, PVD and BOR
• -4 to 26 MHz crystal oscillator
• -Internal 16 MHz factory-trimmed RC (1% accuracy)
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Low power
• -Sleep, Stop and Standby modes
• -VBAT supply for RTC, 20×32 bit backup registers plus optional 4 KB backup SRAM
• 3× 12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2× 12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers: 2x watchdog, 1x SysTick timer and up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to four IC/OC/PWM or pulse counter
• Debug mode
• -SWD and JTAG interfaces
• -Cortex ® -M4 Trace Macrocell™

DS10693 Rev 10

Figure 10. STM32F446xC/xE LQFP64 pinout

1. The above figure shows the package top view.

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Figure 11. STM32F446xC/xE LQFP100 pinout

1. The above figure shows the package top view.

Figure 12. STM32F446xC LQFP144 pinout

1. The above figure shows the package top view.

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Figure 13. STM32F446xC/xE WLCSP81 ballout

Figure 14. STM32F446xC/xE UFBGA144 ballout

1. The above picture shows the package top view.

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Table 9. Legend/abbreviations used in the pinout table

Table 10. STM32F446xx pin and ball descriptions

Table 10. STM32F446xx pin and ball descriptions

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

The definition and values of input/output AC characteristics are given in Figure 32 and Table 58 , respectively.

Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 16 .

Table 58. I/O AC characteristics (1)(2)

Table 58. I/O AC characteristics (1)(2)

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Table 58. I/O AC characteristics (1)(2) (continued)

Table 58. I/O AC characteristics (1)(2) (continued)

1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 32 .
4. For maximum frequencies above 50 MHz and V DD > 2.4 V, the compensation cell should be used.

Figure 32. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 13 , Table 14 , and Table 15 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Table 13. Voltage characteristics

VIN maximum value must always be respected. Refer to

injected current.

Table 14

for the values of the maximum allowed

Table 14. Current characteristics

1. A positive injection is induced by V IN >V DDA while a negative injection is induced by V IN <V SS . IINJ(PIN) must never be exceeded. Refer to Table 13 for the maximum allowed input voltage value.

2. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 15. Thermal characteristics

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The maximum chip-junction temperature, T J max, in degrees Celsius, can be calculated using the following equation:

T J max = T A max + (P D max x JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com .