STM32F446XC/E

Part: STM32F446xC/E

Type: Arm® Cortex®-M4 32-bit MCU+FPU

Key Specs:

• Core Frequency: up to 180 MHz
• DMIPS: 225 DMIPS
• Flash Memory: up to 512 KB
• SRAM: 128 KB
• Backup SRAM: 4 KB (optional)
• Supply Voltage: 1.7 V to 3.6 V
• ADC: 3x 12-bit, 2.4 MSPS (up to 24 channels)
• SPI Speed: 45 Mbits/s

Features:

• Adaptive real-time accelerator (ART Accelerator)
• Memory Protection Unit (MPU)
• DSP instructions
• Flexible external memory controller (SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash)
• Dual mode QuadSPI interface
• LCD parallel interface (8080/6800 modes)
• Power management: POR, PDR, PVD, BOR
• Low power modes: Sleep, Stop, Standby
• VBAT supply for RTC and backup registers
• 2x 12-bit D/A converters
• 16-stream DMA controller
• Up to 17 timers (watchdog, SysTick, 16-bit, 32-bit)
• Debug interfaces: SWD, JTAG, Cortex®-M4 Trace Macrocell™
• Up to 114 I/O ports with interrupt capability
• Up to 20 communication interfaces (SPDIF-Rx, I2C, USART/UART

• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
  • 512 Kbytes of Flash memory
  • 128 Kbytes of SRAM
  • Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memories
  • Dual mode QuadSPI interface
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
  • 1.7 V to 3.6 V application supply and I/Os
  • POR, PDR, PVD and BOR
  • 4 to 26 MHz crystal oscillator
  • Internal 16 MHz factory-trimmed RC (1% accuracy)
  • 32 kHz oscillator for RTC with calibration
  • Internal 32 kHz RC with calibration
• Low power
  • Sleep, Stop and Standby modes
  • VBAT supply for RTC, 20×32 bit backup registers plus optional 4 KB backup SRAM
• 3× 12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2× 12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers: 2x watchdog, 1x SysTick timer and up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to four IC/OC/PWM or pulse counter
• Debug mode
  • SWD and JTAG interfaces
  • Cortex®-M4 Trace Macrocell™

1. The above figure shows the package top view.

Figure 12. STM32F446xC LQFP144 pinout

1. The above figure shows the package top view.

Figure 13. STM32F446xC/xE WLCSP81 ballout

1. The above figure shows the package top view.

Figure 14. STM32F446xC/xE UFBGA144 ballout

1. The above picture shows the package top view.

DS10693 Rev 10 43/198

• LQFP64

Table 10. STM32F446xx pin and ball descriptions

• LQFP64
• 1
• 2
• 3
• 4
• 5

Table 10. STM32F446xx pin and ball descriptions (continued)

• LQFP100
• 6
• 7
• 8
• 9
• 10
• 11
• 12
• 13
• 14
• 15
• 16
• 17
• 18
• 19

• LQFP64

Table 10. STM32F446xx pin and ball descriptions (continued)

• LQFP64
• 26
• 27
• 28

Table 10. STM32F446xx pin and ball descriptions (continued)

• LQFP64

• LQFP64
• 37
• 38
• 39

Table 10. STM32F446xx pin and ball descriptions (continued)

• LQFP64
• 40
• 41
• 42
• 43
• 44
• 45
• 46
• 47
• 48
• 49
• 50

• LQFP64
• 51
• 52
• 53
• 54

Table 10. STM32F446xx pin and ball descriptions (continued)

• LQFP64

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

1. PA11, PA12, PB14 and PB15 I/Os are supplied by VDDUSB

TIM2_CH1/ TIM2_ETR - - HDMI_ CEC SPI1_NSS/ I2S1_WS SPI3_ NSS/ I2S3_WS

Table 11. Alternate function

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

• • • • • • • • • • • • -- EVENT OUT

UART4_RT S

DS10693 Rev 10 57/198

PA14JTCK- SWCLK

PA15 JTDI

STM32F446xC/E Pinout and pin description

EVENT

OUT

58/198 DS10693 Rev 10

B

PB3

Port

PB4

PB15

PB0 - TIM1_CH2N TIM3_CH3 TIM8_ CH2N

TIM8/9/10/11 CEC

I2C1/2/3 /4/CEC SPI1/2/3/4 SPI2/3/4/ SAI1

SYS TIM1/2 TIM3/4/5

PB1 - TIM1_CH3N TIM3_CH4 TIM8_ CH3N

-- - SPI3_MOSI/ I2S3_SD UART4_ CTS - OTG_HS_ ULPI_D1 - SDIO_D1 - - EVENT OUT

CAN1/2

SAI2/

QUADSPI/ OTG2_HS/ OTG1_FS

OTG1_FS

FMC/

SDIO/

DCMI

SYS

OTG2_FS

TIM12/13/

14/

QUADSPI

-- - - - - OTG_HS_ ULPI_D2 - SDIO_D2 - - EVENT OUT

PB2 - TIM2_CH4 - - - - SAI1_ SD_A SPI3_MOSI/ I2S3_SD - QUADSPI_ CLK OTG_HS_ ULPI_D4 - SDIO_CK - - EVENT OUT

Table 11. Alternate function (continued)

SPI2/3/

USART1/2/3

/UART5/

SPDIFRX

AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

SAI/

USART6/

UART4/5/

SPDIFRX

Pinout and pin description STM32F446xC/E

EVENT

OUT

• EVENT OUT

STM32F446xC/E Pinout and pin description

DS10693 Rev 10 59/198

60/198 DS10693 Rev 10

• 1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V.
• 2. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.16.2: Internal reset OFF).
• 1. When the ADC is used, refer to Table 74: ADC characteristics.
• 1. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
• 1. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation.
• 1. The over-drive mode is not supported when the internal regulator is OFF.
• 1. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
• 1. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
• 1. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.

Stresses above the absolute maximum ratings listed in Table 13, Table 14, and Table 15 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

1. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed injected current.

Table 14. Current characteristics

1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

• 1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
• 1. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 13 for the maximum allowed input voltage value.
• 1. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated using the following equation:

TJ max = TA max + (PD max x JA)

where:

• TA max is the maximum ambient temperature in C,
• JA is the package junction-to-ambient thermal resistance, in C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:

PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH),

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.