STM32F446ME

Part: STM32F446xC/E — STMicroelectronics

Type: ARM Cortex-M4 32-bit MCU with FPU

Description: 32-bit ARM Cortex-M4 MCU with FPU at up to 180 MHz (225 DMIPS), with up to 512 KB Flash and 128 KB SRAM, USB OTG HS/FS, 3 ADCs and 20 communication interfaces.

Operating Conditions:

• Supply voltage: 1.7–3.6 V (VDD); VDDA 2.4–3.6 V for full 2.4 MSPS ADC operation
• Operating temperature: -40 to 85 °C (suffix 6; suffix 7 allows up to 105 °C; low power dissipation mode extends the range to 105 °C / 125 °C)
• Max HCLK: 180 MHz (Power Scale 1 with over-drive ON); 168 MHz with over-drive OFF

Absolute Maximum Ratings:

• Max supply voltage (VDD–VSS): 4.0 V
• Max input voltage on FT/FTf pins: VDD + 4.0 V
• Max input voltage on BOOT0: 9.0 V
• Total current into all VDD lines: 240 mA
• Max current into each VDD pin: 100 mA
• Output current sunk or sourced by any I/O: 25 mA
• Max junction temperature: 125 °C
• Storage temperature: -65 to +150 °C

Key Specs:

• Core clock: up to 180 MHz (over-drive ON, Power Scale 1)
• APB1/APB2 max clock: 45 MHz / 90 MHz (over-drive ON)
• VBAT backup supply: 1.65–3.6 V
• VDDUSB: 3–3.6 V when USB used
• 5 V-tolerant input on RST/FT/FTf pins: up to 5.5 V (2 V ≤ VDD ≤ 3.6 V)
• Power dissipation at TA = 85 °C (suffix 6): 345 mW (LQFP64), 476 mW (LQFP100), 606 mW (LQFP144)
• ADC: 3×12-bit, 2.4 MSPS each (7.2 MSPS interleaved)
• Total I/O current limit: ±120 mA sink/source across all I/Os

Features:

• ARM Cortex-M4 with FPU, MPU, DSP instructions and ART Accelerator
• 512 KB Flash, 128 KB SRAM, optional 4 KB backup SRAM
• Flexible memory controller (SRAM, PSRAM, SDRAM, NOR/NAND) and dual-mode Quad SPI
• USB 2.0 OTG FS and HS (ULPI) with dedicated USB power rail
• Up to 4 I2C, 4 USART/2 UART, 4 SPI (3 with I2S), 2 SAI, 2 CAN, SDIO, SPDIF-Rx, HDMI-CEC
• 2×12-bit DAC, 16-stream DMA, up to 17 timers
• 8- to 14-bit parallel camera interface
• POR, PDR, PVD, BOR; 4–26 MHz crystal oscillator, internal 16 MHz RC
• SWD/JTAG debug and Cortex-M4 ETM trace
• RTC with subsecond accuracy; 96-bit unique ID

Applications:

• Audio and consumer electronics
• USB-connected embedded systems
• Camera and display interface products

Package:

• LQFP64 (10×10 mm)
• LQFP100 (14×14 mm)
• LQFP144 (20×20 mm)
• UFBGA144 (7×7 mm)
• UFBGA144 (10×10 mm)
• WLCSP81

• Core: ARM ® 32-bit Cortex ® -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Fl ash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
• -512 kB of Flash memory
• -128 KB of SRAM
• -Flexible external memory controller with up to 16-bit data bus: SRAM,PSRAM,SDRAM/LPSDR SDRAM, Flash NOR/NAND memories
• -Dual mode Quad SPI interface
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
• -1.7 V to 3.6 V application supply and I/Os
• -POR, PDR, PVD and BOR
• -4-to-26 MHz crystal oscillator
• -Internal 16 MHz factory-trimmed RC (1% accuracy)
• -32 kHz oscillator for RTC with calibration
• -Internal 32 kHz RC with calibration
• Low power
• -Sleep, Stop and Standby modes
• -VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers: 2x watchdog, 1x SysTick timer and up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to 4 IC/OC/PWM or pulse counter
• Debug mode
• -SWD & JTAG interfaces
• -Cortex ® -M4 Trace Macrocell™

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Figure 10. STM32F446xC/xE LQFP64 pinout

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Figure 11. STM32F446xC/xE LQFP100 pinout

1. The above figure shows the package top view.

Figure 12. STM32F446xC LQFP144 pinout

1. The above figure shows the package top view.

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Figure 13. STM32F446xC/xE WLCSP81 ballout

Figure 14. STM32F446xC/xE UFBGA144 ballout

1. The above picture shows the package top view.

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Table 9. Legend/abbreviations used in the pinout table

Table 10. STM32F446xx pin and ball descriptions

Table 10. STM32F446xx pin and ball descriptions

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

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Table 10. STM32F446xx pin and ball descriptions (continued)

Table 10. STM32F446xx pin and ball descriptions (continued)

The definition and values of input/output AC characteristics are given in Figure 32 and Table 58 , respectively.

Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 16 .

Table 58. I/O AC characteristics (1)(2)

Table 58. I/O AC characteristics (1)(2)

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Table 58. I/O AC characteristics (1)(2) (continued)

Table 58. I/O AC characteristics (1)(2) (continued)

1. Guaranteed by design.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 32 .
4. For maximum frequencies above 50 MHz and V DD > 2.4 V, the compensation cell should be used.

Figure 32. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics , Table 14: Current characteristics , and Table 15: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Table 13. Voltage characteristics

Table 14. Current characteristics

1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
2. A positive injection is induced by V IN >V DDA while a negative injection is induced by V IN <V SS . IINJ(PIN) must never be exceeded. Refer to Table 13 for the maximum allowed input voltage value.
3. When several inputs are submitted to a current injection, the maximum Σ I INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 15. Thermal characteristics

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The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation:

T J max = T A max + (P D max x Θ JA )

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com . ECOPACK ® is an ST trademark.