STM32F446XC/E

Part: STM32F446xC/E

Type: Arm® Cortex®-M4 32-bit MCU+FPU

Key Specs:

• Core frequency: up to 180 MHz
• DMIPS: 225 DMIPS
• Flash memory: up to 512 Kbytes
• SRAM: 128 Kbytes + 4 KB backup SRAM
• Application supply: 1.7 V to 3.6 V
• ADC: 3× 12-bit, 2.4 MSPS (up to 7.2 MSPS in triple interleaved mode)
• Timers: Up to 17 (twelve 16-bit, two 32-bit, 2x watchdog, 1x SysTick)
• I/O ports: Up to 114 with interrupt capability

Features:

• Adaptive real-time accelerator (ART Accelerator)
• Flexible external memory controller (SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash)
• Dual mode QuadSPI interface
• LCD parallel interface, 8080/6800 modes
• Low power modes: Sleep, Stop, Standby
• 2× 12-bit D/A converters
• General-purpose DMA: 16-stream controller with FIFOs and burst support
• Debug mode: SWD and JTAG interfaces, Cortex®-M4 Trace Macrocell™
• Up to 20 communication interfaces (I2C, USART, UART, SPI, SAI, CAN, SDIO, CEC)
• USB 2.0 full-speed/high-speed device/host/OTG controller
• 8- to 14-bit parallel camera interface up to 54 Mbytes/s
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID

Applications:

• (Not clearly stated)

Package:

• LQFP100: 14 × 14 mm
• LQFP144: 20 x 20 mm
• UFBGA144: 7 x 7 mm
• UFBGA144: 10 x 10 mm

• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
  • 512 Kbytes of Flash memory
  • 128 Kbytes of SRAM
  • Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memories
  • Dual mode QuadSPI interface
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
  • 1.7 V to 3.6 V application supply and I/Os
  • POR, PDR, PVD and BOR
  • 4 to 26 MHz crystal oscillator
  • Internal 16 MHz factory-trimmed RC (1% accuracy)
  • 32 kHz oscillator for RTC with calibration
  • Internal 32 kHz RC with calibration
• Low power
  • Sleep, Stop and Standby modes
  • VBAT supply for RTC, 20×32 bit backup registers plus optional 4 KB backup SRAM
• 3× 12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2× 12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers: 2x watchdog, 1x SysTick timer and up to twelve 16-bit and two 32-bit timers up to 180 MHz, each with up to four IC/OC/PWM or pulse counter
• Debug mode
  • SWD and JTAG interfaces
  • Cortex®-M4 Trace Macrocell™

LQFP100 (14 × 14 mm) LQFP144 (20 x 20 mm)

UFBGA144 (7 x 7 mm) UFBGA144 (10 x 10 mm)

• Up to 114 I/O ports with interrupt capability
  • Up to 111 fast I/Os up to 90 MHz
  • Up to 112 5 V-tolerant I/Os
• Up to 20 communication interfaces
  • SPDIF-Rx
  • Up to 4× I2C interfaces (SMBus/PMBus)
  • Up to four USARTs and two UARTs (11.25 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)
  • Up to four SPIs (45 Mbits/s), three with muxed I2S for audio class accuracy via internal audio PLL or external clock
  • 2x SAI (serial audio interface)
  • 2× CAN (2.0B Active)
  • SDIO interface
  • Consumer electronics control (CEC) I/F
• Advanced connectivity
  • USB 2.0 full-speed device/host/OTG controller with on-chip PHY
  • USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
  • Dedicated USB power rail enabling on-chip PHYs operation throughout the entire MCU power supply range
• 8- to 14-bit parallel camera interface up to 54 Mbytes/s
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID

Table 1. Device summary

Reference	Part numbers
STM32F446xC/E	STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, STM32F446ZE.

Contents STM32F446xC/E

Figure 10. STM32F446xC/xE LQFP64 pinout

1. The above figure shows the package top view.

Figure 11. STM32F446xC/xE LQFP100 pinout

1. The above figure shows the package top view.

S VDD PDR_O PE 1 PE 1 PE 1 PE 3 PE 1 PE 1 PE 1 PE 1 PE 1 PE 1 PE 1 PE 1 _____________________________________ 4 4 4 4 7 4 8 8 8 1 8 9 8 8 1 8 1 8 1 8 1 8 1 8 1 8 108 PE 2 PE3 2 PE4 3 PE5 PE6 P 4 5 VBAT 🗖 6 103 PA 11 102 PA 10 101 PA 9 PC13 7 PC14 □ 8 PC15 PF0 P 100 PA 8 99 PC9 9 10 PF1 🗖 98 PC8 97 PC7 11 PF2 ☐ 12 PF3 ☐ 13 96 PC6 95 PF4 14 PF5 🗖 15 V_SS□ 16 V_DD□ 17 PF6□ 18 91 | PG6 LQFP144 PF7 ☐ 19 90 □ PG5 PF8 20 89 | PG4 88 PF9 PF10 21 22 PH0 🗖 23 86 PD15 85 PD14 84 VDD PH1 24 NRST 25 83 V_SS 82 PD13 PC0 □ 26 PC1 27 PC2 ☐ 28 81 □PD12 PC3 □ PD11 29 80 V_DD C V_SSA C 30 78 PD9 77 PD8 31 V_REF+☐ 32 VREF+ S VDDA S PA 0 S 33 76 PB 15 75 PB 14 34 35 PA 1 🗆 74 ⊟PB 13 PA 2 🗆 36 73 PB 12 33. 33. 33. 33. 33. 33. 34. 44. 44. 45. 45. 45. 45. 45. 45. 45. 4 V S S S S S S S S S S S S S S S S S S S

Figure 12. STM32F446xC LQFP144 pinout

1. The above figure shows the package top view.

ai18496c

Figure 13. STM32F446xC/xE WLCSP81 ballout

^1. The above figure shows the package top view.

Figure 14. STM32F446xC/xE UFBGA144 ballout

• A
  PC13
  PE3
  PE2
  PE1
  PE0
  PB4
  PB3
  PD6
  PD7
  PA15
  PA14
  PA13
• B
  PC14
  PE4
  PE5
  PE6
  PB9
  PB5
  PG15
  PG12
  PD5
  PC11
  PC10
  PAI2
• VDD
  C
  PC15
  VBAT
  PF0
  PF1
  PB8
  PB6
  PG14
  PG11
  PD4
  PC12
  PA11
  USB
• D
  PH0
  VSS
  VDD
  PF2
  BOOT0
  PB7
  PG13
  PG10
  PD3
  PD1
  PA10
  PA9
• PDR_
  E
  PH1
  PF3
  PF4
  PF5
  VSS
  VSS
  PG9
  PD2
  PD0
  PC9
  PA8
  ON
• F
  NRST
  PF7
  PF6
  VDD
  VDD
  VDD
  VDD
  VDD
  VDD
  VDD
  PC8
  PC7
• G
  PF10
  PF9
  PF8
  VSS
  VDD
  VDD
  VDD
  VSS
  VCAP_2
  VSS
  PG8
  PC6
• BYPASS
  H
  VSS
  VCAP_1
  PE11
  PD11
  PG7
  PG6
  PG5
  PC1
  PC2
  PC3
  PC0
  _REG
• J
  VSSA
  PA0
  PA4
  PC4
  PB2
  PG1
  PE10
  PE12
  PD10
  PG4
  PG3
  PG2
• K
  VREF-
  PA1
  PA5
  PC5
  PF13
  PG0
  PE9
  PE13
  PD9
  PD13
  PD14
  PD15
• L
  VREF+
  PA2
  PA6
  PB0
  PF12
  PF15
  PE8
  PE14
  PD8
  PD12
  PB14
  PB15
• M
  VDDA
  PA3
  PA7
  PB1
  PF11
  PF14
  PE7
  PE15
  PB10
  PB11
  PB12
  PB13
• MSv36519V2

1. The above picture shows the package top view.

DS10693 Rev 10 43/198

Table 9. Legend/abbreviations used in the pinout table

Name	Abbreviation	Definition
Pin name		Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
	S	Supply pin
Pin type	I	Input only pin
	I/O	Input / output pin
	FT	5 V tolerant I/O
	FTf	5V tolerant IO, I2C FM+ option
I/O structure	TTa	3.3 V tolerant I/O directly connected to ADC
	B	Dedicated BOOT0 pin
	RST	Bidirectional reset pin with weak pull-up resistor
Notes		Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate functions		Functions selected through GPIOx_AFR registers
Additional Functions directly selected/enabled through peripheral registers functions

		Pin number
LQFP64	LQFP100	WLCSP 81
-	1	D7
-	2	D6
-	3	A9
-	4	-

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
-	5	-
1	6	B9
2	7	C8
3	8	C9
4	9	D9
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	10	-
-	11	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
5	12	E9

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
6	13	F9
7	14	D8
8	15	G9
9	16	-
10	17	E8
11	18	F8
-	19	H9
-	-	G8
12	20	F7
-	-	-
-	21	-
13	22	H8
14	23	J9
15	24	G7
16	25	E7

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
17	26	E6
18	27	-
-	-	J8
19	28	-
20	29	H7
21	30	F6
22	31	G6
23	32	E5
24	33	J7
25	34	-

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
26	35	F5
27	36	H6
28	37	J6
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	38	J5
-	39	H5
-	40	G5

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
-	-	-
-	-	-
-	41	J4
-	42	-
-	43	-
-	44	-
-	45	-
-	46	-
29	47	H4
-	-	-
30	48	J3
31	49	H3
32	50	J2
33	51	G4

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
34	52	H2
35	53	J1
36	54	G3
-	55	-
-	56	-
-	57	-
-	58	H1
-	59	G2
-	60	G1
-	-	-
-	-	-

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
-	61	-
-	62	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	E1
37	63	F1
38	64	F2
39	65	F3

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
40	66	D1
41	67	E2
42	68	F4
43	69	E3
44	70	C1
45	71	E4
46	72	D2
-	73	C2
47	74	B1
48	75	A1
49	76	C3
50	77	B2

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
51	78	D3
52	79	D4
53	80	A2
-	81	B3
-	82	C4
54	83	D5
-	84	-
-	85	A3
-	86	-
-	-	-
-	-	-

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
-	87	B4
-	88	A4
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
-	-	-
55	89	A5

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
56	90	B5
57	91	A6
58	92	C5
59	93	B6
60	94	A7
61	95	C6
62	96	C7
-	97	-
-	98	-

Table 10. STM32F446xx pin and ball descriptions (continued)

		Pin number
LQFP64	LQFP100	WLCSP 81
63	99	B7
-	-	B8
64	100	A8

^1. PA11, PA12, PB14 and PB15 I/Os are supplied by VDDUSB

Table 11. Alternate function

	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
Port	sys	TIM1/2	TIM3/4/5	TIM8/9/10/11 CEC	I2C1/2/3 /4/CEC	SPI1/2/3/4	SPI2/3/4/ SAI1	SPI2/3/ USART1/2/3 /UART5/ SPDIFRX	SAI/ USART6/ UART4/5/ SPDIFRX	CAN1/2 TIM12/13/ 14/ QUADSPI	SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS	OTG1_FS	FMC/ SDIO/ OTG2_FS	DCMI	-	sys
PAC	-	TIM2_CH1/ TIM2_ETR	TIM5_CH1	TIM8_ETR	-	-	ı	USART2_ CTS	UART4_ TX	-	ī	-	-	-	-	EVENT OUT
PA1	-	TIM2_CH2	TIM5_CH2	-	-	-	-	USART2_ RTS	UART4_ RX	QUADSPI_ BK1_IO3	SAI2_ MCLK_B	-	-	-	-	EVENT OUT
PA2	-	TIM2_CH3	TIM5_CH3	TIM9_CH1	-	-	-	USART2_ TX	SAI2_ SCK_B	-	-	-	-	-	-	EVENT OUT
PAS	-	TIM2_CH4	TIM5_CH4	TIM9_CH2	-	-	SAI1_ FS_A	USART2_ RX	-	-	OTG_HS_ ULPI_D0	-	-	-	-	EVENT OUT
PA4	-	-	-	-	-	SPI1_NSS/I 2S1_WS	SPI3_NSS / I2S3_WS	USART2_ CK	-	-	-	-	OTG_HS_ SOF	DCMI_ HSYNC	-	EVENT OUT
PA5	j -	TIM2_CH1/ TIM2_ETR	-	TIM8_ CH1N	-	SPI1_SCK/I 2S1_CK	-	-	-	-	OTG_HS_ ULPI_CK	-	-	-	-	EVENT OUT
PA6	-	TIM1_ BKIN	TIM3_CH1	TIM8_ BKIN	-	SPI1_MISO	I2S2_ MCK	-	-	TIM13_CH1	-	-	-	DCMI_ PIXCLK	-	EVENT OUT
PA7	-	TIM1_ CH1N	TIM3_CH2	TIM8_ CH1N	-	SPI1_MOSI / I2S1_SD	-	-	-	TIM14_CH1	-	-	FMC_ SDNWE	-	-	EVENT OUT
PA8	MCO1	TIM1_CH1	-	-	I2C3_ SCL	-	-	USART1_ CK	-	-	OTG_FS_ SOF	-	-	-	-	EVENT OUT
PAS	-	TIM1_CH2	-	-	I2C3_ SMBA	SPI2_SCK /I2S2_CK	SAI1_ SD_B	USART1_ TX	-	-	-	-	-	DCMI_D0	-	EVENT OUT
PA1	0 -	TIM1_CH3	-	-	-	-	-	USART1_ RX	-	-	OTG_FS_ ID	-	-	DCMI_D1	-	EVENT OUT
PA1	1 -	TIM1_CH4	-	-	-	-	-	USART1_ CTS	-	CAN1_RX	OTG_FS_ DM	-	-	-	-	EVENT OUT
PA1	2 -	TIM1_ETR	-	-	-	-	-	USART1_ RTS	SAI2_ FS_B	CAN1_TX	OTG_FS_ DP	-	-	-	-	EVENT OUT
PA1	3 JTMS- SWDIC	-	-	-	-	-	-	-	-	-	-	-	-	-	-	EVENT OUT
PA1	4 JTCK- SWCLE	-	-	-	-	-	-	-	-	-	=	-	-	-	-	EVENT OUT
PA1	5 JTDI	TIM2_CH1/ TIM2_ETR	-	-	HDMI_ CEC	SPI1_NSS/ I2S1_WS	SPI3_ NSS/ I2S3_WS	-	UART4_RT S	-	-	-	-	-	-	EVENT OUT

Pinout and pin description

Table 11. Alternate function (continue	d)
----------------------------------------	----

		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
	Port	sys	TIM1/2	TIM3/4/5	TIM8/9/10/11 CEC	I2C1/2/3 /4/CEC	SPI1/2/3/4	SPI2/3/4/ SAI1	SPI2/3/ USART1/2/3 /UART5/ SPDIFRX	SAI/ USART6/ UART4/5/ SPDIFRX	CAN1/2 TIM12/13/ 14/ QUADSPI	SAI2/ QUADSPI/ OTG2_HS/ OTG1_FS	OTG1_FS	FMC/ SDIO/ OTG2_FS	DCMI	-	sys
	PB0	-	TIM1_CH2N	TIM3_CH3	TIM8_ CH2N	-	-	-	SPI3_MOSI/ I2S3_SD	UART4_ CTS	-	OTG_HS_ ULPI_D1	-	SDIO_D1	-	-	EVENT OUT
	PB1	-	TIM1_CH3N	TIM3_CH4	TIM8_ CH3N	-	-	-	-	-	-	OTG_HS_ ULPI_D2	-	SDIO_D2	-	-	EVENT OUT
	PB2	-	TIM2_CH4	-	-	-	-	SAI1_ SD_A	SPI3_MOSI/ I2S3_SD	-	QUADSPI_ CLK	OTG_HS_ ULPI_D4	-	SDIO_CK	-	-	EVENT OUT
	PB3	JTDO/ TRACE SWO	TIM2_CH2	-	-	I2C2_ SDA	SPI1_SCK /I2S1_CK	SPI3_SCK / I2S3_CK	-	-	-	-	-	-	-	-	EVENT OUT
	PB4	NJTRS T	-	TIM3_CH1	-	I2C3_ SDA	SPI1_MISO	SPI3_ MISO	SPI2_NSS/ I2S2_WS	-	-	-	-	-	-	-	EVENT OUT
	PB5	-	-	TIM3_CH2	-	I2C1_ SMBA	SPI1_MOSI /I2S1_SD	SPI3_ MOSI/ I2S3_SD	-	-	CAN2_RX	OTG_HS_ ULPI_D7	-	FMC_ SDCKE1	DCMI_ D10	-	EVENT OUT
	PB6	1	-	TIM4_CH1	HDMI_ CEC	I2C1_ SCL	-	-	USART1_ TX	-	CAN2_TX	QUADSPI_ BK1_NCS	-	FMC_ SDNE1	DCMI_D5	-	EVENT
	PB7	1	-	TIM4_CH2	-	I2C1_ SDA	-	-	USART1_ RX	SPDIF_ RX0	-	-	-	FMC_NL	DCMI_ VSYNC	-	EVENT OUT
B	PB8	1	TIM2_CH1/ TIM2_ETR	TIM4_CH3	TIM10_ CH1	I2C1_ SCL	-	-	-	-	CAN1_RX	-	-	SDIO_D4	DCMI_D6	-	EVENT OUT
	PB9	1	TIM2_CH2	TIM4_CH4	TIM11_ CH1	I2C1_ SDA	SPI2_NSS/ I2S2_WS	SAI1_ FS_B	-	-	CAN1_TX	-	-	SDIO_D5	DCMI_D7	-	EVENT OUT
	PB10	1	TIM2_CH3	-	-	I2C2_ SCL	SPI2_SCK/ I2S2_CK	SAI1_ SCK_A	USART3_ TX	-	-	OTG_HS_ ULPI_D3	-	-	-	-	EVENT OUT
	PB11	-	TIM2_CH4	-	-	I2C2_ SDA	-	-	USART3_ RX	SAI2_ SD_A	-	-	-	-	-	-	EVENT OUT
	PB12	-	TIM1_BKIN	-	-	I2C2_ SMBA	SPI2_NSS/ I2S2_WS	SAI1_ SCK_B	USART3_ CK	-	CAN2_RX	OTG_HS_ ULPI_D5	-	OTG_ HS_ID	-	-	EVENT
	PB13	-	TIM1_CH1N	-	-	-	SPI2_SCK/ I2S2_CK	-	USART3_ CTS	-	CAN2_TX	OTG_HS_ ULPI_D6	-	-	-	-	EVENT
	PB14	-	TIM1_CH2N	-	TIM8_ CH2N	-	SPI2_MISO	-	USART3_ RTS	-	TIM12_CH1	-	-	OTG_ HS_DM	-	-	EVENT OUT
	PB15	RTC_ REFIN	TIM1_CH3N	-	TIM8_ CH3N	-	SPI2_MOSI /I2S2_SD	-	-	-	TIM12_CH2	-	-	OTG_ HS_DP	-	-	EVENT OUT

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to V_SS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T_A = 25 °C and T_A = T_A max (given by the selected temperature range).

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3sigma ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on T_A = 25 °C, V_DD = 3.3 V (for the 1.7 V ≤ V_DD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested.

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2sigma ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 16.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 17.

6.1.6 Power supply scheme

V_BAT Backup circuitry V_BAT = (OSC32K,RTC, Power 1.65 to 3.6V switch Wakeup logic Backup registers, backup RAM) 10 GPIOs Logic V_CAP1 Kernel logic 2 × 2.2 uF V_CAP2 (CPU, digital & RAM) V_DD 1/2/...11/12 Voltage regulator 12 × 100 nF + 1 × 4.7 μ F 1/2/...11/12 V_DDUSB⁽²⁾ BYPASS REG Flash memory V_DDUSB⁽²⁾ DUV Reset PDR ON controlle V_DDA V_REF V_REF Analog: 100 nF 100 nF ADC RCs, V_mathsf{REF} + 1 μF Veen MSv33072V1

Figure 18. Power supply scheme

• 1. V_DDA and V_SSA must be connected to V_DD and V_SS , respectively.
• V_DDUSB is a dedicated independent USB power supply for the on-chip full-speed OTG PHY module and associated DP/DM GPlOs. Its value is independent from the V_DD and V_DDA values, but must be the last supply to be provided and the first to disappear. If V_DD is different from V_DDUSB and only one on-chip OTG PHY is used, the second OTG PHY GPIOs (DP/DM) are still supplied at V_DDUSB (3.3V).
• 3. V_DDUSB is available only on WLCSP81, UFBGA144 and LQFP144 packages. For packages where V_DDUSB pin is not available, it is internally connected to V_DD .
• 4. V_{CAP 2} pad is not available on LQFP64.

Caution:

Each power supply pair (e.g. V_DD/V_SS , V_DDA/V_SSA ) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.

6.1.7 Current consumption measurement

MSv36557V1 VBAT VDD VDDA IDD_VBAT IDD VDDUSB

Figure 19. Current consumption measurement scheme

Stresses above the absolute maximum ratings listed in Table 13, Table 14, and Table 15 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard, extended mission profiles are available on demand.

Symbol	Ratings	Min	Max	Unit
VDD–VSS	External main supply voltage (including VDDA, VDD, (1) VDDUSB and VBAT)	–0.3	4.0
	Input voltage on FT & FTf pins(2)	VSS–0.3	VDD+4.0
	Input voltage on TTa pins		4.0	V
VIN	Input voltage on any other pin	VSS–0.3 4.0
	Input voltage on BOOT0 pin	VSS	9.0
VDDx	Variations between different VDD power pins	-	50	mV
VSSX VSS	Variations between all the different ground pins -		50
VESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 6.3.15		-

Table 13. Voltage characteristics

^1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

^2. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed injected current.

Table 14. Current characteristics

Symbol	Ratings	Max.	Unit
IVDD	Total current into sum of all VDD power lines (source)(1)	240
IVSS	Total current out of sum of all VSS ground lines (sink)(1)	- 240
IVDDUSB	Total current into VDDUSB power line (source)	25
IVDD	Maximum current into each VDD power pin (source)(1)	100
IVSS	Maximum current out of each VSS ground pin (sink)(1)	- 100
	Output current sunk by any I/O and control pin	25
IIO	Output current sourced by any I/Os and control pin	- 25	mA
	Total output current sunk by sum of all I/Os and control pins (2)	120
IIO	Total output current sunk by sum of all USB I/Os	25
	Total output current sourced by sum of all I/Os and control pins(2)	-120
	Injected current on FT, FTf, RST and B pins	–5/+0(3)
IINJ(PIN)	Injected current on TTa pins	±5(4)
IINJ(PIN)	Total injected current (sum of all I/O and control pins)(5)	±25

• 1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value.
• 1. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 13 for the maximum allowed input voltage value.
• 1. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 15. Thermal characteristics

Symbol	Ratings Value		Unit
TSTG	Storage temperature range	–65 to +150	°C
TJ	Maximum junction temperature	125	°C

^2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.

The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated using the following equation:

TJ max = TA max + (PD max x JA)

where:

• TA max is the maximum ambient temperature in C,
• JA is the package junction-to-ambient thermal resistance, in C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:P_I/O max = sum (V_OL × I_OL) + sum ((V_DD - V_OH) × I_OH),$

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

Symbol	Parameter	Value	Unit
JA	Thermal resistance junction-ambient LQFP64 - 10 × 10 mm	46
	Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch	42
	Thermal resistance junction-ambient LQFP144 - 20 × 20 mm / 0.5 mm pitch	33
	Thermal resistance junction-ambient UFBGA144 - 7 × 7 mm / 0.5 mm pitch	51	°C/W
	Thermal resistance junction-ambient UFBGA144 - 10 × 10 mm / 0.8 mm pitch	48
	Thermal resistance junction-ambient WLCSP81	48

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

Part numbering STM32F446xC/E