NAU8810YG
The NAU8810YG is an electronic component. View the full NAU8810YG datasheet below including electrical characteristics, absolute maximum ratings.
Overview
The NAU8810 a cost effective low power wideband Monophonic audio CODEC. It is suitable for a wide range of audio applications, including voice telephony. Supported functions include a 5-band Graphic Equalizer, Automatic Level Control (ALC) with noise gate, PGA, standard I2S or PCM audio interface, optional PCM time slot assignment, and a full fractional-N on-chip PLL. This device includes one differential microphone input, and multiple variable gain control stages in the audio paths. Both a Mono headset/line-level output and a high power differential BTL speaker driver output are provided.
The analog input path includes a PGA enabling dynamic range optimization of a wide range of input sources with programmable gain from -12dB to +35.25dB. In addition to a digital high pass filter to remove DC offset voltages, the ADC also features programmable voice band digital filtering. Audio data is communicated via the audio interface that supports multiple I2S and PCM data formats. The DAC converter path includes filtering, and mixing, programmable-gain amplifiers, and soft muting. The 2-Wire digital control interface has an independent supply voltage to enable easy integration into multiple supply voltage systems. The NAU88U10 operates at supply voltages from 2.5V to 3.6V, and the digital core can operate at a voltage as low as 1.71V to conserve power.
The NAU8810 is specified for operation from -40 C to +85 C, and is available with automotive AEC-Q100 qualification. Please refer to ordering information for AEC-Q100 compliance part number.
Features
- 5-band Graphic Equalizer
- Programmable ALC
- ADC Notch Filter
- Programmable High Pass Filter
- Digital ADC/DAC Passthrough
- Mono data output on both channels
- Automotive AEC-Q100 grade 3 & TS16949 qualification, tested to a higher reliability standard
- Temperature: -40 C to +85 C
Applications
- All types of wired/wireless telephony
- Security Systems
- Mobile Telephone Hands-free Kits
- Residential & Consumer Intercoms
Pin Configuration
Figure 1: 20-Pin QFN Package
Electrical Characteristics
VDDD = 1.8V, VDDA = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25 o C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated.
| PARAMETER | SYMBOL | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| Analogue to Digital Converter (ADC) | Analogue to Digital Converter (ADC) | Analogue to Digital Converter (ADC) | Analogue to Digital Converter (ADC) | Analogue to Digital Converter (ADC) | Analogue to Digital Converter (ADC) | Analogue to Digital Converter (ADC) |
| Full scale input signal 1 | V INFS | PGABST = 0dB PGAGAIN = 0dB | 1.0 0 | V RMS dBV | ||
| Signal to Noise Ratio 2 | SNR | Gain = 0dB, A-weighted | 87 | 91 | dB | |
| Total Harmonic Distortion 3 | THD | Input = -1dBFS, Gain = 0dB | -79 | -65 | dB | |
| Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load) | Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load) | Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load) | Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load) | Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load) | Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load) | Digital to Analogue Converter (DAC) to MONO output (all data measured with 10kΩ / 50pF load) |
| Full Scale output signal 1 | MOUTBST=0 MOUTBST=1 | 1.0x (V REF ) 1.5 x V REF | V RMS V RMS | |||
| Signal to Noise Ratio 2 | SNR | A-weighted (ADC/DAC oversampling rate of 128) | 90 | 93 | dB | |
| Total Harmonic Distortion 3 | THD | R L = 10 KΩ; -1.0dBfs | -84 | -70 | dB | |
| Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA) | Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA) | Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA) | Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA) | Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA) | Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA) | Microphone Inputs (MICN & MICP) and MIC Input Programmable Gain Amplifier (PGA) |
| Full-scale Input Signal Level 1 | V INFS | PGABST = 0dB PGAGAIN = 0dB | 1 0 | V RMS dBV | ||
| Programmable input PGA gain | -12 | 35.25 | dB | |||
| Programmable Gain Step Size | Guaranteed monotonic | 0.75 | dB | |||
| Programmable Boost PGA | PGABST = 0 | 0 | ||||
| gain | PGABST = 1 | 20 | dB | |||
| Mute Attenuation | 100 | dB | ||||
| PGA equivalent output noise | 0 to 20kHz, Gain set to 35.25dB | 110 | μV | |||
| Auxiliary Input resistance | PGA Gain = 35.25dB | 1.6 | kΩ | |||
| R AUX | PGA Gain = 0dB PGA Gain = -12dB | 47 75 | kΩ kΩ | |||
| Positive Microphone Input resistance | R MIC+ | PMICPGA = 1 | 94 | kΩ | ||
| Input Capacitance | C MIC | 10 | pF | |||
| Speaker Output PGA | Speaker Output PGA | Speaker Output PGA | Speaker Output PGA | Speaker Output PGA | Speaker Output PGA | Speaker Output PGA |
| Programmable Gain | -57 | 6 | dB | |||
| Programmable Gain Step Size | Guaranteed monotonic | 1 | dB |
VDDD = 1.8V, VDDA = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25 o C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated.
| PARAMETER | SYMBOL | TEST | CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|---|---|
| BTL Speaker Output (SPKOUT+, SPKOUT- with 8 Ω bridge tied load) | BTL Speaker Output (SPKOUT+, SPKOUT- with 8 Ω bridge tied load) | BTL Speaker Output (SPKOUT+, SPKOUT- with 8 Ω bridge tied load) | BTL Speaker Output (SPKOUT+, SPKOUT- with 8 Ω bridge tied load) | BTL Speaker Output (SPKOUT+, SPKOUT- with 8 Ω bridge tied load) | BTL Speaker Output (SPKOUT+, SPKOUT- with 8 Ω bridge tied load) | BTL Speaker Output (SPKOUT+, SPKOUT- with 8 Ω bridge tied load) | BTL Speaker Output (SPKOUT+, SPKOUT- with 8 Ω bridge tied load) | BTL Speaker Output (SPKOUT+, SPKOUT- with 8 Ω bridge tied load) |
| Full scale output 7 | SPKBST = 0 VDDSPK = VDDA | SPKBST = 0 VDDSPK = VDDA | SPKBST = 0 VDDSPK = VDDA | VDDA / 3.3 | VDDA / 3.3 | VDDA / 3.3 | V RMS | |
| Full scale output 7 | SPKBST = 1 VDDSPK = 1.5 * VDDA | SPKBST = 1 VDDSPK = 1.5 * VDDA | SPKBST = 1 VDDSPK = 1.5 * VDDA | (VDDA / 3.3) * 1.5 | (VDDA / 3.3) * 1.5 | (VDDA / 3.3) * 1.5 | V RMS | |
| Output Power | PO | Output power is very closely correlated with THD; see below | Output power is very closely correlated with THD; see below | Output power is very closely correlated with THD; see below | Output power is very closely correlated with THD; see below | Output power is very closely correlated with THD; see below | Output power is very closely correlated with THD; see below | |
| Signal to Noise Ratio | SNR | VDDSPK = 3.3V RL = 8Ω | VDDSPK = 3.3V RL = 8Ω | VDDSPK = 3.3V RL = 8Ω | 90 | dB | ||
| Signal to Noise Ratio | SNR | VDDSPK = 1.5*VDDA RL = 8Ω | VDDSPK = 1.5*VDDA RL = 8Ω | VDDSPK = 1.5*VDDA RL = 8Ω | 90 | dB | ||
| Total Harmonic Distortion | THD | PO =180mW | RL = 8Ω | VDDSPK=3.3V | -63 | dB | ||
| Total Harmonic Distortion | THD | PO =400mW | RL = 8Ω | VDDSPK=3.3V | -56 | dB | ||
| Total Harmonic Distortion | THD | PO =360mW | RL = 8Ω | VDDSPK = 1.5*VDDA | -60 | dB | ||
| Total Harmonic Distortion | THD | PO =800mW | RL = 8Ω | VDDSPK = 1.5*VDDA | -61 | dB | ||
| Total Harmonic Distortion | THD | PO =1W | PO =1W | PO =1W | -34 | dB | ||
| Power Supply Rejection Ratio (50Hz - 22kHz) | PSRR | VDDSPK = 3V, SPKBST = 0 | VDDSPK = 3V, SPKBST = 0 | VDDSPK = 3V, SPKBST = 0 | 50 | dB | ||
| Power Supply Rejection Ratio (50Hz - 22kHz) | PSRR | VDDSPK = 1.5*VDDA, SPKBST = 1 | VDDSPK = 1.5*VDDA, SPKBST = 1 | VDDSPK = 1.5*VDDA, SPKBST = 1 | 50 | dB | ||
| Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) | Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) | Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) | Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) | Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) | Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) | Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) | Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) | Headphone' output (SPKOUTP, SPKOUTN with resistive load to ground) |
| Full scale output 7 | VDDA / | 3.3 | V RMS | |||||
| Signal to Noise Ratio | SNR | A-weighted | A-weighted | A-weighted | 90 | dB | ||
| Total Harmonic Distortion | THD | Po = 20mW | RL=16 Ω | VDDSPK=3.3V | -84 | dB | ||
| Total Harmonic Distortion | THD | Po = 20mW | RL=32 Ω | VDDSPK=3.3V | -85 | dB | ||
| Microphone Bias | Microphone Bias | Microphone Bias | Microphone Bias | Microphone Bias | Microphone Bias | Microphone Bias | Microphone Bias | Microphone Bias |
| Bias Voltage | V MICBIAS | (MICBIASV = 0) | (MICBIASV = 0) | (MICBIASV = 0) | 0.9* VDD A | V | ||
| Bias Voltage | V MICBIAS | (MICBIASV = 1) | (MICBIASV = 1) | (MICBIASV = 1) | 0.65* VDD A | V | ||
| Bias Current Source | I MICBIAS | 3 | mA | |||||
| Output Noise Voltage | V N | MICBIASM = 0 (1kHz to 20kHz) | MICBIASM = 0 (1kHz to 20kHz) | MICBIASM = 0 (1kHz to 20kHz) | 14 | nV/√Hz | ||
| Output Noise Voltage | V N | MICBIASM = 1 (1kHz to 20kHz) | MICBIASM = 1 (1kHz to 20kHz) | MICBIASM = 1 (1kHz to 20kHz) | 4 | nV/√Hz | ||
| Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only |
| Target Record Level | -28.5 | -6 | dB | |||||
| Programmable Gain | -12 | 35.25 | dB | |||||
| Programmable Gain Step Size | Guaranteed Monotonic | Guaranteed Monotonic | Guaranteed Monotonic | 0.75 | dB | |||
| Gain Hold Time 4, 6 | t HOLD | MCLK=12.288MHz | MCLK=12.288MHz | MCLK=12.288MHz | 0 / 2.67 / …/ 43691 | 0 / 2.67 / …/ 43691 | 0 / 2.67 / …/ 43691 | ms |
| (time doubles with each step) |
|---|
emPowerAudio
™
VDDD = 1.8V, VDDA = VDDSPK = 3.3V (VDDSPK = 1.5*VDDA when Boost), TA = +25 o C, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated.
| PARAMETER | SYMBOL | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|---|
| Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only | Automatic Level Control (ALC)/Limiter - ADC only |
| Gain Ramp-Up (Decay) Time 5, 6 | t DCY | ALC Mode ALCM=0 MCLK=12.288MHz | 3.3 / 6.6 / 13.1 / …/ 3360 (time doubles every step) | 3.3 / 6.6 / 13.1 / …/ 3360 (time doubles every step) | 3.3 / 6.6 / 13.1 / …/ 3360 (time doubles every step) | ms |
| Gain Ramp-Up (Decay) Time 5, 6 | t DCY | Limiter Mode ALCM=1 MCLK=12.288MHz | 0.73 / 1.45 / 2.91 / …/ 744 (time doubles every step) | 0.73 / 1.45 / 2.91 / …/ 744 (time doubles every step) | 0.73 / 1.45 / 2.91 / …/ 744 (time doubles every step) | ms |
| Gain Ramp-Down (Attack) Time 5, 6 | t ATK | ALC Mode ALCM=0 MCLK=12.288MHz | 0.83 / 1.66 / 3.33 / …/ 852 (time doubles every step) | 0.83 / 1.66 / 3.33 / …/ 852 (time doubles every step) | 0.83 / 1.66 / 3.33 / …/ 852 (time doubles every step) | ms |
| Gain Ramp-Down (Attack) Time 5, 6 | t ATK | Limiter Mode ALCM=1 MCLK=12.288MHz | 0.18 / 0.36 / 0.73 / …/ 186 (time doubles every step) | 0.18 / 0.36 / 0.73 / …/ 186 (time doubles every step) | 0.18 / 0.36 / 0.73 / …/ 186 (time doubles every step) | ms |
| Digital Input / Output | Digital Input / Output | Digital Input / Output | Digital Input / Output | Digital Input / Output | Digital Input / Output | Digital Input / Output |
| Input HIGH Level | V IH | 0.7 × VDDD | V | |||
| Input LOW Level | V IL | 0.3 × VDDD | V | |||
| Output HIGH Level | V OH | I OL = 1mA | 0.9 × VDDD | V | ||
| Output LOW Level | V OL | I OH = -1mA | 0.1 x VDDD | V |
Absolute Maximum Ratings
| CONDITION | MIN | MAX | Units |
|---|---|---|---|
| VDDD, VDDA supply voltages | -0.3 | +3.63 | V |
| VDDSPK supply voltage (MOUTBST=0, SPKBST=0) | -0.3 | +3.63 | V |
| VDDSPK supply voltage (MOUTBST=1, SPKBST=1) | -0.3 | +5.50 | V |
| Core Digital Input Voltage range | VSSD - 0.3 | VDDD + 0.30 | V |
| Analog Input Voltage range | VSSA - 0.3 | VDDA + 0.30 | V |
| Industrial operating temperature | -40 | +85 | 0 C |
| Storage temperature range | -65 | +150 | 0 C |
CAUTION: Do not operate at or near the maximum ratings listed for extended period. Exposure to such conditions may adversely influence product reliability and result in failures not covered by warranty. These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Typical Application
Figure 48: Application Diagram For 20-Pin QFN
- Note 1: All non-polar capacitors are assumed to be low ESR type parts, such as with MLC construction or similar. If capacitors are not low ESR, additional 0.1μF and/or 0.01μF capacitors may be necessary in parallel with the bulk 4.7μF capacitors on the supply rails.
- Note 2: Load resistors to ground on outputs may be helpful in some applications to insure a DC path for the output capacitors to charge/discharge to the desired levels. If the output load is always present and the output load provides a suitable DC path to ground, then the additional load resistors may not be necessary. If needed, such load resistors are typically a high value, but a value dependent upon the application requirements.
- Note 3: To minimize pops and clicks, large polarized output capacitors should be a low leakage type.
- Note 4: Depending on the microphone device and PGA gain settings, common mode rejection can be improved by choosing the resistors on each node of the microphone such that the impedance presented to any noise on either microphone wire is equal.
Get structured datasheet data via API
Get started free