FT232R

The 48-pin LQFP and 48-pin QFN have the same pin numbering for specific functions. This pin numbering is illustrated in the schematic symbol shown in Figure 3.1

USB Hi-Speed to UART/FIFO Interface . The FT232H provides USB 2.0 Hi-Speed (480Mbits/s) to flexible and configurable UART/FIFO Interfaces.

Functional Integration . The FT232H integrates a USB protocol engine which controls the physical Universal Transceiver Macrocell Interface (UTMI) and handles all aspects of the USB 2.0 Hi-Speed interface. The FT232H includes an integrated +1.8V/3.3V Low Drop-Out (LDO) regulator. It also includes 1Kbytes Tx and Rx data buffers. The FT232H integrates the entire USB protocol on a chip with no firmware required.

MPSSE . MultiProtocol Synchronous Serial Engines (MPSSE), capable of speeds up to 30 Mbits/s, provides flexible synchronous interface configurations.

FT1248 interface. The FT232H supports a new proprietary half-duplex FT1248 interface with a variable bi-directional data bus interface that can be configured as 1, 2, 4, or 8-bits wide and this enables the flexibility to expand the size of the data bus to 8 pins. For details regarding 2-bit, 4-bit and 8-bit modes, please refer to application note AN_167_FT1248_Serial_Parallel Interface Basics available from the FTDI website.

Data Transfer rate. The FT232H supports a data transfer rate up to 12 Mbaud when configured as an RS232/RS422/RS485 UART interface upto 40 Mbytes/second over a synchronous 245 parallel FIFO interface or up to 8 Mbyte/Sec over a asynchronous 245 FIFO interface. Please note the FT232H does not support the baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud and 11 Mbaud.

Latency Timer. A feature of the driver used as a timeout to transmit short packets of data back to the PC. The default is 16ms, but it can be altered between 0ms and 255ms.

Bus (ACBUS) functionality, signal inversion and drive strength selection. There are 11 configurable ACBUS I/O pins. These configurable options are:

1. TXDEN - transmit enable for RS485 designs.
2. PWREN# - Power control for high power, bus powered designs.
3. TXLED# - for pulsing an LED upon transmission of data.
4. RXLED# - for pulsing an LED upon receiving data.
5. TX&RXLED# - which will pulse an LED upon transmission OR reception of data .
6. SLEEP# - indicates that the device going into USB suspend mode.
7. CLK30 / CLK15 / CLK7.5 30MHz, 15MHz and 7.5MHz clock output signal options.
8. TriSt-PU - Input pulled up, not used
9. DRIVE 1 - Output driving high
10. DRIVE 0 - Output driving low
11. I/O mode - ACBUS BitBang

The ACBUS pins can also be individually configured as GPIO pins, similar to asynchronous bit bang mode. It is possible to use this mode while the UART interface is being used, thus providing up to 4 general purpose I/O pins which are available during normal operation.

The ACBUS lines can be configured with any one of these input/output options by setting bits in the external EEPROM see section 3.4.

• Single chip USB to UART (RS232, RS422 or RS485)
• USB to FIFO
• USB to FT1248
• USB to JTAG
• USB to SPI
• USB to I 2 C
• USB to Bit-Bang
• USB to Fast Serial Interface
• USB to CPU target interface (as memory)

This section describes the operation of the FT232H pins. Both the LQFP and the QFN packages have the same function on each pin. The function of many pins is determined by the configuration of the FT232H. The following table details the function of each pin dependent on the configuration of the interface. Each of the functions is described in the following table (Note: The convention used throughout this document for active low signals is the signal name followed by #).

Pins marked * are EEPROM selectable

Pins marked ** default to tri-stated inputs with an internal 75KΩ (approx) pull up resistor to VCCIO.

Pin marked *** default to GPIO line with an internal 75KΩ pull down resistor to GND. Using the EEPROM this pin can be enabled USBVCC mode instead of GPIO mode.

The I/O pins are +3.3v cells, which are +5V tolerant (except the USB PHY pins).

DC Characteristics (Ambient Temperature = -40°C to +85°C)

Table 5.2 Operating Voltage and Current (except PHY)

*NOTE: Failure to connect all VCCIO pins of the device will have unpredictable behaviour.

Table 5.2 Operating Voltage and Current (except PHY)

The I/O pins are +3.3v cells, which are +5V tolerant (except the USB PHY pins).

Table 5.3 I/O Pin Characteristics VCCIO = +3.3V (except USB PHY pins)

• The I/O drive strength and slow slew-rate are configurable in the EEPROM.

FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC

DC Characteristics (Ambient Temperature = -40°C to +85°C)

Table 5.4 PHY Operating Voltage and Current

The absolute maximum ratings for the FT232H devices are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these values may cause permanent damage to the device.

• If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours.

• Single chip USB to UART (RS232, RS422 or RS485)
• USB to FIFO
• USB to FT1248
• USB to JTAG
• USB to SPI
• USB to I 2 C
• USB to Bit-Bang
• USB to Fast Serial Interface
• USB to CPU target interface (as memory)

Figure 8.1 48 pin QFN Package Details