CS43198
The CS43198 is an electronic component from Cirrus Logic Inc.. View the full CS43198 datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
Cirrus Logic Inc.
Category
Integrated Circuits (ICs)
Overview
The CS43198 is a high-performance, 32-bit resolution, stereo audio DAC that supports up to 384-kHz sampling frequency with pseudodifferential analog outputs. The advanced 32-bit oversampled multibit modulator with mismatch shaping technology eliminates distortion due to on-chip component mismatch. Proprietary digital-interpolation filters support five selectable filter responses with pseudo-linear phase and ultralow latency to minimize pre-echos and ringing artifacts. An on-chip programmable filter is available for further response customization. Other features include volume control with 0.5-dB steps, wideband flatness mode support, and digital deemphasis for 44.1-kHz sample rate.
The patented on-chip DSD processor preserves audio integrity by allowing signal processing such as volume control and 50-kHz Scarlet Book recommended filtering to be applied directly to the DSD stream without an intermediate decimation stage. Additional features like volume matching and channel mixing enable seamless transition between DSD and PCM playback paths. Direct DSD Mode is also provided to bypass the DSD processor.
The CS43198 accepts I 2 S, right-justified, left-justified, and TDM-format PCM data at sample rates from 32 to 384 kHz. The industry-standard high-speed I 2 C interface capable of up to 1-MHz operation provides easy configuration control. An integrated PLL allows for maximum clocking flexibility in any system. Popguard ® technology eliminates output transients upon power-up or power-down events.
The CS43198 is available in a commercial-grade 42-ball WLCSP or 40-pin QFN package for operation from -20°C to +70°C.
Features
- Enhanced oversampling DAC architecture
- 32-bit resolution
- Up to 384-kHz sampling rate
- Low clock jitter sensitivity
- Auto mute detection
- Integrated high performance outputs
- 130-dB dynamic range (A-weighted)
- -115-dB total harmonic distortion + noise (THD+N)
- 110-dB interchannel isolation
- Up to 2-Vrms pseudodifferential stereo analog output
- Headphone detection
- Headphone plug-in detection
- Popguard ® technology eliminates pop noise
- Integrated PLL
- Support for 11.2896-/22.5792-, 12.288-/24.576-, 9.6-/ 19.2-, 12-/24-, and 13-/26-MHz system MCLK rates
- Reference clock sourced from XTI/MCLK pin
- System clock output
- Mono Mode (differential) support
- I 2 C control-up to 1 MHz
- Wideband Flatness Mode Support
- Direct Stream Digital (DSD ® ) path
- Up to 256·Fs DSD
- Patented DSD processor
- On-chip 50-kHz filter to meet Scarlet Book Super Audio Compact Disk (SACD) recommendations
- Matched PCM and DSD analog output levels
- Nondecimating volume control with 0.5-dB step size and soft ramp
- DSD and Pulse-code modulation (PCM) mixing for alerts
- Dedicated DSD and DoP pin interface
- Direct DSD path support
- Serial audio input path
- Programmable Hi-Fi digital filter
- Five selectable digital filter responses
- Low-latency Mode minimizes pre-echo
- 110 dB of stopband attenuation
- Supports sample rates from 32 to 384 kHz
- I 2 S, right-justified, left-justified, TDM, and DSD-over-PCM (DoP) interface
- Master or slave operation
- Volume control with 0.5-dB step size and soft ramp
- 44.1 kHz deemphasis and inverting feature
- 40-pin 5mm × 5mm QFN or 42-ball CSP package options
Applications
- Smart phones, tablets, portable media players, laptops, digital headphones, powered speakers, AVR, home theater systems, Blu-ray/DVD/SACD players, and pro audio
Pin Configuration
Table 1-1. Pin Descriptions
| Pin Name | QFN Pin # | WLCSP Ball | Power Supply | I/O | Pin Description | Internal Connection | Digital I/O Driver | Digital I/O Receiver |
|---|---|---|---|---|---|---|---|---|
| Digital I/O | Digital I/O | Digital I/O | Digital I/O | Digital I/O | Digital I/O | Digital I/O | Digital I/O | Digital I/O |
| ADR | 30 | C2 | VL | I | Address Bit (I²C). In I²C Mode,ADR is a chip address pin. | - | - | - |
| CLKOUT | 33 | B2 | VL | O | CLK Output. Single-ended clock output sourced from PLL or buffered crystal. | Weak pull-down | CMOS output | - |
| SCLK1 | 34 | A2 | VL | I/O | Serial Audio Input Bit Clock 1. Serial bit clock for audio data on the SDIN pins. | Weak pull-down | CMOS output | Hysteresis onCMOS input |
| LRCK1 | 38 | B3 | VL | I/O | Serial Audio Input Left/Right Clock. Word-rate clock for the audio data on the SDIN pins. | Weak pull-down | CMOS output | Hysteresis onCMOS input |
| SDIN1 | 2 | A6 | VL | I | Serial Audio Input Data Port. Audio data serial input pin 1. | Weak pull-down | - | Hysteresis onCMOS input |
| DSDA/ SDIN2 | 40 | A5 | VL | I | DSD Data Input A/Serial Data In 2. DSD audio or PCM audio data serial input pin 2. | Weak pull-down | - | Hysteresis onCMOS input |
| DSDB/ LRCK2 | 29 | C1 | VL | I/O | DSD Data Input B/Serial Audio Input Left/Right Clock 2. DSD audio data serial input pin or word rate clock for the audio data on the SDIN2 pin. | Weak pull-down | CMOS output | Hysteresis onCMOS input |
| DSDCLK/ SCLK2 | 32 | B1 | VL | I/O | DSD Clock Input/Serial Audio Input Bit Clock 2. DSD clock input. Serial bit clock for audio data on the SDIN2 pin. | Weak pull-down | CMOS output | Hysteresis onCMOS input |
| INT | 27 | C5 | VP | O | Interrupt. When pulled up, works as system interrupt pin. Open drain, active low programmable. | - | CMOS open-drain output | - |
| RESET | 28 | C4 | VP | I | System Reset. The device enters system reset when enabled. | - | - | Hysteresis onCMOS input |
| SDA | 39 | B4 | VL | I/O | Serial Control Data I/O (I²C). In I²C Mode, SDAis the control I/O data line. | - | CMOS open-drain output | Hysteresis onCMOS input |
| SCL | 1 | B5 | VL | I | Software Clock (I²C). Serial control interface clock used to clock control data bits into and out of the CS43198. | - | - | Hysteresis onCMOS input |
| XTI/MCLK | 37 | A4 | VL | I | Crystal/Oscillator Input/MCLK In. Crystal or digital clock input for the master clock. | Weak pull-down | - | Hysteresis onCMOS input |
| XTO | 36 | A3 | VL | O | Crystal/Oscillator Output. Crystal output. | Weak pull-down | CMOS output | - |
| Analog I/O | Analog I/O | Analog I/O | Analog I/O | Analog I/O | Analog I/O | Analog I/O | Analog I/O | Analog I/O |
| FILT+ FILT- | 5 6 | D4 D5 | VA | O | Positive/Negative Voltage Reference. Positive/negative reference voltage for DAC. | - | - | - |
| HP_ DETECT | 22 | F4 | VP | I | Headphone Detect. Can be configured to be debounced on unplugged and plugged events before it is presented as a noninterrupt status bit (HPDETECT). | - | Hi-Z | - |
| AOUTB | 16 | G3 | VCP_ | O | Audio Output. Refer to analog specification table for full-scale output level. | - | - | - |
| AOUTA REFB | 14 17 | G4 | FILT± VCP_ | Output Reference. Reference for analog output. | - | - | - | |
| REFA | 13 | E3 E4 | FILT± | I | ||||
| Power Supplies | Power Supplies | Power Supplies | Power Supplies | Power Supplies | Power Supplies | Power Supplies | Power Supplies | Power Supplies |
| VL | 31 | A1 | N/A | I | Logic Power. Input/Output power supply, typically +1.8 V. | - | - | - |
| VD | 4 | C6 | N/A | I | Internal Digital Power. Internal digital power supply, typically +1.8 V. | - | - | - |
| VA | 7 | D6 | N/A | I | Analog Power. Power supply for the internal analog section. | - | - | - |
| VCP | 25 | D2 | N/A | I | Charge Pump Supply . Provides charge pump voltage to the analog output circuit. | - | - | - |
Table 1-1. Pin Descriptions
Table 1-1. Pin Descriptions (Cont.)
| Pin Name | QFN Pin # | WLCSP Ball | Power Supply | I/O Pin Description | Internal Connection | Digital I/O Driver | Digital I/O Receiver |
|---|---|---|---|---|---|---|---|
| VP | 26 | D1 | N/A | I Battery supply . Provides voltage to the headphone Class H circuit. | - | - | - |
| Ground | Ground | Ground | Ground | Ground | Ground | Ground | Ground |
| GNDD | 35 | C3 | N/A | I Digital and I/O Ground. Ground for the I/O and core logic.GNDA, GNDCP, GNDD must be connected to a common ground area under the chip. | - | - | - |
| GNDA | 8 | E5 | N/A | I Analog Ground. Ground reference for the internal analog section. GNDA, GNDCP, GNDD must be connected to a common ground area under the chip. | - | - | - |
| GNDCP | 19,12, 15 | F2, F3, G5 | N/A | I Charge Pump Ground. Ground reference for the charge pump section. GNDA, GNDCP, GNDDmust be connected to a common ground area under the chip. | - | - | - |
| Charge Pump | Charge Pump | Charge Pump | Charge Pump | Charge Pump | Charge Pump | Charge Pump | Charge Pump |
| VCP_FILT+ VCP_FILT- | 21 18 | E2 G2 | VCP/ VP 1 | I/O Inverting Charge Pump Filter Connection. Power supply from the inverting charge pump that provides the positive/negative rail for the analog output. When operating in external VCP_FILT mode, these pins can directly take in supply voltage. | - | - | - |
| -VA | 9 | E6 | VA | O VA Negative Charge Pump Output. Negative charge pump output for DAC rail. It is derived from VA. | - | - | - |
| FLYP_VA FLYN_VA | 10 11 | F6 G6 | VA | O -VA Charge Pump Cap Positive/Negative Node. Positive/ negative nodes for the DAC negative charge pump's flying capacitor. | - | - | - |
| FLYP_VCP | 24 | E1 | VCP/ VP 1 | O -VCP Charge Pump Cap Positive Node. Positive node for the analog output negative charge pump's flying capacitor. | - | - | - |
| FLYC_VCP | 23 | F1 | VCP/ VP 1 | O -VCP Charge Pump Cap Center Node. Center node for the analog output negative charge pump's flying capacitor. | - | - | - |
| FLYN_VCP | 20 | G1 | VCP_ FILT± | O -VCP Charge Pump Cap Negative Node. Negative node for the analog output negative charge pump's flying capacitor. | - | - | - |
| Test | Test | Test | Test | Test | Test | Test | Test |
| TSO | 3 | B6 | N/A | I/O Test Output. | - | - | - |
| TSI | - | D3, F5 | Test Input. | - | - | - |
Electrical Characteristics
Test conditions (unless otherwise specified): Fig. 2-1 shows CS43198 connections; GNDD = GNDA = 0 V; all voltages with respect to ground.
| Parameters | Parameters | Minimum | Typical | Maximum | Units |
|---|---|---|---|---|---|
| VCP_FILT (No load connected to AOUTx) EXT_VCPFILT = 0 | VP_LDO Mode VCP_FILT+ pin (HV_EN = 1) VCP_FILT+ pin (HV_EN = 0) VCP_FILT- pin (HV_EN = 1) VCP_FILT- pin (HV_EN = 0) | - - - - | 3.0 2.6 -3.0 -2.6 | - - - - | V V V V |
| VCP Mode VCP_FILT+ pin VCP_FILT- pin | - - | VCP -VCP | - - | V V | |
| -VA | -VA pin | - | - VA | - | V |
| Other DC characteristics | FILT+ voltage | - | -0.35 | - | V |
| FILT- voltage | - | 0.35 | - | V | |
| Analog output current limiter on threshold. | - | 120 | 160 | mA | |
| VD power-on reset threshold (V POR ) Up Down | - - | 1.15 0.950 | - - | V V |
Absolute Maximum Ratings
Test conditions (unless otherwise specified): GNDD = GNDA= GNDCP = 0 V; all voltages with respect to ground.
| Parameters | Parameters | Symbol | Minimum | Maximum | Units |
|---|---|---|---|---|---|
| DC power supply | Analog | VA | -0.3 | 2.33 | V |
| Battery | VP | -0.3 | 6.3 | V | |
| Charge pump | VCP | -0.3 | 2.33 | V | |
| Filtered charge pump (positive) | VCP_FILT+ | -0.3 | 3.3 | V | |
| Filtered charge pump (negative) | VCP_FILT- | -3.3 | 0.3 | V | |
| Digital interface | VL | -0.3 | 2.33 | V | |
| Digital internal | VD | -0.3 | 2.33 | V | |
| Input current 1 | I in | - | ±10 | mA | |
| Ambient operating temperature (power applied) | T A | -50 | +115 | °C | |
| Storage temperature | T stg | -65 | +150 | °C |
Caution: Stresses beyond 'Absolute Maximum Ratings' levels may cause permanent damage to the device. These levels are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Table 3-2, 'Recommended Operating Conditions' is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins do not cause SCR latch-up.
Recommended Operating Conditions
Test conditions (unless otherwise specified): GNDD = GNDA = 0 V, all voltages with respect to ground.
| Parameters 1 | Parameters 1 | Parameters 1 | Symbol | Minimum | Maximum | Units |
|---|---|---|---|---|---|---|
| DC power supply | Analog | Analog | VA | 1.66 | 1.94 | V |
| DC power supply | Charge pump | Charge pump | VCP | 1.66 | 1.94 | V |
| DC power supply | Filtered charge pump 2 | EXT_VCPFLT = 1 | VCP_FILT+ | 2.85 | 3.15 | V |
| DC power supply | VCP_FILT- | -3.15 | -2.85 | V | ||
| DC power supply | Battery supply | HV_EN = 0, EXT_VCPFILT = 0 HV_EN = 1, EXT_VCPFILT = 0 EXT_VCPFILT = 1 | VP | 3.0 3.3 3.3 | 5.25 5.25 5.25 | V V V |
| DC power supply | Digital Interface | Digital Interface | VL | 1.66 | 1.94 | V |
| DC power supply | Digital Internal | Digital Internal | VD | 1.66 | 1.94 | V |
| External voltage applied to pin 3,4 | HP_DETECT pin VCP_FILT± domain pins 5 VL domain pins VA domain pins VP domain pins | V INHI V VCPF V VL V VA V VP | -0.3 - VCP_FILT- -0.3 - VCP_FILT- -0.3 -0.3 -0.3 | VP + 0.3 0.3 + VCP_FILT+ VL + 0.3 VA + 0.3 VP + 0.3 | V V V V V | |
| Ambient temperature | Ambient temperature | Ambient temperature | T A | -20 | +70 | C |
Thermal Information
The CS43198 comes in a compact QFN package, the underside of which reveals a large metal pad that serves as a thermal relief to provide maximum heat dissipation. This pad must mate with a matching copper pad on the PCB and must be electrically connected to ground. A series of vias must be used to connect this copper pad to one or more larger ground planes on other PCB layers. For best performance in split-ground systems, connect this thermal pad to GNDA.
Package Information
Figure 10-1. 40-Pin QFN Package Drawing
Table 10-1. 40-Pin QFN Package Dimensions
| Description | Description | Dim | Millimeters | Millimeters | Millimeters |
|---|---|---|---|---|---|
| Dim | Minimum | Nominal | Maximum | ||
| Total thickness | Total thickness | A | 0.7 | 0.75 | 0.8 |
| Stand off | Stand off | A1 | 0 | 0.035 | 0.05 |
| Mold thickness | Mold thickness | A2 | - | 0.55 | - |
| L/F thickness | L/F thickness | A3 | 0.203 REF | 0.203 REF | 0.203 REF |
| Lead width | Lead width | b | 0.15 | 0.2 | 0.25 |
| Body size | X | D | 5 BSC | 5 BSC | 5 BSC |
| Body size | Y | E | 5 BSC | 5 BSC | 5 BSC |
| Lead pitch | Lead pitch | e | 0.4 BSC | 0.4 BSC | 0.4 BSC |
| EP size | X | J | 3.4 | 3.5 | 3.6 |
| EP size | Y | K | 3.4 | 3.5 | 3.6 |
| Lead length | Lead length | L | 0.35 | 0.4 | 0.45 |
| Package edge tolerance | Package edge tolerance | aaa | 0.1 | 0.1 | 0.1 |
| Mold flatness | Mold flatness | bbb | 0.1 | 0.1 | 0.1 |
| Coplanarity | Coplanarity | ccc | 0.08 | 0.08 | 0.08 |
| Lead offset | Lead offset | ddd | 0.1 | 0.1 | 0.1 |
| Exposed pad offset | Exposed pad offset | eee | 0.1 | 0.1 | 0.1 |
- Dimensioning and tolerances per ASME Y 14.5M-1995.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| CS43198-CNZ | Cirrus Logic Inc. | — |
| CS43198-CNZR | Cirrus Logic Inc. | 40-WFQFN Exposed Pad |
| CS43198-CWZR | Cirrus Logic Inc. | — |
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