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CD40106B

Hex Schmitt Trigger Inverter (CMOS)

The CD40106B is a hex schmitt trigger inverter (cmos) from onsemi. View the full CD40106B datasheet below including key specifications, absolute maximum ratings.

CD40106B shares its datasheet with MM74Cl4, whose page lists every part number it covers.

Official CD40106B datasheet (PDF) — the source this page was extracted from.

Manufacturer

onsemi

Package

SOIC-14, TSSOP-14, SOEIAJ-14

CD40106B Key Specifications

ParameterValue
CompliancePb-Free, RoHS compliant; NLV prefix AEC-Q100 qualified, PPAP capable
Input Current±0.1 µA max at 25°C
Input ProtectionDouble diode protection on all inputs
Input Capacitance5.0 pF typ, 7.5 pF max
Number Of Channels6 Schmitt trigger inverters
Output Drive CapabilityTwo low-power TTL loads or one low-power Schottky TTL load
SOIC-14 Body DimensionsCASE 751A, narrow body
TSSOP-14 Body Dimensions4.90-5.10 mm x 4.30-4.50 mm body, 0.65 mm pitch, 1.20 mm max height
SOEIAJ-14 Body Dimensions9.90-10.50 mm x 5.10-5.45 mm body, 1.27 mm pitch, 2.05 mm max height
Storage Temperature Range-65°C to +150°C
Input/Output Voltage Range-0.5V to VDD + 0.5V
Supply Voltage Range (VDD)3.0V to 18V
Absolute Max Supply Voltage-0.5V to +18.0V
Operating Temperature Range-55°C to +125°C
Power Dissipation Per Package500 mW
Lead Temperature (8 S Soldering)260°C
Input/Output Current Per Pin (Max)±10 mA
Hysteresis Voltage VH (VDD=5V, 25°C)0.25V min, 0.6V typ, 1.0V max
Hysteresis Voltage VH (VDD=10V, 25°C)0.6V min, 0.7V typ, 1.2V max
Hysteresis Voltage VH (VDD=15V, 25°C)0.3V min, 1.1V typ, 1.5V max
Positive-Going Threshold VT+ (25°C, Typ)3.3V to 5.3V (VDD=5V typ 2.9V range; 5.3V at 10V, 8.0V at 15V, per table)
Output Drive (Sink, VOL=0.4V, VDD=5V, 25°C)0.51 mA min
Output Drive (Source, VOH=4.6V, VDD=5V, 25°C)-0.51 mA min
Propagation Delay (CL=50pF, 25°C, VDD=5V/10V/15V)125 ns / 50 ns / 40 ns typ; 250 ns / 100 ns / 80 ns max
Output Rise/Fall Time (CL=50pF, 25°C, VDD=5V/10V/15V)100 ns / 50 ns / 40 ns typ; 200 ns / 100 ns / 80 ns max
Quiescent Current (Per Package, 25°C, VDD=5V/10V/15V)0.25 µA / 0.5 µA / 1.0 µA max

CD40106B Overview

Part: MC14584B — onsemi

Type: Hex Schmitt Trigger (CMOS)

Description: Hex CMOS Schmitt trigger with 3.0–18 V supply range, built from MOS P-channel and N-channel enhancement mode devices, for squaring up slowly changing waveforms and improving noise immunity.

Operating Conditions:

  • Supply voltage: 3.0–18 V
  • Ambient temperature: -55 to +125 °C
  • Inputs and outputs should be constrained to VSS ≤ (Vin or Vout) ≤ VDD

Absolute Maximum Ratings:

  • Max supply voltage (VDD): -0.5 to +18.0 V
  • Input/output voltage: -0.5 to VDD + 0.5 V
  • Input/output current per pin: ±10 mA
  • Power dissipation per package: 500 mW (derate -7.0 mW/°C from 65 °C to 125 °C for D/DT packages)
  • Storage temperature: -65 to +150 °C
  • Lead temperature (8-second soldering): 260 °C

Key Specs:

  • Positive-going threshold VT+ at 25 °C: typ 3.3 V (VDD = 5 V), 5.3 V (10 V), 8.0 V (15 V)
  • Negative-going threshold VT- at 25 °C: typ 1.8 V (VDD = 5 V), 3.0 V (10 V), 4.6 V (15 V)
  • Hysteresis VH at 25 °C: typ 0.6 V (5 V), 0.7 V (10 V), 1.1 V (15 V)
  • Output drive at 25 °C, VDD = 5 V: IOH -2.4 mA min (VOH = 2.5 V), IOL 0.51 mA min (VOL = 0.4 V)
  • Quiescent current per package at 25 °C: typ 0.0005 mA (10 V), 0.0010 mA (15 V)
  • Input current at VDD = 15 V: ±0.1 µA max at -55 and 25 °C, ±1.0 µA max at 125 °C
  • Input capacitance: 5.0 pF typ
  • Propagation delay at 25 °C, CL = 50 pF: typ 125 ns (5 V), 50 ns (10 V), 40 ns (15 V)
  • Output rise/fall time at 25 °C, CL = 50 pF: typ 100 ns (5 V), 50 ns (10 V), 40 ns (15 V)

Features:

  • Drives two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range
  • Supply voltage range of 3.0 Vdc to 18 Vdc
  • Double diode protection on all inputs
  • Can replace the MC14069UB hex inverter for enhanced noise immunity
  • MC14106B available for greater hysteresis (pin-for-pin replacement for CD40106B and MM74C14)
  • NLV prefix for automotive and other applications requiring unique site and control change requirements; AEC-Q100 qualified and PPAP capable
  • Pb-free and RoHS compliant

Applications:

  • Squaring up slowly changing waveforms
  • Noise-immune gate applications
  • Low-power logic designs

Package:

  • SOIC-14
  • TSSOP-14
  • SOEIAJ-14 (discontinued)

CD40106B Features

  • Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load over the Rated Temperature Range
  • Supply Voltage Range = 3.0 Vdc to 18 Vdc
  • Double Diode Protection on All Inputs
  • For Greater Hysteresis, Use MC14106B which is Pin-for-Pin Replacement for CD40106B and MM74Cl4
  • Can Be Used to Replace MC14069UB
  • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable
  • These Devices are Pb-Free and are RoHS Compliant

CD40106B Pin Configuration

CD40106B Absolute Maximum Ratings

SymbolParameterValueUnit
V DDDC Supply Voltage Range-0.5 to +18.0V
V in , V outInput or Output Voltage Range (DC or Transient)-0.5 to V DD + 0.5V
I in , I outInput or Output Current (DC or Transient) per Pin± 10mA
P DPower Dissipation, per Package (Note 1)500mW
T AAmbient Temperature Range-55 to +125° C
T stgStorage Temperature Range-65 to +150° C
T LLead Temperature (8-Second Soldering)260° C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Operating the device outside its recommended conditions, but still within its maximum rated limits may not cause immediate damage. However, doing so can lead to reduced performance, unpredictable behavior, and potentially shorten the device's lifespan or reliability.

  1. Temperature Derating:

'D/DT' Packages: -7.0 mW/ ° C From 65 ° C To 125 ° C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V in and V out should be constrained to the range V SS ≤ (V in or V out ) ≤ V DD .

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open.

Variants on the same datasheet

These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.

Part NumberManufacturerPackage
MC14069UBonsemi—
MC14106Bonsemi—
MC14584Bonsemi—
MM74Cl4onsemi—

Other Integrated Circuits

All Integrated Circuits datasheetsAll onsemi datasheets (337)

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