AT25SL128A-MHE-T
128-Mbit SPI Serial NOR FlashThe AT25SL128A-MHE-T is a 128-mbit spi serial nor flash from Renesas Electronics. View the full AT25SL128A-MHE-T datasheet below including key specifications, electrical characteristics.
AT25SL128A-MHE-T shares its datasheet with AT25SL128A, whose page lists every part number it covers.
Official AT25SL128A-MHE-T datasheet (PDF) — the source this page was extracted from.
Manufacturer
Renesas ElectronicsCategory
Memory ICsPackage
DFN-8 5x6mm
Lifecycle
NRND (Last Updated: 5 days ago)
AT25SL128A-MHE-T Key Specifications
| Parameter | Value |
|---|---|
| Clock Frequency | 104 MHz |
| DigiKey Programmable | Not Verified |
| Export Control Classification Number (ECCN) Code | 3A991 |
| Harmonized Tariff Schedule (HTS) Code | 8542.32.00.51 |
| Height | 600 µm |
| Height - Seated (Max) | 600 µm |
| Introduction Date | 2018-04-08 |
| Length | 6 mm |
| Lifecycle Status | NRND (Last Updated: 5 days ago) |
| LTB Date | 2026-06-17 |
| LTD Date | 2026-12-17 |
| Manufacturer Lifecycle Status | NOT RECOMMENDED FOR NEW DESIGNS (Last Updated: 5 days ago) |
| Max Operating Temperature | 85 °C |
| Max Supply Current | 27 mA |
| Max Supply Voltage | 2 V |
| Memory Format | FLASH |
| Memory Interface | SPI |
| Memory Organization | 16M x 8 |
| Memory Size | 128Mbit |
| Memory Type | FLASH |
| Memory Type | Non-Volatile |
| Min Operating Temperature | -40 °C |
| Min Supply Voltage | 1.7 V |
| Mounting Type | Surface Mount |
| MSL | 1 |
| Nominal Supply Voltage (DC) | 1.8 V |
| Number of Circuits | 1 |
| Number of Terminals | 8 |
| Operating Temperature | -40°C ~ 85°C (TA) |
| Package / Case | 8-UDFN Exposed Pad |
| Package Quantity | 6000 |
| Packaging | Tape & Reel |
| Part Family | AT25SL128A |
| Pitch | 1.27 mm |
| REACH SVHC | Yes |
| RoHS | Compliant |
| Supplier Device Package | 8-UDFN (5x6) |
| Diode Technology | FLASH |
| Temperature Grade | Industrial |
| Terminal Pitch | 1.27 mm |
| Supply Voltage | 1.7V ~ 2V |
| Width | 5 mm |
| Write Cycle Time | 150µs, 5ms |
AT25SL128A-MHE-T Overview
Part: AT25SL128A
Type: 128-Mbit SPI Serial Flash Memory
Description: 1.7–2.0 V, 128-Mbit SPI serial Flash memory with Dual I/O, Quad I/O, and QPI support running up to 133 MHz fast read.
Operating Conditions:
- Supply voltage: 1.7 to 2.0 V
- Operating temperature: -40 to +85 °C
Key Specs:
- Density: 128 Mbit (16 MB)
- Max clock frequency: 133 MHz (Fast Read)
- Standby current: 10 μA (typical)
- Deep power-down current: 2 μA (typical)
- Page program time: 0.6 ms (typical, 1 to 256 bytes)
- Block erase time (4 kB): 60 ms (typical)
- Block erase time (32 kB / 64 kB): 200 ms / 350 ms (typical)
- Chip erase time: 80 s (typical)
- Endurance: 100,000 program/erase cycles
- Data retention: 20 years
Features:
- SPI Modes 0 and 3 support
- Dual output (1-1-2), Quad output (1-1-4), Quad I/O / XiP (1-4-4, 0-4-4), and QPI (4-4-4) operation
- Continuous read with 8/16/32/64-byte wrap
- Flexible erase architecture (4 kB, 32 kB, 64 kB block erase, and chip erase)
- Page/byte programming from 1 to 256 bytes
- Erase and program suspend/resume support
- Serial Flash Discoverable Parameter (SFDP) register
- 4-kbit secured OTP area
- User-definable memory protection and hardware protection via WP pin
Applications:
- High-volume industrial applications
- Consumer electronics
- Connected applications
- Code shadow and Execute in Place (XiP) program memory
Package:
- 8-pad DFN (6 x 5 x 0.6 mm)
- 8-lead SOIC (208-mil)
- 21-ball WLCSP
- 21-ball low-profile WLCSP
AT25SL128A-MHE-T Features
- Single voltage operation with range of 1.7 V - 2.0 V
- Serial Peripheral Interface (SPI) compatible support
- Supports SPI Modes 0 and 3
- Supports Dual SPI dual output operations (1-1-2)
- Supports Quad output operations (1-1-4)
- Supports Quad I/O / XiP operations (1-4-4, 0-4-4)
- Supports QPI I/O operations (4-4-4)
- Read Operations
- Fast read up to 133 MHz
- Continuous read with 8/16/32/64-byte wrap
- Flexible erase architecture time
- Block erase 4 kB: 60 ms (Typical)
- Block erase 32 kB and 64 kB: 200 ms and 350 ms (Typical)
- Full chip erase: 80 s (typical)
- Flexible Programming and time
- Page/byte program: from 1 to 256 bytes
- Page program time 0.6 ms (typical)
- Erase program suspend resume
- JEDEC Manufacturer and Device ID
- Memory protection support
- User-definable protected area at start or end of memory array
- Enable/disable protection with WP pin
- Serial Flash Discoverable Parameter (SFDP) register
- Low power dissipation
- 10 μA Standby Current (Typical)
- 2 μA Deep Power-Down Current (Typical)
- Endurance 100,000 program/erase cycles
- Data retention: 20 years
- Temperature Range: Industrial (-40 °C to +85 °C)
- Industry Standard green (Pb/Halide-free/RoHS compliant) package options
- 8-pad DFN (6 x 5 x 0.6 mm)
- 8-lead SOIC (208-mil)
- 21-ball WLCSP
- 21-ball low-profile WLCSP
AT25SL128A-MHE-T Pin Configuration
The following figures show the available package types.
A
Figure 2. 21-WLCSP (Bottom View)
Figure 3. 8-WSOIC (Top View)
During all operations, V CC must be held stable and within the specified valid range, V CC (min) to V CC (max). All of the input and output signals must be held high or low (according to voltages of V IH , V OH , V IL , or V OL .
Figure 3. 8-WSOIC (Top View)
Table 1. Pin Descriptions
| Symbol | Name and Function | Asserted State | Type |
|---|---|---|---|
| CS | CHIP SELECT When this input signal is high, the device is deselected and serial data output pins are at high impedance. Unless an internal program, erase, or write status register cycle is in progress, the device is in the Standby Power Mode (this is not the Deep Power- Down mode). Driving Chip Select (CS) low enables the device, placing it in the active power mode. After power-up, a falling edge on Chip Select (CS) is required before issuing any command. | Low | Input |
| SCK | SERIAL CLOCK This input signal provides the timing for the serial interface. Commands, addresses, or data present at serial data input are latched on the rising edge of Serial Clock (SCK). Data are shifted out on the falling edge of the Serial Clock (SCK). | - | Input |
| SI (I/O 0 ) | SERIAL INPUT The SI pin is used to shift data into the device. The SI pin is used for all data input, including command and address sequences. Data on the SI pin is always latched in on the rising edge of SCK. With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin (I/O 0 ) in conjunction with other pins to allow two or four bits of data on I/O 3-0 to be clocked in on every falling edge of SCK To maintain consistency with the SPI nomenclature, the SI (I/O 0 ) pin is referenced as the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes, in which case it is referenced as I/O 0. Data present on the SI pin is ignored whenever the device is deselected (CS is deasserted). | - | Input/Output |
| SO (I/O 1 ) | SERIAL OUTPUT The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in conjunction with other pins to allow two bits of data on (I/O 1-0 ) to be clocked in on every falling edge of SCK To maintain consistency with the SPI nomenclature, the SO (I/O 1 ) pin is referenced as the SO pin unless specifically addressing the Dual-I/O modes, in which case it is referenced as I/O 1. The SO pin is in a high-impedance state whenever the device is deselected (CS is deasserted). | - | Input/Output |
| WP (I/O 2 ) | WRITE PROTECT The Write Protect (WP) pin can be used to protect the Status Register against data modification. Used with the Status Register's Block Protect (SEC, TB, BP2, BP1, and BP0) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The WPpin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the WP pin (Hardware Write Protect) function is not available because this pin is used for IO 2 . The WPpin does not have an internal pull- up; thus, it must be either driven or, if not used, pulled up with an external resistor to V CC . | - | Input/Output |
Table 1. Pin Descriptions
Table 1. Pin Descriptions (Continued)
| Symbol | Name and Function | Asserted State | Type |
|---|---|---|---|
| HOLD (I/O 3 ) | HOLD The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin are ignored, and the SO pin is placed in a high-impedance state. The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold condition to start. AHold condition pauses serial communication only; it does not have an effect on internally self-timed operations such as a program or erase cycle. With the Quad-Input Byte/Page Program command, the HOLD pin becomes an input pin (I/O 3 ) and, with other pins, allows four bits (on I/O 3-0 ) of data to be clocked in on every rising edge of SCK. With the Quad-Output Read commands, the HOLD Pin becomes an output pin (I/O 3 ) in conjunction with other pins to allow four bits of data on (I/O3 3-0 ) to be clocked in on every falling edge of SCK. To maintain consistency with SPI nomenclature, the HOLD (I/O 3 ) pin is referenced as the HOLD pin unless specifically addressing the Quad-I/O modes, in which case it is referenced as I/O 3. The HOLD pin does not have an internal pull-up; thus, it must be either driven or, if not used, pulled up with an external resistor to V CC . See Figure 1 and Figure 2 for the pin configuration of Quad I/O and QPI operation. | - | Input/Output |
| V CC | DEVICE POWER SUPPLY V CC is the supply voltage. It is the single voltage used for all device functions, including read, program, and erase. The V CC pin is used to supply the source voltage to the device. Operations at invalid V CC voltages can produce spurious results; do not attempt this. | - | Power |
| GND | GROUND GND is the reference for the V CC supply voltage. The ground reference for the power supply. Connect GND to the system ground. | - | Power |
Table 1. Pin Descriptions (Continued)
AT25SL128A-MHE-T Electrical Characteristics
| Parameter | Symbol | Conditions | Range | Unit |
|---|---|---|---|---|
| Supply Voltage | V CC | -0.6 to V CC + 0.4 | V | |
| Voltage Applied to Any Pin | V IO | Relative to Ground | -0.6 to V CC + 0.4 | V |
| Transient Voltage on any Pin | V IOT | <20 ns Transient Relative to Ground | -1.0 V to V CC + 1.0 V | V |
| Storage Temperature | T STG | -65 to + 150 | ° C | |
| Lead Temperature | T LEAD | See Note (2) | ° C | |
| Electrostatic Discharge Voltage | V ESD | Human Body Model (3) | -2000 to +2000 | V |
Notes:
- Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. The Absolute Maximum Ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability. Voltage extremes referenced in the Absolute Maximum Ratings are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time.
- Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
- 3 . JEDEC Std JESD22-A114A (C1 = 100 pF , R1 = 1500 ohms , R2 = 500 ohms).
Variants on the same datasheet
These parts have exact links to the same datasheet. They are candidates to compare, not verified drop-in replacements; check package, pinout and electrical limits.
| Part Number | Manufacturer | Package |
|---|---|---|
| AT25SL128A | Renesas Electronics | — |
| AT25SL128A-SHE-T | Renesas Electronics | 8-pad DFN |
| AT25SL128A-SUE-T | Renesas Electronics | — |
| AT25SL128A-UIUE | Renesas Electronics | WLCSP-21 |
| AT25SL128A-UIUE-T | Renesas Electronics | WLCSP-21 |
| AT25SL128A-UUE-T | Renesas Electronics | WLCSP-21 |
Other Memory ICs
- CH347T – WCH, Serial SLC NAND Flash Memory
- M24512-DFMC6TG – STMicroelectronics, EEPROM
- ST25DV04KC-JF6L3 – STMicroelectronics, Dynamic NFC/RFID Tag IC
- ZD25WQ16CTIGT – Zetta, Serial Multi I/O NOR Flash
- W25Q32JVSSIQ – Winbond
- 23A1024 – Microchip Technology, Serial SRAM
- 23LC1024 – Microchip Technology, Serial SRAM
- 23LC1024-I/P – Microchip Technology, Serial SRAM
All Memory ICs datasheetsAll Renesas Electronics datasheets (42)
Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.
Ask your AI agent about the AT25SL128A-MHE-T
Connect SheetsData to Claude, Cursor, Codex or any MCP client and your agent reads this datasheet for you: pinout, limits, register maps and design checks, with the numbers taken from the PDF.
claude mcp add --transport http sheetsdata https://mcp.sheetsdata.com/mcp
Then ask: "Can the AT25SL128A-MHE-T run from my 12 V rail? Check it against the datasheet limits."
Create a free account $2 of usage every month, no card needed.