Skip to main content

We use cookies to understand how you use our site and improve your experience. See our Privacy Policy.

AD9833

Programmable Waveform Generator (DDS)

The AD9833 is a programmable waveform generator (dds) from Analog Devices. View the full AD9833 datasheet below including key specifications.

Official AD9833 datasheet (PDF) — the source this page was extracted from.

Manufacturer

Analog Devices

Category

Integrated Circuits

Package

MSOP-10

AD9833 Key Specifications

ParameterValue
PackagingTube
Standard Pack Qty50
DNL±0.5 LSB typ
INL±1.0 LSB typ
SNR55 dB min, 60 dB typ (fMCLK = 25 MHz)
QualificationAEC-Q100 (automotive grade variant)
DAC Resolution10 bits
Supply Voltage2.3V to 5.5V
DAC Update Rate25 MSPS
Output WaveformsSine, triangular, square
Serial Interface3-wire SPI (up to 40 MHz clock)
Power Consumption12.65 mW at 3 V
Frequency Resolution28-bit (0.1 Hz at 25 MHz reference clock)
Operating Temperature-40°C to +105°C
Output Frequency Range0 MHz to 12.5 MHz
Phase Register Resolution12 bits

AD9833 Overview

Part: AD9833 — Analog Devices

Type: Programmable Waveform Generator (DDS)

Description: Low power, 12.65 mW, 2.3–5.5 V programmable waveform generator producing sine, triangular, and square wave outputs up to 12.5 MHz with 28-bit frequency resolution and a 3-wire SPI interface.

Operating Conditions:

  • Supply voltage: 2.3–5.5 V
  • Operating temperature: -40 to +105 °C
  • Master clock: 25 MHz max (MCLK period 40 ns min); SPI clock up to 40 MHz (SCLK period 25 ns min)

Absolute Maximum Ratings:

  • Max supply voltage: VDD to AGND/DGND -0.3 V to +6 V
  • Digital/analog I/O voltage: -0.3 V to VDD + 0.3 V
  • Max junction temperature: 150 °C
  • Storage temperature: -65 to +150 °C

Key Specs:

  • DAC resolution: 10 bits, update rate 25 MSPS max
  • Supply current IDD: 4.5 mA typ, 5.5 mA max (fMCLK = 25 MHz, fOUT = fMCLK/4096)
  • Sleep mode current: 0.5 mA typ (DAC powered down, MCLK running)
  • SNR: 55 dB min, 60 dB typ (AD9833BRMZ, fMCLK = 25 MHz, fOUT = fMCLK/4096)
  • THD: -66 dBc typ, -56 dBc max (AD9833BRMZ, fMCLK = 25 MHz)
  • SFDR: -60 dBc wideband typ, -78 dBc narrow-band (±200 kHz) typ (fMCLK = 25 MHz, fOUT = fMCLK/50)
  • INL ±1.0 LSB typ, DNL ±0.5 LSB typ
  • VOUT: 38 mV min, 0.65 V max (typ); wake-up time 1 ms typ; digital input current 10 μA max

Features:

  • Digitally programmable frequency and phase
  • 0 MHz to 12.5 MHz output frequency range
  • 28-bit resolution: 0.1 Hz at 25 MHz reference clock
  • Sinusoidal, triangular, and square wave outputs
  • No external components required
  • 3-wire SPI interface
  • Power-down (SLEEP) option
  • AEC-Q100 qualified for automotive applications

Applications:

  • Frequency stimulus/waveform generation
  • Liquid and gas flow measurement
  • Proximity, motion, and defect detection sensing
  • Line loss/attenuation
  • Test and medical equipment
  • Sweep/clock generators
  • Time domain reflectometry (TDR)

Package:

  • 10-lead MSOP

AD9833 Features

Digitally programmable frequency and phase 12.65 mW power consumption at 3 V 0 MHz to 12.5 MHz output frequency range 28-bit resolution: 0.1 Hz at 25 MHz reference clock Sinusoidal, triangular, and square wave outputs 2.3 V to 5.5 V power supply No external components required 3-wire SPI interface Extended temperature range: -40°C to +105°C Power-down option 10-lead MSOP package AEC-Q100 qualified for automotive applications

AD9833 Applications

Frequency stimulus/waveform generation Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Line loss/attenuation Test and medical equipment Sweep/clock generators

Time domain reflectometry (TDR) applications

AD9833 Pin Configuration

02704-005

Figure 5. Pin Configuration

Pin No.MnemonicDescription
1COMPDAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
2VDDPositive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5V regulator is also supplied fromVDD.VDD can have a value from 2.3V to 5.5 V. A0.1 μF and a 10 μF decoupling capacitor should be connected betweenVDD and AGND.
3CAP/2.5VThe digital circuitry operates from a 2.5V power supply. This 2.5V is generated fromVDD using an on-board regulator whenVDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is connected from CAP/2.5V to DGND. IfVDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to VDD.
4DGNDDigital Ground.
5MCLKDigital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. This clock determines the output frequency accuracy and phase noise.
6SDATASerial Data Input. The 16-bit serial data-word is applied to this input.
7SCLKSerial Clock Input. Data is clocked into the AD9833 on each falling edge of SCLK.
8FSYNCActive Low Control Input. FSYNC is the frame synchronization signal for the input data.When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device.
9AGNDAnalog Ground.
10VOUTVoltage Output. The analog and digital output from the AD9833 is available at this pin. An external load resistor is not required because the device has a 200 Ωresistor on-board.

Other Integrated Circuits

All Integrated Circuits datasheetsAll Analog Devices datasheets (713)

Data on this page is extracted from publicly available manufacturer datasheets using automated tools including AI. It may contain errors or omissions. Always verify specifications against the official manufacturer datasheet before making design or purchasing decisions. See our Terms of Service. Rights holders can submit a takedown request.

Ask your AI agent about the AD9833

Connect SheetsData to Claude, Cursor, Codex or any MCP client and your agent reads this datasheet for you: pinout, limits, register maps and design checks, with the numbers taken from the PDF.

claude mcp add --transport http sheetsdata https://mcp.sheetsdata.com/mcp

Then ask: "Can the AD9833 run from my 12 V rail? Check it against the datasheet limits."

Create a free account $2 of usage every month, no card needed.