STM32F407XXI

Part: STM32F405xx, STM32F407xx (STMicroelectronics)

Type: ARM Cortex-M4 Microcontroller

Description: 32-bit ARM Cortex-M4 MCU with FPU, operating at up to 168 MHz, featuring up to 1 MB Flash, 192+4 KB SRAM, USB OTG HS/FS, Ethernet, and a wide range of communication and analog peripherals.

Operating Conditions:

• Supply voltage: 1.8–3.6 V
• Operating temperature: -40 to +125 °C (Junction)
• Max CPU frequency: 168 MHz

Absolute Maximum Ratings:

• Max supply voltage: 4.0 V
• Max continuous current: 120 mA (Total current into VDD_x, VDDA, VDDSD, VDDUSB)
• Max storage temperature: -65 to +150 °C

Key Specs:

• Core: ARM 32-bit Cortex-M4 CPU with FPU
• Max CPU frequency: 168 MHz
• Flash memory: Up to 1 Mbyte
• SRAM: Up to 192+4 Kbytes (including 64 KB CCM RAM)
• A/D converters: 3x 12-bit, 2.4 MSPS (up to 24 channels)
• D/A converters: 2x 12-bit
• Timers: Up to 17 (twelve 16-bit, two 32-bit)
• Communication interfaces: Up to 15 (I2C, USART/UART, SPI, CAN, SDIO, USB, Ethernet)

Features:

• Adaptive real-time accelerator (ART Accelerator™) for 0-wait state Flash execution
• Flexible static memory controller (FSMC)
• USB 2.0 full-speed/high-speed device/host/OTG controller
• 10/100 Ethernet MAC with dedicated DMA
• 8- to 14-bit parallel camera interface
• True random number generator

Applications:

• null

Package:

• WLCSP90
• LQFP64
• LQFP100
• LQFP144
• UFBGA176+25
• LQFP176

• Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories
  • Up to 1 Mbyte of Flash memory
  • Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled memory) data RAM
  • Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories
• LCD parallel interface, 8080/6800 modes
• Clock, reset and supply management
  • 1.8 V to 3.6 V application supply and I/Os
  • POR, PDR, PVD and BOR
  • 4-to-26 MHz crystal oscillator
  • Internal 16 MHz factory-trimmed RC (1% accuracy)
  • 32 kHz oscillator for RTC with calibration
  • Internal 32 kHz RC with calibration
• Low power
  • Sleep, Stop and Standby modes
  • VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
• Up to 17 timers: up to twelve 16-bit and two 32 bit timers up to 168 MHz, each with up to 4

IC/OC/PWM or pulse counter and quadrature (incremental) encoder input

• Debug mode
  • Serial wire debug (SWD) & JTAG interfaces
  • Cortex-M4 Embedded Trace Macrocell™
• Up to 140 I/O ports with interrupt capability
• Up to 136 fast I/Os up to 84 MHz
  • Up to 138 5 V-tolerant I/Os
• Up to 15 communication interfaces
  • Up to 3 × I2C interfaces (SMBus/PMBus)
  • Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)
  • Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock
  • 2 × CAN interfaces (2.0B Active)
  • SDIO interface
• Advanced connectivity
  • USB 2.0 full-speed device/host/OTG controller with on-chip PHY
  • USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
  • 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit parallel camera interface up to 54 Mbytes/s
• True random number generator
• CRC calculation unit
• 96-bit unique ID
• RTC: subsecond accuracy, hardware calendar

Table 1. Device summary

Reference	Part number
STM32F405xx	STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE
STM32F407xx	STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 4948 47 46 45 44 43 42 41 40 39 38 37 36 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBAT PC14 PC15 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0_WKUP PA1 PA2 VDD PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD LQFP64 ai18493b PC13 PH0 PH1 VSS

Figure 12. STM32F40x LQFP64 pinout

ai18495c

100 99 98 97 96 95 94 92 91 90 89 88 87 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE2 PE3 PE4 PE5 PE6 VBAT PC14 PC15 VSS VDD PH0 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 VDD VSS VCAP_2 PA13 PA12 PA 11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LQFP100 PC13 PH1

Figure 13. STM32F40x LQFP100 pinout

Figure 14. STM32F40x LQFP144 pinout

Figure 15. STM32F40x LQFP176 pinout

Figure 16. STM32F40x UFBGA176 ballout

15	14	13	12	11	10	9	8	7	6	5	4	3 3	2	1
PA13	PA14	PA15	PC12	PD7	PB3	PB4	PG13	PG14	PB5	PB8	PE0	PE1	PE2	PE3
PA12	PC10	PC11	PD0	PD6	PG10	PG11	PG12	PG15	PB6	PB7	PB9	PE6	PE5	PE4
PA11	PI2	PI3	PD1	PD5	PG9	VDD	VDD	VDD	PDR_ON	VDD	PI5	PI6	PI7	VBAT
PA10	PI1	PH15	PD2	PD3	PD4	VSS	VSS	VSS	BOOT0	VSS	PI4	PI9	PI8	PC13
PA9	PI0	PH14	PH13								PI11	PI10	PF0	PC14
PA8	PC9	VCAP_2	VSS		VSS	VSS	VSS	VSS	VSS		PH2	VDD	VSS	PC15
PC7	PC8	VDD	VSS		VSS	VSS	VSS	VSS	VSS		PH3	VDD	VSS	PH0
PC6	PG8	VDD	VSS		VSS	VSS	VSS	VSS	VSS		PH4	PF1	PF2	PH1
PG6	PG7	VDD	VDD		VSS	VSS	VSS	VSS	VSS		PH5	PF4	PF3	NRST
PG3	PG4	PG5	PH12		VSS	VSS	VSS	VSS	VSS		VDD	PF5	PF6	PF7
PG2	PD15	PH10	PH11								BYPASS_ REG	PF8	PF9	PF10
PD13	PD14	PH9	PH8	PH6	VCAP_1	VSS	VSS	PG1	PB2	PC3	PC2	PC1	PC0	VSSA
PD10	PD11	PD12	PH7	PE13	VDD	VDD	VDD	PG0	PF13	PC4	PA4	PA0	PA1	VREF-
PD8	PD9	PB13	PB12	PE14	PE11	PE9	PE8	PF15	PF12	PC5	PA5	PA6	PA2	VREF+
PB15	PB14	PB11	PB10	PE15	PE12	PE10	PE7	PF14	PF11	PB0	PB1	PA7	PA3	VDDA

1. This figure shows the package top view.

Figure 17. STM32F40x WLCSP90 ballout

	10	9	8	7	6	5	4	3	2	1
A	VBAT	PC13	PDR_ON	BOOT0	PB4	PD7	PD4	PC12	PA14	VDD
B	PC14	PC15	VDD	PB7	PB3	PD6	PD2	PA15	PI1	VCAP_2
C	PA0	VSS	PB9	PB6	PD5	PD1	PC11	PI0	PA12	PA11
D	PC2	BYPASS_REG	PB8	PB5	PD0	PC10	PA13	PA10	PA9	PA8
E	PC0	PC3	VSS	VSS	VDD	VSS	VDD	PC9	PC8	PC7
F	PH0	PH1	PA1	VDD	PE10	PE14	VCAP_1	PC6	PD14	PD15
G	NRST	VDDA	PA5	PB0	PE7	PE13	PE15	PD10	PD12	PD11
H	VSSA	PA3	PA6	PB1	PE8	PE12	PB10	PD9	PD8	PB15
J	PA2	PA4	PA7	PB2	PE9	PE11	PB11	PB12	PB14	PB13

Table 6. Legend/abbreviations used in the pinout table

Name	Abbreviation	Definition
Pin name		specified in brackets below the pin name, the pin function during and after as the actual pin name
	S	Supply pin
Pin type	I	Input only pin
	I/O	Input / output pin
	FT	5 V tolerant I/O
I/O structure	TTa	3.3 V tolerant I/O directly connected to ADC
i/O structure	B	Dedicated BOOT0 pin
	RST	Bidirectional reset pin with embedded weak pull-up resistor
Notes	Unless otherwise	specified by a note, all I/Os are set as floating inputs during and after reset
Alternate functions	Functions selected	d through GPIOx_AFR registers
Additional functions	Functions directly	selected/enabled through peripheral registers

Table 7. STM32F40x pin and ball definitions

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
-	-	1	1
-	-	2	2
-	-	3	3
-	-	4	4
-	-	5	5
1	A10	6	6
-	-	-	-
2	A9	7	7
3	B10	8	8
4	B9	9	9
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	10

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
-	-	-	11
-	-	-	12
-	-	-	13
-	-	-	14
-	-	-	15
-	C9	10	16
-	B8	11	17
-	-	-	18
-	-	-	19
-	-	-	20
-	-	-	21
-	-	-	22
5	F10	12	23
6	F9	13	24
7	G10	14	25
8	E10	15	26
9	-	16	27
10	D10	17	28

Table 7. STM32F40x pin and ball definitions (continued)

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
11	E9	18	29
-	-	19	30
12	H10	20	31
-	-	-	-
-	-	21	32
13	G9	22	33
14	C10	23	34
15	F8	24	35
16	J10	25	36
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
17	H9	26	37
18	E5	27	38
	D9
19	E4	28	39
20	J9	29	40
21	G8	30	41
22	H8	31	42
23	J8	32	43
24	-	33	44
25	-	34	45
26	G7	35	46

Table 7. STM32F40x pin and ball definitions (continued)

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
27	H7	36	47
28	J7	37	48
-	-	-	49
-	-	-	50
-	-	-	51
-	-	-	52
-	-	-	53
-	-	-	54
-	-	-	55
-	-	-	56
-	-	-	57
-	G6	38	58
-	H6	39	59
-	J6	40	60
-	-	-	61
-	-	-	62
-	F6	41	63
-	J5	42	64
-	H5	43	65
-	G5	44	66

Table 7. STM32F40x pin and ball definitions (continued)

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
-	F5	45	67
-	G4	46	68
29	H4	47	69
30	J4	48	70
31	F4	49	71
32	-	50	72
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-
-	-	-	-

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
33	J3	51	73
34	J1	52	74
35	J2	53	75
36	H1	54	76
-	H2	55	77
-	H3	56	78
-	G3	57	79
-	G1	58	80
-	G2	59	81

Table 7. STM32F40x pin and ball definitions (continued)

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
-	-	60	82
-	-	-	83
-	-	-	84
-	F2	61	85
-	F1	62	86
-	-	-	87
-	-	-	88
-	-	-	89
-	-	-	90
-	-	-	91
-	-	-	92
-	-	-	93
-	-	-	94
-	-	-	95
37	F3	63	96
38	E1	64	97
39	E2	65	98

	ı	Pin r	numb	er
LQFP64	WLCSP90	LQFP100	LQFP144	UFBGA176
40	E3	66	99	F14
41	D1	67	100	F15
42	D2	68	101	E15
43	D3	69	102	D15
44	C1	70	103	C15
45	C2	71	104	B15
46	D4	72	105	A15
47	B1	73	106	F13
-	E7	74	107	F12
48	E6	75	108	G13
-	-	-	-	E12
-	-	-	ı	E13
-	-	-	-	D13
-	C3	-	-	E14

Table 7. STM32F40x pin and ball definitions (continued)

	F	Pin r	numb	er						definitions (continued)
LQFP64	WLCSP90	LQFP100	LQFP144	UFBGA176	LQFP176	Pin name (function after reset) (1)	Pin type	I / O structure	Notes	Alternate functions
-	B2	-	-	D14	132	PI1	I/O	FT		SPI2_SCK / I2S2_CK / DCMI_D8/ EVENTOUT
-	ı	1	ı	C14	133	PI2	I/O	FT		TIM8_CH4 /SPI2_MISO / DCMI_D9 / I2S2ext_SD/ EVENTOUT
-	-	-	1	C13	134	PI3	I/O	FT		TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT
-	-	-	-	D9	135	VSS	S
-	-	-	-	C9	136	VDD	S
49	A2	76	109	A14	137	PA14 (JTCK/SWCLK)	I/O	FT		JTCK-SWCLK/ EVENTOUT
50	BЗ	77	110	A13	138	PA15 (JTDI)	I/O	FT		JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ET R / SPI1_NSS / EVENTOUT
51	D5	78	111	B14	139	PC10	I/O	FT		SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT
52	C4	79	112	B13	140	PC11	I/O	FT		UART4_RX/SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT
53	A3	80	113	A12	141	PC12	I/O	FT		UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI /I2S3_SD / USART3_CK/ EVENTOUT
-	D6	81	114	B12	142	PD0	I/O	FT		FSMC_D2/CAN1_RX/ EVENTOUT
-	C5	82	115	C12	143	PD1	I/O	FT		FSMC_D3 / CAN1_TX/ EVENTOUT
54	B4	83	116	D12	144	PD2	I/O	FT		TIM3_ETR/UART5_RX/ SDIO_CMD / DCMI_D11/ EVENTOUT

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
-	-	84	117
-	A4	85	118
-	C6	86	119
-	-	-	120
-	-	-	121
-	B5	87	122
-	A5	88	123
-	-	-	124
-	-	-	125
-	-	-	126
-	-	-	127
-	-	-	128
-	-	-	129

			Pin number
LQFP64	WLCSP90	LQFP100	LQFP144
-	E8	-	130
-	F7	-	131
-	-	-	132
55	B6	89	133
56	A6	90	134
57	D7	91	135
58	C7	92	136
59	B7	93	137
60	A7	94	138
61	D8	95	139
62	C8	96	140

Table 7. STM32F40x pin and ball definitions (continued)

• 1. Function availability depends on the chosen device.
• 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
  • The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED).
• 1. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com.
• 1. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
• 1. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low).

Table 8. FSMC pin definition

			FSMC
Pins(1)	CF	NOR/PSRAM/ SRAM	NOR/PSRAM Mux
PE2		A23	A23
PE3		A19	A19

Table 8. FSMC pin definition (continued)

			FSMC
Pins(1)	CF	NOR/PSRAM/ SRAM	NOR/PSRAM Mux
PE4		A20	A20
PE5		A21	A21
PE6		A22	A22
PF0	A0	A0
PF1	A1	A1
PF2	A2	A2
PF3	A3	A3
PF4	A4	A4
PF5	A5	A5
PF6	NIORD
PF7	NREG
PF8	NIOWR
PF9	CD
PF10	INTR
PF12	A6	A6
PF13	A7	A7
PF14	A8	A8
PF15	A9	A9
PG0	A10	A10
PG1		A11
PE7	D4	D4	DA4
PE8	D5	D5	DA5
PE9	D6	D6	DA6
PE10	D7	D7	DA7
PE11	D8	D8	DA8
PE12	D9	D9	DA9
PE13	D10	D10	DA10
PE14	D11	D11	DA11
PE15	D12	D12	DA12
PD8	D13	D13	DA13
PD9	D14	D14	DA14
PD10	D15	D15	DA15
PD11		A16	A16

Table 8. FSMC pin definition (continued)

			FSMC
Pins(1)	CF	NOR/PSRAM/ SRAM	NOR/PSRAM Mux
PD12		A17	A17
PD13		A18	A18
PD14	D0	D0	DA0
PD15	D1	D1	DA1
PG2		A12
PG3		A13
PG4		A14
PG5		A15
PG6
PG7
PD0	D2	D2	DA2
PD1	D3	D3	DA3
PD3		CLK	CLK
PD4	NOE	NOE	NOE
PD5	NWE	NWE	NWE
PD6	NWAIT	NWAIT	NWAIT
PD7		NE1	NE1
PG9		NE2	NE2
PG10	NCE4_1	NE3	NE3
PG11	NCE4_2
PG12		NE4	NE4
PG13		A24	A24
PG14		A25	A25
PB7		NADV	NADV
PE0		NBL0	NBL0
PE1		NBL1	NBL1

^2. Ports F and G are not available in devices delivered in 100-pin packages.

								Table 9. A	ternate function m	apping
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8
F	ort	sys	TIM1/2	TIM3/4/5	TIM8/9/10/1 1	I2C1/2/3	SPI1/SPI2/ I2S2/I2S2ext	SPI3/I2Sext/ I2S3	USART1/2/3/ I2S3ext	UART4/5/ USART6
	PA0		TIM2_CH1_E TR	TIM 5_CH1	TIM8_ETR				USART2_CTS	UART4_TX
	PA1		TIM2_CH2	TIM5_CH2					USART2_RTS	UART4_RX
	PA2		TIM2_CH3	TIM5_CH3	TIM9_CH1				USART2_TX
	PA3		TIM2_CH4	TIM5_CH4	TIM9_CH2				USART2_RX
	PA4						SPI1_NSS	SPI3_NSS I2S3_WS	USART2_CK
	PA5		TIM2_CH1_E TR		TIM8_CH1N		SPI1_SCK
	PA6		TIM1_BKIN	TIM3_CH1	TIM8_BKIN		SPI1_MISO
Port A	PA7		TIM1_CH1N	TIM3_CH2	TIM8_CH1N		SPI1_MOSI
	PA8	MCO1	TIM1_CH1			I2C3_SCL			USART1_CK
	PA9		TIM1_CH2			I2C3_SMB A			USART1_TX
	PA10		TIM1_CH3						USART1_RX
	PA11		TIM1_CH4						USART1_CTS
	PA12 PA13 PA14	JTMS- SWDIO JTCK- SWCLK	TIM1_ETR						USART1_RTS
	PA15	JTDI	TIM 2_CH1 TIM 2_ETR				SPI1_NSS	SPI3_NSS/ I2S3_WS

M

								Table 9. Alternat	te function mappin	g (continued)
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8
P	ort	sys	TIM1/2	TIM3/4/5	TIM8/9/10/1 1	I2C1/2/3	SPI1/SPI2/ I2S2/I2S2ext	SPI3/I2Sext/ I2S3	USART1/2/3/ I2S3ext	UART4/5/ USART6
	PB0		TIM1_CH2N	TIM3_CH3	TIM8_CH2N
	PB1 PB2		TIM1_CH3N	TIM3_CH4	TIM8_CH3N
	PB3	JTDO/ TRACES WO	TIM2_CH2				SPI1_SCK	SPI3_SCK I2S3_CK
	PB4	NJTRST		TIM3_CH1			SPI1_MISO	SPI3_MISO	I2S3ext_SD
	PB5			TIM3_CH2		I2C1_SMB A	SPI1_MOSI	SPI3_MOSI I2S3_SD
	PB6			TIM4_CH1		I2C1_SCL			USART1_TX
	PB7			TIM4_CH2		I2C1_SDA			USART1_RX
Port B	PB8			TIM4_CH3	TIM10_CH1	I2C1_SCL
	PB9			TIM4_CH4	TIM11_CH1	I2C1_SDA	SPI2_NSS I2S2_WS
	PB10		TIM2_CH3			I2C2_SCL	SPI2_SCK I2S2_CK		USART3_TX
	PB11		TIM2_CH4			I2C2_SDA			USART3_RX
	PB12		TIM1_BKIN			I2C2_SMB A	SPI2_NSS I2S2_WS		USART3_CK
	PB13		TIM1_CH1N				SPI2_SCK I2S2_CK		USART3_CTS
	PB14		TIM1_CH2N		TIM8_CH2N		SPI2_MISO	I2S2ext_SD	USART3_RTS
	PB15	RTC_ REFIN	TIM1_CH3N		TIM8_CH3N		SPI2_MOSI I2S2_SD

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
	SYS	TIM1/2	TIM3/4/5	TIM8/9/10/11	I2C1/2/3	SPI1/SPI2/I2S2/I2S2ext	SPI3/I2Sext/I2S3	USART1/2/3/I2S3ext	UART4/
	SYS	TIM1/2	TIM3/4/5	TIM8/9/10/11	I2C1/2/3	SPI1/SPI2/I2S2/I2S2ext	SPI3/I2Sext/I2S3	USART1/2/3/I2S3ext	UART4/5/USART6	CAN1/CAN2/TIM12/13/14	OTG_FS/OTG_HS	ETH	FSMC/SDIO/OTG_FS	DCMI		EVENTOUT
PB0		TIM1_CH2N	TIM3_CH3	TIM8_CH2N							OTG_HS_ULPI_D1	ETH_MII_RXD2				EVENTOUT
PB1		TIM1_CH3N	TIM3_CH4	TIM8_CH3N							OTG_HS_ULPI_D2	ETH_MII_RXD3				EVENTOUT
PB2	JTDO/TRACESWO	TIM2_CH2				SPI1_SCK	SPI3_SCK									EVENTOUT
PB3	NJTRST	TIM2_CH1				SPI1_MOSI	SPI3_MOSI	I2S3ext_SD								EVENTOUT
PB4	NJTRST		TIM3_CH1			SPI1_MISO	SPI3_MISO	I2S3ext_SD								EVENTOUT
PB5			TIM3_CH2		I2C1_SMB_A	SPI1_MOSI	SPI3_MOSI									EVENTOUT
PB6		TIM4_CH1			I2C1_SCL			USART1_TX		CAN2_RX	OTG_HS_ULPI_D7	ETH_PPS_OUT		DCMI_D10		EVENTOUT
PB7		TIM4_CH2			I2C1_SDA			USART1_RX		CAN2_TX			FSMC_NL	DCMI_VSYNC		EVENTOUT
PB8		TIM4_CH3		TIM10_CH1	I2C1_SCL					CAN1_RX		ETH_MII_TXD3	SDIO_D4	DCMI_D8		EVENTOUT
PB9		TIM4_CH4		TIM11_CH1	I2C1_SDA	SPI2_NSS				CAN1_TX			SDIO_D5	DCMI_D7		EVENTOUT
PB10		TIM2_CH3			I2C2_SCL	SPI2_SCK		USART3_TX			OTG_HS_ULPI_D3	ETH_MII_RX_ER				EVENTOUT
PB11		TIM2_CH4			I2C2_SDA			USART3_RX			OTG_HS_ULPI_D4	ETH_MII_TX_EN				EVENTOUT
PB0		TIM1_CH2N	TIM3_CH3	TIM8_CH2N							OTG_HS_ULPI_D1	ETH_MII_RXD2				EVENTOUT
PB1		TIM1_CH3N	TIM3_CH4	TIM8_CH
PB12		TIM1_BKIN			I2C2_SMB_A	SPI2_NSS		USART3_CK		CAN2_RX	OTG_HS_ULPI_D5	ETH_MII_TXD0	OTG_HS_ID			EVENTOUT
PB13		TIM1_CH1N				SPI2_SCK		USART3_CTS		CAN2_TX	OTG_HS_ULPI_D6	ETH_MII_TXD1	OTG_HS_DM			EVENTOUT
PB14		TIM1_CH2N		TIM8_CH2N		SPI2_MISO	I2S2ext_SD	USART3_RTS	TIM12_CH1				OTG_HS_DP			EVENTOUT
PB15	RTC_REFIN	TIM1_CH3N		TIM8_CH3N		SPI2_MOSI	I2S2_SD		TIM12_CH2							EVENTOUT

Table 9. Alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 Port AF14 AF15 CAN1/ OTG_FS/ OTG_HS TIM8/9/10/1 SPI1/SPI2/ SPI3/I2Sext/ USART1/2/3/ UART4/5/ FSMC/SDIO/ SYS TIM1/2 TIM3/4/5 I2C1/2/3 CAN2/ ETH DCMI 12S2/12S2ext 1253 12S3ext USART6 OTG_FS TIM12/13/14 PD0 CAN1_RX FSMC_D2 EVENTOUT PD1 CAN1_TX FSMC_D3 EVENTOUT PD2 TIM3_ETR UART5_RX SDIO_CMD DCMI_D11 EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT USART2_RTS PD4 FSMC_NOE EVENTOUT PD5 USART2 TX FSMC NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT FSMC_NE1/ FSMC_NCE2 PD7 USART2_CK EVENTOUT Port D USART3 TX FSMC D13 EVENTOUT PD8 USART3_RX FSMC_D14 EVENTOUT PD9 FSMC D15 EVENTOUT PD10 USART3 CK FSMC_A16 USART3_CTS EVENTOUT PD11 PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT PD13 FSMC_A18 EVENTOUT TIM4_CH2 PD14 TIM4_CH3 FSMC_D0 EVENTOUT PD15 TIM4 CH4 FSMC D1 EVENTOUT

DocID022152 Rev 4

Pinouts and pin description

Port	AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
PA0		TIM2_CH1_ETR	TIM5_CH1	TIM8_ETR				USART2_CTS	UART4_TX			ETH_MII_CRS				EVENTOUT
PA1		TIM2_CH2	TIM5_CH2					USART2_RTS	UART

		•						Table 9. Alternat	e function mappin	g (continued)
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8
P	ort PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8	sys	TIM1/2	TIM3/4/5	TIM8/9/10/1 1	I2C1/2/3	SPI1/SPI2/ I2S2/I2S2ext	SPI3/I2Sext/ I2S3	USART1/2/3/ I2S3ext	UART4/5/ USART6 USART6_CK USART6_ RTS
Port G	PG9 PG10 PG11 PG12 PG13 PG14 PG15							Table 9. Alternat	e function mappin	USART6_RX USART6_ RTS UART6_CTS USART6_TX USART6_ CTS g (continued)
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8
P	ort PH0 PH1 PH2 PH3 PH4 PH5 PH6	sys	TIM1/2	TIM3/4/5	TIM8/9/10/1 1	I2C1/2/3 I2C2_SCL I2C2_SDA I2C2_SMB A	SPI1/SPI2/ I2S2/I2S2ext	SPI3/I2Sext/ I2S3	USART1/2/3/ I2S3ext	UART4/5/ USART6
Port H	PH7					I2C3_SCL
roitii	PH8 PH9 PH10 PH11 PH12			TIM5_CH1 TIM5_CH2 TIM5_CH3		I2C3_SDA I2C3_SMB A
	PH13 PH14 PH15				TIM8_CH1N TIM8_CH2N TIM8_CH3N			-

• cID02
• 22152
• 2 Re√
• 4

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						1		Table 9. Alternat	e function mappin	g (continued)
		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8
P	ort PI0 PI1	sys	TIM1/2	TIM3/4/5 TIM5_CH4	TIM8/9/10/1 1	I2C1/2/3	SPI1/SPI2/ I2S2/I2S2ext SPI2_NSS I2S2_WS SPI2_SCK I2S2_CK	SPI3/I2Sext/ I2S3	USART1/2/3/ I2S3ext	UART4/5/ USART6
	PI2 PI3 PI4				TIM8_CH4 TIM8_ETR TIM8_BKIN		SPI2_MISO SPI2_MOSI I2S2_SD	I2S2ext_SD
Port I	PI5 PI6 PI7 PI8 PI9 PI10 PI11				TIM8_CH1 TIM8_CH2 TIM8_CH3

The definition and values of input/output AC characteristics are given in Figure 37 and Table 49, respectively.

^2. The $I_{|O}$ current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of $I_{|O}$ (I/O ports and control pins) must not exceed $I_{VSS}$ .

^3. The $I_{\rm IO}$ current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of $I_{\rm IO}$ (I/O ports and control pins) must not exceed $I_{\rm VDD}$ .

^4. Based on characterization data, not tested in production.

Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the ambient temperature and $V_{DD}$ supply voltage conditions summarized in Table 14.

Table 49. I/O AC characteristics^(1)(2)(3)

OSPEEDRy [1:0] bit value (1)	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
			$C_L = 50 \text{ pF}, V_{DD} > 2.70 \text{ V}	-	-	2
	£ .	Maximum frequency (4)	C L = 50 pF, V DD > 1.8 V	-	-	2	MHz
	f max(IO)out	waximum requericy.	C L = 10 pF, V DD > 2.70 V	-	-	TBD	IVITZ
00			C L = 10 pF, V DD > 1.8 V	-	-	TBD
	t f(IO)out	Output high to low level fall time	C L = 50 pF, V DD = 1.8 V to	-	-	TBD	ns
	t r(IO)out	Output low to high level rise time	3.6 V	-	-	TBD	115
			C L = 50 pF, V DD > 2.70 V	-	-	25
	f	Maximum frequency (4)	C L = 50 pF, V DD > 1.8 V	-	-	12.5 (5)	MHz
01	f max(IO)out	waximum frequency.	C L = 10 pF, V DD > 2.70 V	-	-	50 (5)	1911 12
			C L = 10 pF, V DD > 1.8 V	-	-	TBD
01		Output high to low level fall	C L = 50 pF, V DD < 2.7 V	-	-	TBD
	t f(IO)out	time	C L = 10 pF, V DD > 2.7 V	-	-	TBD	no
		Output low to high level rise	C L = 50 pF, V DD < 2.7 V	-	-	TBD	ns
	t r(IO)out	time	C L = 10 pF, V DD > 2.7 V	-	-	TBD
			C L = 40 pF, V DD > 2.70 V	-	-	50 (5)
	£ .	Maximum frequency (4)	C L = 40 pF, V DD > 1.8 V	-	-	25	MHz
	f max(IO)out	waximum frequency.	C L = 10 pF, V DD > 2.70 V	-	-	100 (5)	IVIITZ
			C L = 10 pF, V DD > 1.8 V	-	-	TBD
10	t f(IO)out	Output high to low level fall time	C L = 50 pF, 2.4 < V DD < 2.7 V	-	-	TBD
	, , , , , , , , , , , , , , , , , , , ,	une	C L = 10 pF, V DD > 2.7 V	-	-	TBD	ns
	t r(IO)out	Output low to high level rise time	C L = 50 pF, 2.4 < V DD < 2.7 V C L = 10 pF, V DD > 2.7 V	-	- -	TBD TBD
OSPEEDRy [1:0] bit value(1)	Symbol	Parameter	Conditions	Min	Typ	Max	Unit
-----------------------------------	------------	-----------------------------------------------------------------------	----------------------------------	-----	-----	--------	------
		Maximum frequency(4)	CL = 30 pF, VDD > 2.70 V	-	-	100(5)
11	Fmax(IO)ou		CL = 30 pF, VDD > 1.8 V	-	-	50(5)
	t		CL = 10 pF, VDD > 2.70 V	-	-	200(5)	MHz
			CL = 10 pF, VDD > 1.8 V	-	-	TBD
	tf(IO)out	Output high to low level fall time	CL = 20 pF, 2.4 < VDD < 2.7 V	-	-	TBD
			CL = 10 pF, VDD > 2.7 V	-	-	TBD
	tr(IO)out	Output low to high level rise time	CL = 20 pF, 2.4 < VDD < 2.7 V	-	-	TBD	ns
			CL = 10 pF, VDD > 2.7 V	-	-	TBD
-	tEXTIpw	Pulse width of external signals detected by the EXTI controller		10	-	-	ns

Table 49. I/O AC characteristics(1)(2)(3) (continued)

• 1. TBD stands for "to be defined".
• 1. The maximum frequency is defined in Figure 37.
• 1. For maximum frequencies above 50 MHz, the compensation cell should be used.

ai14131 10% 90% 50% t r(IO)out OUTPUT EXTERNAL ON 50pF Maximum frequency is achieved if (tr + tf ) ≤ 2/3)T and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pF T t r(IO)out

Figure 37. I/O AC characteristics definition

Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol	Ratings	Min	Max	Unit
VDD–VSS	(1) External main supply voltage (including VDDA, VDD)	–0.3	4.0
	Input voltage on five-volt tolerant pin(2)	VSS–0.3	VDD+4	V
VIN	Input voltage on any other pin	VSS–0.3	4.0
ΔVDDx	Variations between different VDD power pins	-	50
VSSX - VSS	Variations between all the different ground pins	- 50		mV
VESD(HBM)	Electrostatic discharge voltage (human body model)	see Section 5.3.14: Absolute maximum ratings (electrical sensitivity)

^1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range.

^2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current.

Symbol Ratings Max. Unit Total current into V_DD power lines (source)⁽¹⁾ 150 I_VDD Total current out of V_SS ground lines (sink)⁽¹⁾ 150 I_VSS Output current sunk by any I/O and control pin I₁₀ Output current source by any I/Os and control pin 25 mΑ Injected current on five-volt tolerant I/O(3) -5/+0 I_INJ(PIN)⁽²⁾ Injected current on any other pin⁽⁴⁾ ±5 Sigma I_INJ(PIN)⁽⁴⁾ Total injected current (sum of all I/O and control pins)(5) ±25

Table 12. Current characteristics

• 1. All main power ( V_DD , V_DDA ) and ground ( V_SS , V_SSA ) pins must always be connected to the external power supply, in the permitted range.
• Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC characteristics.
• 1. Positive injection is not possible on these I/Os. A negative injection is induced by V_IN < V_SS . I_INJ(PIN) must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
• A positive injection is induced by V_IN>V_DD while a negative injection is induced by V_IN<V_SS. I_INJ(PIN) must never be exceeded. Refer to Table 11 for the values of the maximum allowed input voltage.
• When several inputs are submitted to a current injection, the maximum ΣI_INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values).

Table 13. Thermal characteristics

| Symbol | Ratings | Value | Unit | | V12 | Regulator ON :
1.2 V internal voltage on
VCAP_1/VCAP_2 pins | VOS bit in PWR_CR register = 0⁽¹⁾
Max frequency 144MHz | 1.08 | 1.14 | 1.20 | V | | | | VOS bit in PWR_CR register=1
Max frequency 168MHz | 1.20 | 1.26 | 1.32 | | | | Regulator OFF:
1.2 V external voltage must be
supplied from external regulator
on VCAP_1/VCAP_2 pins | Max frequency 144MHz | 1.10 | 1.14 | 1.20 | | | | | Max frequency 168MHz | 1.20 | 1.26 | 1.30 | | | VIN | Input voltage on RST and FT pins⁽⁶⁾ | 2 V ≤ VDD ≤ 3.6 V | -0.3 | - | 5.5 | V | | | | VDD ≤ 2 V | -0.3 | - | 5.2 | | | | Input voltage on TTa pins | | -0.3 | - | VDDA+
0.3 | | | | Input voltage on B pin | | - | - | 5.5 | | | PD | Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7⁽⁷⁾ | LQFP64 | - | - | 435 | mW | | | | LQFP100 | - | - | 465 | | | | | LQFP144 | - | - | 500 | | | | | LQFP176 | - | - | 526 | | | | | UFBGA176 | - | - | 513 | | | | | WLCSP90 | - | - | 543 | | | TA | Ambient temperature for 6 suffix
version | Maximum power dissipation | -40 | - | 85 | °C | | | | Low power dissipation⁽⁸⁾ | -40 | - | 105 | | | | Ambient temperature for 7 suffix
version | Maximum power dissipation | -40 | - | 105 | | | | | Low power dissipation⁽⁸⁾ | -40 | - | 125 | | | TJ | Junction temperature range | 6 suffix version | -40 | - | 105 | °C | | | | 7 suffix version | -40 | - | 125 | | |---|---|---|---| | T_STG | Storage temperature range | -65 to +150 | °C | | T_J | Maximum junction temperature | 125 | °C |

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation:

TJ max = TA max + (PD max x ΘJA)

Where:

• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.

PI/O max represents the maximum power dissipation on output pins where:P_I/O$ max = $\Sigma (V_{OL} \times I_{OL}) + \Sigma ((V_{DD} - V_{OH}) \times I_{OH}),

taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application.

• Symbol Parameter Value Unit
• Thermal resistance junction-ambient
  LQFP64 - 10 × 10 mm / 0.5 mm pitch 46
• Thermal resistance junction-ambient
  LQFP100 - 14 × 14 mm / 0.5 mm pitch 43
• Thermal resistance junction-ambient
  LQFP144 - 20 × 20 mm / 0.5 mm pitch 40
• ΘJA Thermal resistance junction-ambient
  LQFP176 - 24 × 24 mm / 0.5 mm pitch 38 °C/W
• Thermal resistance junction-ambient
  UFBGA176 - 10× 10 mm / 0.65 mm pitch 39
• Thermal resistance junction-ambient
  WLCSP90 - 0.400 mm pitch 38.1

Table 96. Package thermal characteristics

Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org.

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline

Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data

		millimeters			inches(1)
Symbol	Min	Typ	Max	Min	Typ
A	0.520	0.570	0.620	0.0205	0.0224
A1	0.165	0.190	0.215	0.0065	0.0075
A2	0.350	0.380	0.410	0.0138	0.015
b	0.240	0.270	0.300	0.0094	0.0106
D	4.178	4.218	4.258	0.1645	0.1661
E	3.964	3.969	4.004	0.1561	0.1563
e		0.400			0.0157
e1		3.600			0.1417
e2		3.200			0.126
F		0.312			0.0123
G		0.385			0.0152
eee			0.050

^1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline

Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data

		millimeters			inches(1)
Symbol	Min	Typ	Max	Min	Typ
A			1.600
A1	0.050		0.150	0.0020
A2	1.350	1.400	1.450	0.0531	0.0551
b	0.170	0.220	0.270	0.0067	0.0087
c	0.090		0.200	0.0035
D		12.000			0.4724
D1		10.000			0.3937
E		12.000			0.4724
E1		10.000			0.3937
e		0.500			0.0197
θ	0°	3.5°	7°	0°	3.5°
L	0.450	0.600	0.750	0.0177	0.0236
L1		1.000			0.0394
N	Number of pins			64

Figure 78. LQFP64 recommended footprint

• 1. Drawing is not to scale.
• 1. Dimensions are in millimeters.

Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline

Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data(1)

		millimeters			inches
Symbol	Min	Typ	Max	Min	Typ
A			1.600
A1	0.050		0.150	0.0020
A2	1.350	1.400	1.450	0.0531	0.0551
b	0.170	0.220	0.270	0.0067	0.0087
c	0.090		0.200	0.0035
D	15.800	16.000	16.200	0.6220	0.6299
D1	13.800	14.000	14.200	0.5433	0.5512
D3		12.000			0.4724
E	15.80v	16.000	16.200	0.6220	0.6299
E1	13.800	14.000	14.200	0.5433	0.5512
E3		12.000			0.4724
e		0.500			0.0197
L	0.450	0.600	0.750	0.0177	0.0236
L1		1.000			0.0394
k	0°	3.5°	7°	0°	3.5°
ccc			0.080

^1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 80. LQFP100 recommended footprint

• 1. Drawing is not to scale.
• 1. Dimensions are in millimeters.

Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline

Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data

		millimeters			inches(1)
Symbol	Min	Typ	Max	Min	Typ
A			1.600
A1	0.050		0.150	0.0020
A2	1.350	1.400	1.450	0.0531	0.0551
b	0.170	0.220	0.270	0.0067	0.0087
c	0.090		0.200	0.0035
D	21.800	22.000	22.200	0.8583	0.8661
D1	19.800	20.000	20.200	0.7795	0.7874
D3		17.500			0.689
E	21.800	22.000	22.200	0.8583	0.8661
E1	19.800	20.000	20.200	0.7795	0.7874
E3		17.500			0.6890
e		0.500			0.0197
L	0.450	0.600	0.750	0.0177	0.0236
L1		1.000			0.0394

		millimeters			inches(1)
Symbol	Min	Typ	Max	Min	Typ
k	0°	3.5°	7°	0°	3.5°
ccc			0.080

^1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 82. LQFP144 recommended footprint 0.5 0.35 19.9 17.85 22.6 1.35 19.9 1 36 37 72 108 73 109 144

22.6

• 1. Drawing is not to scale.
• 1. Dimensions are in millimeters.

ai14905c

C Seating plane

A2

A1 ball A1 ball identifier index area

A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array10 \times 10 \times 0.6$ mm, package outline

Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array $10 \times 10 \times 0.6mm mechanical data

Oranah ad		millimeters		inches (1)
Symbol	Min	Typ	Max	Min
Α	0.460	0.530	0.600	0.0181
A1	0.050	0.080	0.110	0.002
A2	0.400	0.450	0.500	0.0157
b	0.230	0.280	0.330	0.0091
D	9.900	10.000	10.100	0.3898
E	9.900	10.000	10.100	0.3898
e		0.650
F	0.425	0.450	0.475	0.0167
ddd			0.080
eee			0.150
fff			0.080

^1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline

Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data

Symbol		millimeters			inches(1)
	Min	Typ	Max	Min	Typ
A			1.600
A1	0.050		0.150	0.0020
A2	1.350		1.450	0.0531
b	0.170		0.270	0.0067
C	0.090		0.200	0.0035
D	23.900		24.100	0.9409
E	23.900		24.100	0.9409
e		0.500			0.0197
HD	25.900		26.100	1.0200
HE	25.900		26.100	1.0200
L	0.450		0.750	0.0177
L1		1.000			0.0394
ZD		1.250			0.0492
ZE		1.250			0.0492

		millimeters		inches(1)
	Symbol Min		Max	Min
ccc			0.080
k	0 °		7 °	0 °

^1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 85. LQFP176 recommended footprint

1. Dimensions are expressed in millimeters.