ST25DV64KC
Dynamic NFC/RFID tag IC with 4-Kbit, 16-Kbit or 64-Kbit EEPROM, fast transfer mode capability and optimized I2C
Dynamic NFC/RFID Tag ICThe ST25DV64KC is a dynamic nfc/rfid tag ic from STMicroelectronics. Dynamic NFC/RFID tag IC with 4-Kbit, 16-Kbit or 64-Kbit EEPROM, fast transfer mode capability and optimized I2C. View the full ST25DV64KC datasheet below including key specifications, electrical characteristics.
Manufacturer
STMicroelectronics
Category
RF / WirelessKey Specifications
| Parameter | Value |
|---|---|
| Frequency | 13.56MHz |
| Interface | I2C |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 85°C |
| Package / Case | 8-SOIC (0.154\", 3.90mm Width) |
| Standards | ISO 15693, NFC |
| Supplier Device Package | 8-SO |
| Type | RFID Transponder |
| Supply Voltage | 1.8V ~ 5.5V |
Overview
Part: ST25DV04KC, ST25DV16KC, ST25DV64KC from STMicroelectronics
Type: Dynamic NFC/RFID Tag IC
Description: Dynamic NFC/RFID tag ICs with 4-Kbit, 16-Kbit, or 64-Kbit EEPROM, supporting I2C and ISO/IEC 15693 contactless interfaces, featuring fast transfer mode and energy harvesting.
Operating Conditions:
- Supply voltage: 1.8 V to 5.5 V
- Operating temperature: -40 to +125 °C (max 105 °C on RF interface for SO8N and TSSOP8)
- I2C clock frequency: 1 MHz
- RF fast read access: up to 53 kbit/s
Absolute Maximum Ratings:
- Max supply voltage: null
- Max continuous current: null
- Max junction/storage temperature: 125 °C
Key Specs:
- EEPROM memory size: 4-Kbit, 16-Kbit, or 64-Kbit (depending on version)
- I2C interface speed: 1 MHz protocol
- RF interface standard: ISO/IEC 15693, NFC Forum Type 5 tag certified
- RF fast read access speed: up to 53 kbit/s
- Internal tuning capacitance: 28.5 pF
- I2C write time: typical 5 ms (for 1 to 16 bytes)
- Data retention: 40 years
- Write cycles endurance: 1 million at 25 °C, 400k at 125 °C
- Fast transfer buffer size: 256 bytes
Features:
- Two-wire I2C serial interface supports 1MHz protocol
- ISO/IEC 15693 and NFC Forum Type 5 tag certified contactless interface
- Fast data transfer mode with 256 bytes dedicated buffer
- Energy harvesting analog output pin
- Configurable GPO interruption pin
- User memory and system configuration protection with passwords
Applications:
- null
Package:
- SO8N (8-pin)
- TSSOP8 (8-pin)
- UDFPN8 (8-pin)
- UFDFPN12 (12-pin)
Features
I 2C interface
- Two-wire I2C serial interface supports 1MHz protocol
- Single supply voltage: 1.8 V to 5.5 V
- Multiple byte write programming (up to 256 bytes)
- Configurable I2C slave address
Contactless interface
- Based on ISO/IEC 15693
- NFC Forum Type 5 tag certified by the NFC Forum
- Supports all ISO/IEC 15693 modulations, coding, sub-carrier modes and data rates
- Custom fast read access up to 53 kbit/s
- Single and multiple blocks read (same for Extended commands)
- Single and multiple blocks write (up to four) (same for Extended commands)
- Internal tuning capacitance: 28.5 pF
Electrical Characteristics
| Test conditions specified in Table 245. I2C operating conditions | ||
|---|---|---|
| Symbol | Alt. | Parameter |
| fC | fSCL | Clock frequency |
| tCHCL | tHIGH | Clock pulse width high(1) |
| tCLCH | tLOW | Clock pulse width low(1) |
| tSTARTOUT | - | I²C timeout on Start condition(1) |
| tXH1XH2 | tR | Input signal rise time(1) |
| tXL1XL2 | tF | Input signal fall time(1) |
| tDL1DL2 | tF | SDA (out) fall time(1) |
| tDXCX | tSU:DAT | Data in set up time(1) |
| tCLDX | tHD:DAT | Data in hold time |
| tCLQX | tDH | Data out hold time(5) |
| tCLQV | tAA | Clock low to next data valid (access time)(6) |
| tCHDX | tSU:STA | Start condition set up time(7) |
| tDLCL | tHD:STA | Start condition hold time |
| tCHDH | tSU:STO | Stop condition set up time |
| tDHDL | tBUF | Time between Stop condition and next Start condition |
| tW | - | I²C write time (9) |
| tbootDC | - | RF OFF and LPD = 0(1) |
| tbootLPD | - | RF OFF(1) |
- 1. Evaluated by Characterization Not tested in production.
- 2. tCHCL timeout.
- 3. tCLCH timeout.
- 4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I 2C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.
- 5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
- 6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus × Cbus time constant is less than 150 ns (as specified in the Figure 81. I2C Fast mode (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus).
- 7. For a reStart condition, or following a write cycle.
- 8. tDLCL timeout
- 9. I 2C write time for 1 Byte, up to 16 Bytes in EEPROM (user memory) provided they are all located in the same memory row, that is the most significant memory address bits (b16-b4) are the same.
DS13519 - Rev 2 page 145/200
Table 251. I 2C AC characteristics up to 125 °C
| Test conditions specified in Table 245. I2C operating conditions | ||
|---|---|---|
| Symbol | Alt. | Parameter |
| fC | fSCL | Clock frequency |
| tCHCL | tHIGH | Clock pulse width high |
| tCLCH | tLOW | Clock pulse width low |
| tSTARTOUT | - | I²C timeout on Start condition(3) |
| tXH1XH2 | tR | Input signal rise time(3) |
| tXL1XL2 | tF | Input signal fall time(3) |
| tDL1DL2 | tF | SDA (out) fall time(3) |
| tDXCX | tSU:DAT | Data in set up time(3) |
| tCLDX | tHD:DAT | Data in hold time |
| tCLQX | tDH | Data out hold time(5) |
| tCLQV | tAA | Clock low to next data valid (access time)(6) |
| tCHDX | tSU:STA | Start condition set up time(7) |
| tDLCL | tHD:STA | Start condition hold time |
| tCHDH | tSU:STO | Stop condition set up time |
| tDHDL | Time between Stop condition and next Start tBUF 1400 condition | |
| tW | - | I²C write time (9) |
| tbootDC | - | RF OFF and LPD = 0(3) |
| tbootLPD | - | RF OFF(3) |
DS13519 - Rev 2 page 146/200
SDA Out
Figure 80. I 2C AC waveforms
Figure 81 indicates how the value of the pull-up resistor can be calculated. In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.
Data valid
Figure 81. I 2C Fast mode (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus)
Data valid
DS13519 - Rev 2 page 147/200
Thermal Information
Table 257. Thermal characteristics
| Symbol | Parameter | Value | Unit |
|---|---|---|---|
| Thermal resistance junction-ambient | |||
| SO8N 4.9 x 6 mm, 1.27 mm pitch package(1) Thermal resistance junction-ambient | 219 | ||
| ƟJA | TSSOP8 3 x 6.4 mm, 0.65 mm pitch package(1) | 255 | °C/W |
| Thermal resistance junction-ambient UFDFN8 2 × 3 mm, 0.5 mm pitch package(1)(2) | 67 |
DS13519 - Rev 2 page 150/200
Package Information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| ST25DV04KC | STMicroelectronics | — |
| ST25DV04KC-IE | STMicroelectronics | — |
| ST25DV04KC-IE6S3 | STMicroelectronics | 8-SOIC (0.154", 3.90mm Width) |
| ST25DV04KC-JF | STMicroelectronics | — |
| ST25DV16KC | STMicroelectronics | — |
| ST25DVXXKC | STMicroelectronics | — |
Get structured datasheet data via API
Get started free