SE050C2HQ1/Z01SD

Part: SE050 — NXP Semiconductors

Type: IoT Secure Element

Description: Ready-to-use IoT secure element solution operating from 1.62 V to 3.6 V with Common Criteria EAL 6+ certification, integrated Java Card OS, and 50 kB secured user flash memory.

Operating Conditions:

• Supply voltage: 1.62–3.6 V
• Operating temperature: -40 to 105 °C
• DC input voltage on digital inputs and digital I/O pads: -0.3 V to VCC/Vin + 0.3 V
• Contactless interface field strength: 1.5 to 7.5 A/m

Absolute Maximum Ratings:

• Max supply voltage: 6 V
• Max junction/storage temperature: 125 °C (storage)

Key Specs:

• Supply voltage (nominal): 1.8 V (operating range 1.62 V to 3.6 V)
• Total power dissipation: 600 mW max
• Power-Down mode current (with state retention): < 500 μA
• Deep Power-Down mode current (no state retention): < 5 μA
• Input/output current (pads I2C_SDA, I2C_SCL): 10 mA max
• Latch-up current: 100 mA max (VI < 0 V or VI > Vin, VCC)
• ESD rating (HBM): ±2 kV
• ESD rating (CDM): ±500 V
• I2C Target interface speed: up to 3.4 Mbit/s (High-speed mode)
• I2C Controller interface speed: up to 400 kbit/s (Fast mode)
• Flash endurance / data retention: up to 100 million write cycles / 25 years

Features:

• Built on NXP Integral Security Architecture 3.0 with CC EAL 6+ certified HW and OS
• Hardware support for RSA (up to 4096-bit) and ECC (NIST, Brainpool, Edwards, Montgomery, Koblitz)
• Symmetric crypto support for AES (128, 192, 256) and 3DES (2K, 3K)
• Hash support for SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, HMAC, and CMAC
• TRNG (NIST SP800-90B, AIS31) and DRBG (NIST SP800-90A, AIS20)
• 50 kB secured flash memory for key and data storage
• Simultaneous I2C target and I2C controller interfaces
• Contactless ISO14443-A PICC interface support
• SCP03 protocol support for host-to-SE encrypted communication
• Matter Ready cryptographic functions support

Applications:

• Smart Industry
• Smart Home
• Smart Cities
• Smart Supply Chains
• Device-to-device authentication and cloud onboarding
• Qi 1.3 wireless charging authentication

Package:

• HX2QFN20 (3 x 3 mm)

The SE050 is based on NXP's Integral Security Architecture 3.0 ™ providing a secure and efficient protection against various security threats. The efficiency of the security measures is proven by a Common Criteria EAL6+ certification.

The SE050 operates fully autonomously based on an integrated Javacard operating system and applet. Direct memory access is possible by the fixed functionalities of the applet only. With that, the content from the memory is fully isolated from the host system.

• Built on NXP Integral Security Architecture 3.0 ™
• CC EAL 6+ certified HW and OS as environment to run NXP IoT applications, supporting fully encrypted communications and secured lifecycle management
• FIPS 140-2 certified platform with Security Level 3 for OS and Applet, and Security Level 4 related to Physical Security of the HW
• -Disclaimer: FIPS certification require a specific product type. For more information, refer to [4].
• Effective protection against advanced attacks, including Power Analysis and Fault Attacks of various kinds
• Multiple logical and physical protection layers, including metal shielding, end-to-end encryption, memory encryption, tamper detection
• Support for RSA and ECC asymmetric cryptography algorithms, future proof curves and high key length, e.g. Brainpool, Edwards and Montgomery curves
• Support for AES and DES symmetric cryptographic algorithms for encryption and decryption
• Support for AES Modes: CBC, EBC, CTR
• HMAC, CMAC, SHA-1, SHA-224/256/384/512 operations
• Various options for key derivation functions, including HKDF, MIFARE KDF, PRF (TLS-PSK)
• Extended temperature range for industrial applications (-40 °C to 105 °C)
• Small footprint HX2QFN20 package (3x3 mm)

SE050

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• Standard physical interface I 2 C target (High-speed mode, 3.4 Mbit/s), I 2 C controller (Fast mode, 400 kbit/s). Both can be active at the same time
• Dedicated CL wireless interface for IoT use cases simplifying configuration set-up, maintenance in the field and late stage configuration
• Secured user flash memory up to 50 kB for secure data or key storage
• Support for SCP03 protocol (bus encryption and encrypted credential injection) to securely bind the host with the secure element
• TRNG compliant to NIST SP800-90B
• DRBG compliant to NIST SP800-90A
• Support for applet level secure messaging channels to allow end-to-end encrypted communication in multitenant ecosystems
• In 2022 NXP launched a new generation of product variants, the SE050E platform. The SE050E platform supports the following new features.
• -AES Modes: CCM and GCM
• -GMAC
• -EC Curves for ECDH: Curve448
• Matter Ready: SE050 provides the necessary cryptographic functions to support the upcoming Matter standard for connecting smart home devices.

Note: The available features in each product vary according to the chosen variant. More details are available on [4].

• Smart Industry
• Smart Home
• Smart Cities
• Smart Supply Chains

Figure 1. SE050 solution block diagram

Note: SE050 is designed to be used as a part of an IoT system. It works as an auxiliary security device attached to a host controller. The host controller communicates with SE050 through an I²C interface (with the host controller being the I²C controller and the SE050 being the I²C target). Besides the mandatory connection to the host controller, the SE050 device can optionally be connected to a sensor node or similar element through a separate I²C interface. In this case, the SE050 device is the I²C controller and the sensor node the I²C target. Lastly, SE050 has a connection for a native contactless antenna, providing a wireless interface to an external device like a smartphone.

Table 13. Non-volatile memory timing characteristics

Conditions: VCC = 1.62 V to 3.6 V; VSS = 0 V; Tamb = -40 °C to 105 °C, unless otherwise specified.

Symbol	Parameter	Conditions	Min	Typ [1]	Max	Unit
t EEP	FLASH erase + program time		[2] -	2.3	-	ms
t EEE	FLASH erase time		-	1.4	-	ms
t EEW	FLASH program time		-	0.9	-	ms
t EER	FLASH data retention time	T amb = 55 °C	25	-	-	years
N EEC	FLASH endurance (maximum number of programming cycles applied to the whole memory block, performed by NXP static and dynamic wear leveling algorithm)		20 × 10 6	100 × 10 6	-	cycles

Table 14. Electrical AC characteristics of I 2 C_SDA, I 2 C_SCL, and RST_N [1] ; VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to 105 °C

SCL, SDA pads in open-drain mode.

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
Input/Output: I 2 C_SDA, I 2 C_SCL in open-drain mode	Input/Output: I 2 C_SDA, I 2 C_SCL in open-drain mode	Input/Output: I 2 C_SDA, I 2 C_SCL in open-drain mode	Input/Output: I 2 C_SDA, I 2 C_SCL in open-drain mode	Input/Output: I 2 C_SDA, I 2 C_SCL in open-drain mode	Input/Output: I 2 C_SDA, I 2 C_SCL in open-drain mode	Input/Output: I 2 C_SDA, I 2 C_SCL in open-drain mode	Input/Output: I 2 C_SDA, I 2 C_SCL in open-drain mode
t r(i)	input rise time	Input/reception mode	[2]	-	-	1	μs
t f(i)	input fall time	Input/reception mode	[3]	-	-	1	μs
t f(o)	output fall time	Output/transmission mode; C L = 30 pF	[2]	-	-	0.3	μs
f CLK	External clock frequency in I 2 C applications	t CLKW , T amb and V CC in their specified limits	-		-	3.4	MHz
t PD	Power down duration time (I 2 C wake-up)	CPU clock = 48 MHz	[4]	-	67	-	μs
t WKPD	Wake-up from power down duration time (I 2 C wake-up)	CPU clock = 48 MHz	[5]	-	97	-	μs
C PIN	Pin capacitances RST_N, I 2 C_SDA, /I 2 C_SCL	Test frequency = 1 MHz; T amb = 25 °C	-		-	10.5	pF
t ENalt	ENA low time and V out , V CC low time for entering deep power down mode		[6]	-	2	-	μs
R on	Resistance of power switch	T amb = 105 °C, I load = 25 mA, V in = 1.62 V	-		-	1.1	Ω
I out	maximum current driving capability of pin V out	T amb = 105 °C	-		-	25	mA
Inputs: RST_N (active only if ISO7816 UART interface is enabled)	Inputs: RST_N (active only if ISO7816 UART interface is enabled)	Inputs: RST_N (active only if ISO7816 UART interface is enabled)	Inputs: RST_N (active only if ISO7816 UART interface is enabled)	Inputs: RST_N (active only if ISO7816 UART interface is enabled)	Inputs: RST_N (active only if ISO7816 UART interface is enabled)	Inputs: RST_N (active only if ISO7816 UART interface is enabled)	Inputs: RST_N (active only if ISO7816 UART interface is enabled)
t RW	Reset pulse width (RST_N low) without entering Power-down mode		40		-	400	μs
t RDSLP	Reset pulse width (RST_N low) to enter Power-down mode		500		-	-	μs

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Table 14. Electrical AC characteristics of I 2 C_SDA, I 2 C_SCL, and RST_N [1] ; VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to 105 °C ...continued

SCL, SDA pads in open-drain mode.

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
t WKP	Wake-up time from Power-down mode	f CLKmin < f CLK < f CLKmax	-	8	10	μs
t WKPIO	Pad LOW time for wake-up from Power-down mode	level triggered ext.int.	-	8	10	μs
t WKPIO	Pad LOW time for wake-up from Power-down mode	edge triggered ext.int.	-	8	10	μs
t WKPRST	RST_N LOW time for wake-up from Power-down mode		40	-	-	μs
C PIN	Pin capacitances RST_N, I 2 C_SDA, /I 2 C_SCL	Test frequency = 1 MHz; T amb = 25 °C	-	-	10.5	pF

• [1] All appropriately marked values are typical values and only referenced for information. They are subject to change without notice.
• [2] tr is defined as rise time between 30 % and 70 % of the signal amplitude.tf is defined as fall time between 70 % and 30 % of the signal amplitude.
• [3] tr is defined as rise time between 30 % and 70 % of the signal amplitude.tf is defined as fall time between 70 % and 30 % of the signal amplitude.
• [5] Wakeup from power down: if clock stretching disabled and I 2 C_SCL=1 MHz; the wakeup time will not be sufficient to receive the first host command; the SE will send an R block to request retransmission from the host
• [4] Wakeup from power down: if clock stretching disabled and I 2 C_SCL=400 kHz; the wakeup time will not be sufficient under the rare condition where host sends the first command during the time where SE is just entering power down; in this case the SE will send an R block to request retransmission from the host
• [6] Low glitches below 0.4 V on pin ENA and Vin, Vout, VCC larger than 30 ns cause Power-On-Reset, respectively entering deep power-down mode.

Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)

Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)

Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to 105 °C, unless otherwise specified. Typical values are only referenced for information. They are subject to change without notice.

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
Input/Output: IO1/IO2	Input/Output: IO1/IO2	Input/Output: IO1/IO2	Input/Output: IO1/IO2	Input/Output: IO1/IO2	Input/Output: IO1/IO2	Input/Output: IO1/IO2	Input/Output: IO1/IO2
t r(i)	input rise time	Input/reception mode	[1] [2]	-	-	1	μs
		Input/reception mode	[3] [2]	-	-	0.25 x t IOWx_min	μs
t f(i)	input fall time	Input/reception mode	[1] [2]	-	-	1	μs
		Input/reception mode	[3] [2]	-	-	0.25 x t IOWx_min	μs
t r(o)	output rise time	Output/transmission mode; CL = 30 pF	[2]	-	-	0.1	μs
t f(o)	output fall time	Output/transmission mode; CL = 30 pF	[2]	-	-	0.1	μs

SE050

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© 2023 NXP B.V. All rights reserved.

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Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface) ...continued

Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to 105 °C, unless otherwise specified. Typical values are only referenced for information. They are subject to change without notice.

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
Inputs: CLK and RST_N	Inputs: CLK and RST_N	Inputs: CLK and RST_N	Inputs: CLK and RST_N	Inputs: CLK and RST_N	Inputs: CLK and RST_N	Inputs: CLK and RST_N	Inputs: CLK and RST_N
f CLK	External clock frequency in ISO/IEC 7816 UART applications	t CLKW , t amb and V CC in their specified limits	[4]	0.85	-	11.5	MHz
t CLKW	Clock pulse width i.r.t. clock period (positive pulse duty cycle of CLK)			40	-	60	%
t r(i)(CLK)	CLK input rise time		[5]	-	-	[6]
t f(i)(CLK)	CLK input fall time		[2] [6]	-	-	[6]
t r(i)(RST_N)	RST_N input rise time		[2]	-	-	400	μs
t f(i)(RST_N)	RST_N input fall time		[2] [7]	-	-	400	μs

• [7] The ETSI TS102 221/GSM 11.1x specifications specify a maximum reset signal (RST_N) rise time and fall time of 400,000 μs, respectively.

Note: tf is defined as fall time between 90 % and 10 % of the signal amplitude.

Table 16. Electrical AC characteristics of LA, LB; Conditions: Tamb = -40 °C to 105 °C, unless otherwise specified

Symbol	Parameter	Conditions		Typ [1]	Max	Unit
Input/Output: LA, LB	Input/Output: LA, LB	Input/Output: LA, LB	Input/Output: LA, LB	Input/Output: LA, LB	Input/Output: LA, LB	Input/Output: LA, LB
C LALB [2]	Pin capacitance LA, LB, bare die (SO28 empty package ground-off)	Pin capacitance LA, LB, bare die (SO28 empty package ground-off)	Pin capacitance LA, LB, bare die (SO28 empty package ground-off)	Pin capacitance LA, LB, bare die (SO28 empty package ground-off)	Pin capacitance LA, LB, bare die (SO28 empty package ground-off)	Pin capacitance LA, LB, bare die (SO28 empty package ground-off)
	Configured for antenna input with 56 pF capacitance,	V LA,LB = 2.1 V rms	[3] [4]	54.3	-	pF
	Test frequency = 13.56 MHz; T amb = 25 °C	V LA,LB = 0.3 V rms	[4]	50.1	-	pF
R LALB [2]	Configured for antenna input with 56 pF capacitance, test frequency = 13.56 MHz; T amb = 25 °C	V LA,LB = 2.1 V rms	[3] [4] [5]	0.913	-	kΩ
f LALB	Operating frequency LA, LB	level triggered ext.int.		13.56	-	MHz

SE050

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The SE050 is characterized by its specified operating supply voltage range of 1.62 V to 3.6 V.

Table 9. Recommended operating conditions

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
V in , V CC	Supply voltage	Nominal supply voltage	1.62	1.8	3.6 [1]	V
V in	DC input voltage on digital inputs and digital I/O pads	-	-0.3	-	V CC /V in [2] + 0.3	V
H	Field strength	Contactless interface operation	1.5	-	7.5	A/m
T amb	Operating ambient temperature [3]		-40	-	105	°C

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