LMZ12001

Part: LMZ14201EXT — Texas Instruments

Type: Step-Down DC-DC Power Module (SIMPLE SWITCHER, integrated shielded inductor)

Description: 6–42 V input, 1 A step-down power module with 0.8–6 V adjustable output, constant on-time control, up to 90% efficiency, and a -55 to 125 °C junction temperature range.

Operating Conditions:

• Supply voltage (VIN): 6–42 V
• Operating junction temperature: -55 to 125 °C
• EN pin: 0–6.5 V
• Output voltage range: 0.8–6 V, up to 1 A output current

Absolute Maximum Ratings:

• VIN, RON to GND: -0.3 to 43.5 V
• EN, FB, SS to GND: -0.3 to 7 V
• Junction temperature: 150 °C
• Storage temperature: -65 to 150 °C
• ESD (HBM): ±2 kV
• Peak reflow case temperature (30 s): 245 °C

Key Specs:

• Feedback voltage VFB: 0.798 V typ (0.777–0.818 V over TJ -55 to 125 °C, IO = 1 A)
• EN rising threshold: 1.18 V typ (1.10–1.26 V), 90 mV hysteresis
• Current limit threshold: 1.95 V typ → 1.95 A typ (1.4–3.0 A)
• Soft-start source current: 8 μA typ (4.9–11 μA)
• Non-switching input current (IQ): 1 mA typ (VFB = 0.86 V)
• Shutdown quiescent current: 25 μA typ (VEN = 0 V)
• Efficiency: 92% typ (VIN = 24 V, VO = 3.3 V, IO = 1 A)
• Line regulation: 0.01% typ (VIN = 12–42 V, IO = 1 A); load regulation 1.5 mV/A typ
• Output ripple: 8 mVPP typ
• Thermal shutdown: 165 °C typ, 15 °C hysteresis
• θJA: 19.3 °C/W (4-layer JEDEC), 21.5 °C/W (2-layer); θJC: 1.9 °C/W

Features:

• Integrated shielded inductor
• Requires only three external resistors and four external capacitors
• Flexible startup sequencing with external soft-start and precision enable
• Protection: input UVLO, output overvoltage, short-circuit, current limit, thermal shutdown
• Startup into a pre-biased output
• Switching frequency adjustable up to 1 MHz with a single resistor
• Passes MIL-STD-883 vibration and drop standards
• Low radiated emissions
• Single exposed pad and standard pinout
• Pin-to-pin compatible with LMZ14203EXT/2EXT, LMZ14203/2/1 and LMZ12003/2/1
• Supported by WEBENCH Power Designer

Applications:

• Point-of-load conversion from 12 V and 24 V input rails
• Military and rugged applications
• Space-constrained / high thermal requirement applications
• Negative output voltage applications
• Powering FPGAs and ASICs

Package:

• 7-pin PFM, 10.16 x 13.77 x 4.57 mm (RoHS compliant)

• 2 · -55°C to 125°C Junction Temperature Range
• Integrated Shielded Inductor
• Simple PCB Layout
• Flexible Startup Sequencing Using External Soft-Start and Precision Enable
• Protection Against Inrush Currents and Faults such as Input UVLO and Output Short Circuit
• Single Exposed Pad and Standard Pinout for Easy Mounting and Manufacturing
• Fast Transient Response for Powering FPGAs and ASICs
• Low Output Voltage Ripple
• Pin-to-Pin Compatible Family
• -LMZ14203EXT/2EXT/1EXT (42V Max 3A, 2A, 1A)
• -LMZ14203/2/1 (42V Max 3A, 2A, 1A)
• -LMZ12003/2/1 (20V Max 3A, 2A, 1A)
• Fully Enabled for Webench® Power Designer

• Point of Load Conversions from 12V and 24V Input Rail
• Time Critical Projects
• Space Constrained / High Thermal Requirement Applications
• Negative Output Voltage Applications (See AN2027 SNVA425)

Figure 1. Easy To Use PFM 7 Pin Package 10.16 x 13.77 x 4.57 mm (0.4 x 0.542 x 0.18 in) θ JA = 20°C/W, θ JC = 1.9°C/W RoHS Compliant Peak Reflow CaseTemp = 245°C

Figure 1. Easy To Use PFM 7 Pin Package 10.16 x 13.77 x 4.57 mm (0.4 x 0.542 x 0.18 in) θ JA = 20°C/W, θ JC = 1.9°C/W RoHS Compliant Peak Reflow CaseTemp = 245°C

1

Power Module SMT Guidelines

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 All trademarks are the property of their respective owners.

• 6W Maximum Total Output Power
• Up to 1A Output Current
• Input Voltage Range 6V to 42V
• Output Voltage Range 0.8V to 6V
• Efficiency up to 90%

VIN, RON to GND

-0.3V to 43.5V

EN, FB, SS to GND

-0.3V to 7V

Junction Temperature

150°C

Storage Temperature Range

-65°C to 150°C

ESD Susceptibility (2)

± 2 kV

Peak Reflow Case Temperature (30 sec)

245°C

For soldering specifications, refer to the following document: www.ti.com/lit/snoa549c

• (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

• (2) The human body model is a 100pF capacitor discharged through a 1.5 k Ω resistor into each pin. Test method is per JESD-22-114.

For the design case of VIN = 24V, VO = 3.3V, IO = 1A, TAMB(MAX) = 85°C , and TJUNCTION = 125°C, the device must see a thermal resistance from case to ambient of less than:

$$\theta_{CA} < (T_{J\text{-}MAX} - T_{AMB(MAX)}) / P_{IC\text{-}LOSS} - \theta_{JC}$$

Given the typical thermal resistance from junction to case to be 1.9 °C/W. Use the 85°C power dissipation curves in the Typical Performance Characteristics section to estimate the PIC-LOSS for the application being designed. In this application it is 0.52W.

θ

CA

= (125 - 85) / 0.52W - 1.9 = 75

To reach θ CA = 75, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a good estimate of the required board area covered by 1 oz. copper on both the top and bottom metal layers is:

$$\text{Board Area}{\text{cm}^2} = 500^{\circ}\text{C} \times \frac{\text{cm}^2}{\text{W}} / \theta{\text{JC}}$$

As a result, approximately 6 square cm of 1 oz copper on top and bottom layers is required for the PCB design. Additional area will decrease die temperature proportionately. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty six, 8mils thermal vias spaced 59mils (1.5 mm) apart must connect the top copper to the bottom copper. For an example of a high thermal performance PCB layout of approximately 31 square cm area. Refer to the Evaluation Board application note AN-2024 SNVA422. For more information on thermal design see AN-2020 SNVA419 and AN-2026 SNVA424.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.