LCMXO2-640ZE

Part: MachXO2 Family Type: Non-volatile Programmable Logic Device (PLD)

Key Specs:

• LUTs: 256 to 6864
• I/Os: 18 to 334
• Standby Power: As low as 22 μW
• Process Technology: 65 nm
• User Flash Memory: Up to 256 kbits
• Embedded Block RAM

Flexible Logic Architecture

• Six devices with 256 to 6864 LUT4s and 18 to 334 I/Os

Ultra Low Power Devices

• Advanced 65 nm low power process
• As low as 22 μW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options

Embedded and Distributed Memory

• Up to 240 kbits sysMEM™ Embedded Block RAM
• Up to 54 kbits Distributed RAM
• Dedicated FIFO control logic

On-Chip User Flash Memory

• Up to 256 kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I2 C and JTAG interfaces
• Can be used as soft processor PROM or as Flash memory

Pre-Engineered Source Synchronous I/O

• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with DQS support

High Performance, Flexible I/O Buffer

• Programmable sysIO™ buffer supports wide range of interfaces:
  • LVCMOS 3.3/2.5/1.8/1.5/1.2
  • LVTTL
  • PCI
  • LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
  • SSTL 25/18
  • HSTL 18
  • Schmitt trigger inputs, up to 0.5 V hysteresis
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode

Flexible On-Chip Clocking

• Eight primary clocks
• Up to two edge clocks for high-speed I/O interfaces (top and bottom sides only)
• Up to two analog PLLs per device with fractional-n frequency synthesis
  • Wide input frequency range (7 MHz to 400 MHz)

Non-volatile, Infinitely Reconfigurable

• Instant-on powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I2 C
• Supports background programming of non-volatile memory
• Optional dual boot with external SPI memory

TransFR™ Reconfiguration

• In-field logic update while system operates

Enhanced System Level Support

• On-chip hardened functions: SPI, I2 C, timer/ counter
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• One Time Programmable (OTP) mode
• Single power supply with extended operating range
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming

Broad Range of Package Options

• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA, QFN package options
• Small footprint package options
  • As small as 2.5 mm x 2.5 mm
• Density migration supported
• Advanced halogen-free packaging

Table 1-1. MachXO2™ Family Selection Guide

		XO2-256	XO2-640	XO2-640U 1	XO2-1200	XO2-1200U 1	XO2-2000	XO2-2000U 1	XO2-4000	XO2-7000
LUTs		256	640	640	1280	1280	2112	2112	4320	6864
Distributed RAM (I	kbits)	2	5	5	10	10	16	16	34	54
EBR SRAM (kbits)	)	0	18	64	64	74	74	92	92	240
Number of EBR S (9 kbits/block)	RAM Blocks	0	2	7	7	8	8	10	10	26
UFM (kbits)		0	24	64	64	80	80	96	96	256
Device Options:	HC 2	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes
	HE 3						Yes	Yes	Yes	Yes
	ZE 4	Yes	Yes		Yes		Yes		Yes	Yes
Number of PLLs	•	0	0	1	1	1	1	2	2	2
Hardened	I2C	2	2	2	2	2	2	2	2	2
Functions:	SPI	1	1	1	1	1	1	1	1	1
	Timer/ Counter	1	1	1	1	1	1	1	1	1
Packages					I	Ю	I
25-ball WLCSP 5 (2.5 mm x 2.5 mm	, 0.4 mm)				18
32 QFN 6 (5 mm x 5 mm, 0.5 mm)		21
49-ball WLCSP 5 (3.2 mm x 3.2 mm	, 0.4 mm)						38
64-ball ucBGA (4 mm x 4 mm, 0.4	4 mm)	44
100-ball TQFP (14 mm x 14 mm)		55	78		79		79
132-ball csBGA (8 mm x 8 mm, 0.5	5 mm)	55	79		104		104		104
144-ball TQFP (20 mm x 20 mm)				107	107		111		114	114
184-ball csBGA 7 (8 mm x 8 mm, 0.5	5 mm)								150
256-ball caBGA (14 mm x 14 mm,	0.8 mm)						206		206	206
256-ball ftBGA (17 mm x 17 mm,	1.0 mm)					206	206		206	206
332-ball caBGA (17 mm x 17 mm,	0.8 mm)								274	278
484-ball ftBGA (23 mm x 23 mm,	1.0 mm)							278	278	334

• 1. Ultra high I/O device.
• 1. High performance with regulator VCC = 2.5 V, 3.3 V

• High performance without regulator V_CC = 1.2 V Low power without regulator V_CC = 1.2 V

• 1. WLCSP package only available for ZE devices.6. QFN package only available for HC and ZE devices.
• 1. 184 csBGA package only available for HE devices.

Introduction

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I²C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.

The MachXO2 devices are designed on a 65 nm non-volatile low power process. The device architecture has several features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family.

The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices. The ultra low power devices are offered in three speed grades –1, –2 and –3, with –3 being the fastest. Similarly, the high-performance devices are offered in three speed grades: –4, –5 and –6, with –6 being the fastest. HC devices have an internal linear voltage regulator which supports external V_CC supply voltages of 3.3 V or 2.5 V. ZE and HE devices only accept 1.2 V as the external V_CC supply voltage. With the exception of power supply voltage all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other.

The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5 mm x 2.5 mm WLCSP to the 23 mm x 23 mm fpBGA. MachXO2 devices support density migration within the same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.

The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os.

The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a "per-pin" basis.

A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and similar state machines.

The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the I²C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash memory) and remote field upgrade (TransFR) capability.

Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification.

Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increasing their productivity.

Symbol	Parameter	Condition	Min.	Typ.	Max.	Units
		Clamp OFF and V CCIO < V IN < V IH (MAX)	_	_	+175	μΑ
		Clamp OFF and V IN = V CCIO	-10	_	10	μΑ
I IL , I IH 1, 4	Input or I/O Leakage	Clamp OFF and Vrm CCIO –0.97 V < Vrm IN < Vrm CCIO	-175	_	_	μΑ
		Clamp OFF and 0 V < V IN < V CCIO -0.97 V	_		10	μΑ
		Clamp OFF and V IN = GND	_		10	μΑ
		Clamp ON and 0 V < V IN < V CCIO	_		10	μΑ
I PU	I/O Active Pull-up Current	0 < V IN < 0.7 V CCIO	-30	_	-309	μΑ
I PD	I/O Active Pull-down Current	V IL (MAX) < V IN < V CCIO	30	_	305	μΑ
I BHLS	Bus Hold Low sustaining current	VIN = VIL (MAX)	30	_	_	μΑ
I BHHS	Bus Hold High sustaining current	V IN = 0.7V CCIO	-30	_	_	μΑ
I BHLO	Bus Hold Low Overdrive current	0 ≤ VIN ≤ VCCIO		_	305	μΑ
I вннo	Bus Hold High Overdrive current	0 ≤ VIN ≤ VCCIO	_	_	-309	μΑ
V BHT 3	Bus Hold Trip Points		V IL (MAX)	_	V IH (MIN)	V
C1	I/O Capacitance 2	VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, VCC = Typ., VIO = 0 to VIH (MAX)	3	5	9	pf
C2	Dedicated Input Capacitance 2	VCCIO = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, VCC = Typ., VIO = 0 to VIH (MAX)	3	5.5	7	pf
		V CCIO = 3.3 V, Hysteresis = Large	_	450	_	mV
		V CCIO = 2.5 V, Hysteresis = Large	_	250	_	mV
		V CCIO = 1.8 V, Hysteresis = Large	_	125	_	mV
V	Hysteresis for Schmitt	V CCIO = 1.5 V, Hysteresis = Large	_	100	_	mV
V HYST	Trigger Inputs 5	V CCIO = 3.3 V, Hysteresis = Small	_	250	_	mV
		V CCIO = 2.5 V, Hysteresis = Small	_	150	_	mV
		V CCIO = 1.8 V, Hysteresis = Small	_	60	_	mV
		V CCIO = 1.5 V, Hysteresis = Small	_	40		mV

^1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled.

^2. T_A 25 °C, f = 1.0 MHz.

^3. Please refer to V_IL and V_IH in the sysIO Single-Ended DC Electrical Characteristics table of this document.

^4. When V_IH is higher than V_CCIO, a transient current typically of 30 ns in duration or less with a peak current of 6 mA can occur on the high-to-low transition. For true LVDS output pins in MachXO2-640U, MachXO2-1200/U and larger devices, V_IH must be less than or equal to V_CCIO.

^5. With bus keeper circuit turned on. For more details, refer to TN1202, MachXO2 sysIO Usage Guide.

	MachXO2 ZE/HE (1.2 V)	MachXO2 HC (2.5 V / 3.3 V)
Supply Voltage VCC–0.5 V to 1.32 V–0.5 V to 3.75 V
Output Supply Voltage VCCIO–0.5 V to 3.75 V–0.5 V to 3.75 V
I/O Tri-state Voltage Applied5	–0.5 V to 3.75 V–0.5 V to 3.75 V
Dedicated Input Voltage Applied–0.5 V to 3.75 V–0.5 V to 3.75 V
Storage Temperature (Ambient) –55 °C to 125 °C –55 °C to 125 °C
Junction Temperature (TJ) –40 °C to 125 °C –40 °C to 125 °C

• 1. Compliance with the Lattice Thermal Management document is required.
• 1. All voltages referenced to GND.
• 1. Overshoot and undershoot of –2 V to (VIHMAX + 2) volts is permitted for a duration of <20 ns.
• 1. The dual function I2 C pins SCL and SDA are limited to –0.25 V to 3.75 V or to –0.3 V with a duration of <20 ns.

Symbol	Parameter	Min.	Max.	Units
	Core Supply Voltage for 1.2 V Devices	1.14	1.26	V
VCC1	Core Supply Voltage for 2.5 V / 3.3 V Devices	2.375	3.6	V
VCCIO1, 2, 3	I/O Driver Supply Voltage	1.14	3.6	V
tJCOM	Junction Temperature Commercial Operation	0	85	°C
tJIND	Junction Temperature Industrial Operation	–40	100	°C

^1. Like power supplies must be tied together. For example, if VCCIO and VCC are both the same voltage, they must also be the same supply.

Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Users must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values.

For Further Information

For further information regarding Thermal Management, refer to the following:

• Thermal Management document
• TN1198, Power Estimation and Management for MachXO2 Devices
• The Power Calculator tool is included with the Lattice design tools, or as a standalone download from www.latticesemi.com/software