LCMXO2-640HC

Part: MachXO2™ Family — Lattice Semiconductor Type: Ultra Low Power, Instant-On, Non-Volatile PLD (Programmable Logic Device) Description: A family of ultra low power, instant-on, non-volatile PLDs with densities from 256 to 6864 LUTs, featuring embedded block RAM, distributed RAM, user flash memory, PLLs, and hardened SPI, I2C, and timer/counter functions.

Operating Conditions:

• Supply voltage: 1.2 V (ZE, HE devices), 2.5 V or 3.3 V (HC devices)
• Standby power: As low as 22 μW
• PLL input frequency range: 7 MHz to 400 MHz

Absolute Maximum Ratings:

Key Specs:

• Logic Density: 256 to 6864 LUT4s
• I/O Count: 18 to 334 I/Os
• Embedded Block RAM (EBR): Up to 240 kbits
• Distributed RAM: Up to 54 kbits
• User Flash Memory (UFM): Up to 256 kbits
• UFM Write Cycles: 100,000
• On-chip Oscillator Accuracy: 5.5%
• PLLs per device: Up to two

Features:

• Flexible Logic Architecture with LUT4s
• Ultra Low Power Devices (65 nm process, 22 μW standby)
• Embedded and Distributed Memory (sysMEM EBR, Distributed RAM, dedicated FIFO logic)
• On-Chip User Flash Memory (WISHBONE, SPI, I2C, JTAG access)
• Pre-Engineered Source Synchronous I/O (DDR registers, gearing logic, DQS support)
• High Performance, Flexible I/O Buffer (LVCMOS, LVTTL, PCI, LVDS, HSTL, SSTL, Schmitt trigger, hot socketing, on-chip termination, pull-up/down)
• Flexible On-Chip Clocking (Eight primary clocks, two edge clocks, two analog PLLs)
• Non-volatile, Infinitely Reconfigurable (Instant-on, JTAG, SPI, I2C programming, background programming, dual boot)
• TransFR™ Reconfiguration (In-field logic update)
• Enhanced System Level Support (Hardened SPI, I2C, timer/counter, on-chip oscillator, TraceID, OTP mode, single power supply, IEEE 1149.1, IEEE 1532)
• Broad Range of Package Options (TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA, QFN)

Applications:

• Low cost, high volume consumer applications
• System applications

Package:

• 25-ball WLCSP (2.5 mm x 2.5 mm, 0.4 mm)
• 32 QFN (5 mm x 5 mm, 0.5 mm)
• 48 QFN (7 mm x 7 mm, 0.5 mm)
• 49-ball WLCSP (3.2 mm x 3.2 mm, 0.4 mm)
• 64-ball ucBGA (4 mm x 4 mm, 0.4 mm)
• 84 QFN (7 mm x 7 mm, 0.5 mm)
• 100-pin TQFP (14 mm x 14 mm)
• 132-ball csBGA (8 mm x 8 mm, 0.5 mm)
• 144-pin TQFP (20 mm x 20 mm)
• 184-ball csBGA (8 mm x 8 mm, 0.5 mm)
• 256-ball caBGA (14 mm x 14 mm, 0.8 mm)
• 256-ball ftBGA (17 mm x 17 mm, 1.0 mm)
• 332-ball caBGA (17 mm x 17 mm, 0.8 mm)
• 484-ball ftBGA (23 mm x 23 mm, 1.0 mm)

• Flexible Logic Architecture

• Six devices with 256 to 6864 LUT4s and 18 to 334 I/Os

• Ultra Low Power Devices

• Advanced 65 nm low power process

• As low as 22 μW standby power

• Programmable low swing differential I/Os

• Stand-by mode and other power saving options

• Embedded and Distributed Memory

• Up to 240 kbits sysMEM™ Embedded Block RAM

• Up to 54 kbits Distributed RAM

• Dedicated FIFO control logic

Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Users must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values.