KSZ8081RND
Ethernet Physical-Layer TransceiverThe KSZ8081RND is a ethernet physical-layer transceiver from Micrel Inc.. View the full KSZ8081RND datasheet below including electrical characteristics, absolute maximum ratings.
Manufacturer
Micrel Inc.
Category
Ethernet Physical-Layer Transceiver
Overview
Part: KSZ8081RNA/RND — Microchip Type: 10BASE-T/100BASE-TX Ethernet PHY Transceiver Description: Single-chip 10BASE-T/100BASE-TX IEEE 802.3 compliant Ethernet transceiver with RMII v1.2 interface support, integrated 1.2V regulator, and flexible 1.8V, 2.5V, or 3.3V digital I/O options.
Operating Conditions:
- Supply voltage: 3.3V (single supply)
- I/O voltage: 1.8V, 2.5V, or 3.3V
- Reference clock: 25 MHz or 50 MHz
Absolute Maximum Ratings:
Key Specs:
- Ethernet compliance: IEEE 802.3 (10BASE-T/100BASE-TX)
- Interface: RMII v1.2
- ESD rating (HBM): 6 kV
- Crystal input: 25 MHz ±50 ppm (KSZ8081RNA default)
- Oscillator/external clock input: 25 MHz ±50 ppm or 50 MHz ±50 ppm (KSZ8081RND default 50 MHz)
- REXT resistor: 6.49 kΩ to ground
- MDIO/INTRP pull-up resistor: 1.0 kΩ (external)
Features:
- RMII back-to-back mode support for 100 Mbps copper repeater
- MDC/MDIO management interface
- Programmable interrupt output
- LED outputs for Link and Activity status
- On-chip termination resistors for differential pairs
- HP Auto MDI/MDI-X
- Auto-Negotiation (10/100 Mbps, Half/Full Duplex)
- Power-Down and Power-Saving modes
- LinkMD® TDR-Based Cable Diagnostics
- Parametric NAND Tree Support
- Loopback Modes for Diagnostics
- Built-in 1.2V regulator for core
Applications:
- Game Consoles
- IP Phones
- IP Set-Top Boxes
- IP TVs
- LOM
- Printers
Package:
- 24-pin 4 mm x 4 mm QFN
Features
- Single-Chip 10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet Transceiver
- RMII v1.2 Interface Support with a 50 MHz Reference Clock Output to MAC, and an Option to Input a 50 MHz Reference Clock
- RMII Back-to-Back Mode Support for a 100 Mbps Copper Repeater
- MDC/MDIO Management Interface for PHY Register Configuration
- Programmable Interrupt Output
- LED Outputs for Link and Activity Status Indication
- On-Chip Termination Resistors for the Differential Pairs
- Baseline Wander Correction
- HP Auto MDI/MDI-X to Reliably Detect and Correct Straight-Through and Crossover Cable Connections with Disable and Enable Option
- Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100 Mbps) and Duplex (Half/Full)
- Power-Down and Power-Saving Modes
- LinkMD ® TDR-Based Cable Diagnostics to Identify Faulty Copper Cabling
- Parametric NAND Tree Support for Fault Detection Between Chip I/Os and the Board
- HBM ESD Rating (6 kV)
- Loopback Modes for Diagnostics
- Single 3.3V Power Supply with V DD I/O Options for 1.8V, 2.5V, or 3.3V
- Built-In 1.2V Regulator for Core
- Available in 24-pin 4 mm x 4 mm QFN Package
Applications
- Game Consoles
- IP Phones
- IP Set-Top Boxes
- IP TVs
- LOM
- Printers
Pin Configuration
FIGURE 2-1: 24-QFN PIN ASSIGNMENT (TOP VIEW)
Electrical Characteristics
T A = 25°C. Specification is for packaged product only.
TABLE 6-1: ELECTRICAL CHARACTERISTICS
| Parameters | Symbol | Min. | Typ. | Max. | Units | Note |
|---|---|---|---|---|---|---|
| Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 | Supply Current (V DDIO , V DDA_3.3 = 3.3V), Note 6-1 |
| 10BASE-T | I DD1_3.3V | - | 41 | - | mA | Full-duplex traffic @100% utilization |
| 100BASE-TX | I DD2_3.3V | - | 47 | - | mA | Full-duplex traffic @100% utilization |
| EDPD Mode | I DD3_3.3V | - | 20 | - | mA | Ethernet cable disconnected (Reg. 18h.11 = 0) |
| Power-Down Mode | I DD4_3.3V | - | 4 | - | mA | Software power-down (Reg. 0h.11 = 1) |
| CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs | CMOS Level Inputs |
| Input High Voltage | V IH | 2.0 | - | - | V | V DDIO = 3.3V |
| Input High Voltage | V IH | 1.8 | - | - | V | V DDIO = 2.5V |
| Input High Voltage | V IH | 1.3 | - | - | V | V DDIO = 1.8V |
| Input Low Voltage | V IL | - | - | 0.8 | V | V DDIO = 3.3V |
| Input Low Voltage | V IL | - | - | 0.7 | V | V DDIO = 2.5V |
| Input Low Voltage | V IL | - | - | 0.5 | V | V DDIO = 1.8V |
| Input Current | \ | I IN \ | - | - | 10 | |
| CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs | CMOS Level Outputs |
| Output High Voltage | V OH | 2.4 | - | - | V | V DDIO = 3.3V |
| Output High Voltage | V OH | 2.0 | - | - | V | V DDIO = 2.5V |
| Output High Voltage | V OH | 1.5 | - | - | V | V DDIO = 1.8V |
| Output Low Voltage | V OL | - | - | 0.4 | V | V DDIO = 3.3V |
| Output Low Voltage | V OL | - | - | 0.4 | V | V DDIO = 2.5V |
| Output Low Voltage | V OL | - | - | 0.3 | V | V DDIO = 1.8V |
| Output Tri-State Leakage | \ | I OZ \ | - | - | 10 | |
| LED Output | LED Output | LED Output | LED Output | LED Output | LED Output | LED Output |
| Output Drive Current | I LED | - | 8 | - | mA | LED0 pin |
| All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) | All Pull-Up/Pull-Down Pins (including Strapping Pins) |
| Internal Pull-Up Resistance | 30 | 45 | 73 | k Ω | V DDIO = 3.3V | |
| Internal Pull-Up Resistance | pu | 39 | 61 | 102 | k Ω | V DDIO = 2.5V |
| Internal Pull-Up Resistance | 48 | 99 | 178 | k Ω | V DDIO = 1.8V | |
| Internal Pull-Down Resistance | pd | 26 | 43 | 79 | k Ω | V DDIO = 3.3V |
| Internal Pull-Down Resistance | pd | 34 | 59 | 113 | k Ω | V DDIO = 2.5V |
| Internal Pull-Down Resistance | pd | 53 | 99 | 200 | k Ω | V DDIO = 1.8V |
| 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) | 100BASE-TX Transmit (measured differentially after 1:1 transformer) |
| Peak Differential Output Voltage | V O | 0.95 | - | 1.05 | V | 100 Ω termination across differential output |
| Output Voltage Imbalance | V IMB | - | - | 2 | % | 100 Ω termination across differential output |
| Rise/Fall Time | t r /t f | 3 | - | 5 | ns | - |
| Rise/Fall Time Imbalance | - | 0 | - | 0.5 | ns | - |
| Duty Cycle Distortion | - | - | - | ±0.25 | ns | - |
| Overshoot | - | - | - | 5 | % | - |
| Output Jitter | - | - | 0.7 | - | ns | Peak-to-peak |
TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
| Parameters | Symbol | Min. | Typ. | Max. | Units | Note |
|---|---|---|---|---|---|---|
| 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) | 10BASE-T Transmit (measured differentially after 1:1 transformer) |
| Peak Differential Output Voltage | V P | 2.2 | - | 2.8 | V | 100 Ω termination across differential output |
| Jitter Added | - | - | - | 3.5 | ns | Peak-to-peak |
| Rise/Fall Time | t r /t f | - | 25 | - | ns | - |
| 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive | 10BASE-T Receive |
| Squelch Threshold | V SQ | - | 400 | - | mV | 5 MHz square wave |
| Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting | Transmitter - Drive Setting |
| Reference Voltage of I SET | V SET | - | 0.65 | - | V | R(I SET ) = 6.49 k Ω |
| REF_CLK Output | REF_CLK Output | REF_CLK Output | REF_CLK Output | REF_CLK Output | REF_CLK Output | REF_CLK Output |
| 50 MHz RMII Clock Output Jitter | - | - | 300 | - | ps | Peak-to-peak. Applies only to RMII - 25 MHz Clock Mode. |
| 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters | 100 Mbps Mode - Industrial Applications Parameters |
| Link Loss Reaction (Indication) Time | t llr | - | 4.4 | - | μ s | Link loss detected at receive differential inputs to PHY signal indication time for each of the following: 1. For LED mode 01, Link LED output changes from low (link-up) to high (link-down). 2. INTRP pin asserts for link-down status change. |
Note 6-1 Current consumption is for the single 3.3V supply KSZ8081RNA/RND device only, and includes the transmit driver current and the 1.2V supply voltage (V DD_1.2 ) that are supplied by the KSZ8081RNA/ RND.
Absolute Maximum Ratings
- (V DD_1.2 )....................................................................................................................................................-0.5V to +1.8V
- (V DDIO , V DDA_3.3 ) ......................................................................................................................................-0.5V to +5.0V
- Input Voltage (all inputs)............................................................................................................................-0.5V to +5.0V
- Output Voltage (all outputs).......................................................................................................................-0.5V to +5.0V
- Lead Temperature (soldering, 10s) .......................................................................................................................+260°C
- Storage Temperature (T S )......................................................................................................................-55°C to +150°C
*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Package Information
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
Related Variants
The following components are covered by the same datasheet.
| Part Number | Manufacturer | Package |
|---|---|---|
| KSZ8081 | Microchip Technology | — |
| KSZ8081MLX | Microchip Technology | 48-pin 7 mm x 7 mm LQFP |
| KSZ8081RNA | Micrel Inc. | — |
| KSZ8081RNA/RND | Microchip Technology | — |
| KSZ8081RNACA | Microchip Technology | 24-VFQFN Exposed Pad |
| KSZ8081RNAIA | Microchip Technology | — |
| KSZ8081RNB | Microchip Technology | 32-Pin QFN |
| KSZ8081RNDCA | Microchip Technology | — |
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